JP5772308B2 - Switching element protection circuit - Google Patents

Description

  The present invention relates to a protection circuit for a switching element that protects the switching element from destruction.

  Conventionally, a field effect transistor (hereinafter referred to as a “nitride FET”) including a nitride semiconductor layer in which gallium nitride (GaN) and aluminum gallium nitride (AlGaN) are stacked, for example, as a high frequency device or a high voltage power device. ) Has been put to practical use. For example, a nitride FET (Schottky gate type nitride FET) having a gate electrode arranged by forming a Schottky junction in a nitride semiconductor layer, or a gate arranged via an insulating film on the nitride semiconductor layer Various integrated circuits using MIS (Metal Insulator Semiconductor) structure nitride FETs (MIS gate type nitride FETs) having electrodes have been proposed (for example, see Patent Document 1).

  Nitride FETs have a low surge resistance, as shown in Patent Document 2, for example. For this reason, as shown in FIG. 6, a protective diode having a lower withstand voltage than the nitride FET is disposed between the drain and the gate. As a circuit in which a protective diode is arranged, power using a protection device (Patent Document 3) for a semiconductor device having a protection function for protecting the semiconductor device from high-speed surges, or a voltage-driven switching element such as a MOS transistor A conversion device (Patent Document 4) and the like are known.

  In the circuit shown in FIG. 6, the basic operation when an overvoltage such as a surge is applied to the drain is as follows. That is, when an overvoltage is applied to the drain of the switching element, the clamping diode breaks and current is supplied to the gate of the switching element, and the switching element is turned on. By using the clamping diode, the switching element is turned on simultaneously with the break to absorb the surge, so that the switching element can be prevented from being destroyed.

  Here, the reason why the gate voltage increases until the switching element can be turned on during the break of the diode is that the gate resistance RG is inserted. The gate voltage VG at the time of the break is a product of the diode current I (diode) and the gate resistance RG, that is, “VG = I (diode) * RG”. Since the gate resistance RG is large to some extent, the switching element can be turned on.

JP 2008-187167 A JP 2008-276741 A JP 2001-44291 A JP 2001-245466 A

  However, the conventional switching element protection circuit described above increases the gate resistance RG for turning on the switching element when a surge voltage is applied in order to prevent the switching element from being destroyed from the surge voltage. Although the gate resistor RG has an effect of preventing oscillation and noise, there is a problem in that since the current during switching of the switching element is limited, the switching time becomes long and the switching element cannot be operated at high speed.

  When a conventional BIP (Bipolar transistor), MOS (Metal Oxide Semiconductor), or IGBT (Insulated Gate Bipolar Transistor) is used as a switching element, the required switching speed is obtained even when a gate resistance is present. A compound semiconductor device typified by a nitride FET is required to have a switching speed higher than the conventional one. In order to maximize the characteristics of the switching element, it is desirable to reduce the gate resistance to zero or as small as possible. However, in a conventional switching element protection circuit, if the circuit method is used as it is and the gate resistance is reduced to zero or small, the clamping operation cannot be performed. This is because the gate voltage at the time of clamping is raised using the gate resistance RG.

  In addition, the characteristics of the protection circuit of the switching element before the gate resistance are also important. For example, when the protection circuit of the switching element is composed of an IC and the internal drive circuit is composed of a MOS-FET, the circuit configuration is generally as shown in FIG. Yes. In this circuit, the switching element Tr1 is turned off by turning on the transistor M2 in the IC, but the on-resistance Ron (M2) of the transistor M2 is also important. When the switching element is turned off, the on-resistance Ron (M2) of the transistor M2 is also added to the gate resistance RG as a resistance component. Therefore, it is necessary to reduce the on-resistance Ron (M2) of the transistor M2 for high-speed switching.

  Here, assuming that the threshold voltage Vth of the GaN-FET is about 1.5V and RG + Ron (M2) = 1Ω, a current of about 1.5 A is required to make the gate voltage VG 1.5V. It is practically impossible to employ a protective diode for passing an ampere-order current due to problems such as cost, and it is particularly difficult when a diode is created inside an IC. If RG + Ron (M2) = 20Ω is set, the diode current becomes 75 mA, but the high-speed switching required for the GaN-FET cannot be realized.

  Another reason why a circuit configuration with zero gate resistance is desired is that the nitride FET element itself can perform a diode-like regenerative operation. When the gate-source of the nitride FET is short-circuited, as shown in FIG. 7, the source is the anode terminal, the drain is the cathode terminal, and the threshold voltage Vth of the nitride FET can be regarded as a forward voltage VF. It becomes a characteristic. When the gate resistance exists, the gate-source voltage is opened during the regenerative operation, and the drain-source voltage is also opened.

  An object of the present invention is to provide a protection circuit for a switching element that can perform a high-speed switching operation of a nitride FET and can protect the nitride FET from a surge voltage.

In order to solve the above problems, a protection circuit for a switching element according to the present invention includes a high-voltage side element and a low-voltage side element connected in series, a high-side pre-driver that outputs a signal for turning on and off the high-voltage side element, A low-side pre-driver that outputs a signal for turning on and off the low-voltage element so as to be in an on / off state opposite to the high-voltage side element; a main switching element having a control terminal connected to a connection point between the high-voltage side element and the low-voltage side element; A sub switching element whose control terminal is connected to the connection point between the high-voltage side element and the low-voltage side element via a resistor, a diode having a cathode connected to one terminal of the main switching element, and an input terminal to the anode of the diode There are connected, supplies the current to the control terminal of the sub-switching element at a break of the diode, the low pressure side element A signal indicating off and a low side controller supplies the pre-driver, the current to the control terminal of the main switching element by turning off the low-pressure side element by the low-side pre-driver receiving a low-side off-signal from the controller It is characterized by supplying .

  According to the protection circuit for a switching element according to the present invention, the nitride FET can be switched at a high speed, and the nitride FET can be protected from a surge voltage.

It is a circuit diagram which shows the structure of the protection circuit of the switching element which concerns on Example 1 of this invention. It is a circuit diagram which shows the structure of the modification of the protection circuit of the switching element which concerns on Example 1 of this invention. It is a circuit diagram which shows the specific structure of a high side predriver, a low side predriver, and a controller. It is a circuit diagram which shows the structure of the protection circuit of the switching element which concerns on Example 2 of this invention. It is a circuit diagram which shows the structure of the protection circuit of the switching element which concerns on Example 3 of this invention. It is a figure for demonstrating the protection circuit of the conventional switching element. It is a figure which shows the relationship between the drain-source voltage and drain current of GAN-FET.

  Hereinafter, a protection circuit for a switching element according to an embodiment of the present invention will be described in detail.

  However, it should be noted that the drawings are schematic. In addition, the examples shown below exemplify apparatuses and methods for embodying the technical idea of the present invention, and the embodiments of the present invention have various modifications within the scope of the claims. May be.

  1 is a block diagram illustrating a basic configuration of a protection circuit for a switching element according to a first embodiment of the present invention. The protection circuit for the switching element includes a transistor M1 (PMOS), a transistor M2 (NMOS), a high-side predriver 11, a low-side predriver 12, a controller 21, a diode D1, a transistor Tr1, an input terminal IN, a high voltage terminal VDD, a low A voltage terminal VSS, a drain terminal DRAIN, and a gate terminal GATE are provided. Note that the transistor M1, the transistor M2, the high-side predriver 11 and the low-side predriver 12 correspond to the conventional drive circuit shown in FIG.

  The high-side transistor M1 corresponds to the high-voltage side element of the present invention. The drain of the transistor M1 is connected to the high voltage terminal VDD, the source is connected to the drain of the transistor M2, and the gate is connected to the output terminal of the high side pre-driver 11.

  The low-side transistor M2 corresponds to the low-voltage side element of the present invention. The drain of the transistor M2 is connected to the source of the transistor M1, the source is connected to the low voltage terminal VSS, and the gate is connected to the output terminal of the low-side predriver 12.

  The high-side pre-driver 11 performs a predetermined process on the signal input from the input terminal IN and sends it to the gate of the transistor M1. Details of the high-side pre-driver 11 will be described later.

  The low-side pre-driver 12 sends a signal obtained by performing a predetermined process on a signal input from the input terminal IN or a low-side off signal input from the controller 21 to the input terminal Loff to the gate of the transistor M2. Details of the low-side pre-driver 12 will be described later.

  The input terminal of the controller 21 is connected to the anode of the clamping diode D1, and the cathode of the diode D1 is connected to the drain terminal DRAIN. Details of the controller 21 will be described later.

  The first output terminal 01 of the controller 21 is connected to a gate current supply line connecting the connection point between the source of the transistor M1 and the drain of the transistor M2 and the gate of the transistor Tr1, and supplies a gate current to the gate current supply line. . The second output terminal 02 of the controller 21 is connected to the input terminal Loff of the low-side pre-driver 12 and outputs a low-side off signal for turning off only the low-side transistor M2. Further, the third output terminal 03 of the controller 21 is connected to the negative power supply voltage terminal VSS.

  The potential of the negative power supply voltage terminal VSS is set lower than the potential of the high voltage terminal VDD such as a ground potential or a negative potential.

  The transistor Tr1 corresponds to the switching element of the present invention, and is composed of, for example, a nitride FET. The drain of the transistor Tr1 is connected to the drain terminal DRAIN, the source is grounded, and the gate is connected to the gate current supply line. The gate current supply line is provided with a gate terminal GATE.

  In addition, as shown in FIG. 2, it can also deform | transform so that the diode D2 may be provided between the 1st output terminal 01 of the controller 21, and a gate current supply line. In the case of this modification, the anode of the diode D2 is connected to the first output terminal 01 of the controller 21, and the cathode is connected to the gate current supply line. Further, a resistor may be provided instead of the diode D2.

  FIG. 3 is a circuit diagram showing a specific configuration of the high-side predriver 11, the low-side predriver 12, and the controller 21.

  The high-side pre-driver 11 and the low-side pre-driver 12 generate a dead time when switching between the transistor M1 and the transistor M2 so that no through current flows through the transistor M1 (PMOS) and the transistor M2 (NMOS).

  Specifically, the high-side pre-driver 11 inputs a signal obtained by inverting the signal from the input terminal IN by the inverter 31, and this input signal and the input signal are formed between the two inverters 32 and 33. The signal delayed by the time constant circuit composed of the resistor R2 and the capacitor C2 is input to the NOR circuit 34.

  The NOR circuit 34 takes the logical product of these signals with negative logic and outputs the result. The signal output from the NOR circuit 34 is inverted by the inverter 35 and then output to the outside via the buffer 36. The delay time is determined according to the time constant of the resistor R2 and the capacitor C2. A signal output from the high-side pre-driver 11 is applied to the gate of the transistor M1.

  The low-side pre-driver 12 receives a signal obtained by inverting the signal from the input terminal IN by the inverter 31, and inputs the input signal and a resistor R3 formed between the two inverters 37 and 38. The signal delayed by the time constant circuit composed of the capacitor C3 is input to the NAND circuit 39. The NAND circuit 39 takes the logical product of these in positive logic and outputs the result. The signal output from the NAND circuit 39 is inverted by the NOR circuit 40 and then output to the outside via the buffer 41. The delay time is determined according to the time constant of the resistor R3 and the capacitor C3. A signal output from the low-side pre-driver 12 is applied to the gate of the transistor M2.

  Each of the signal output from the high-side pre-driver 11 and the signal output from the low-side pre-driver 12 changes after a predetermined time from when the signal input to the input terminal IN changes. Therefore, the timing at which the signal output from the high-side pre-driver 11 starts changing and the timing at which the signal output from the low-side pre-driver 12 starts changing are shifted by a certain time (dead time). As a result, the transistor M1 and the transistor M2 are not turned on at the same time, so that no through current flows through the transistor M1 and the transistor M2. The dead time can be adjusted by the time constant of the time constant circuit.

  The controller 21 employs a circuit system that can supply a current to the gate of the switching element Tr1 using only a diode current in order to protect surges even when the switching element protection circuit is not powered. . The controller 21 includes a current mirror circuit including a PNP transistor Q1 and a PNP transistor Q2.

  The emitters of the transistors Q1 and Q2 are connected to the drain terminal DRAIN via the diode D1. The bases of the transistors Q1 and Q2 are connected, and the collector of the transistor Q1 is connected to the base. The collector of the transistor Q1 is further connected to the gate current supply line via the resistor R1, and the gate current supply line is connected to the first output terminal 01.

  The collector of the transistor Q2 is connected to the low voltage terminal VSS via the series circuit of the resistors R4 and R5 and the third output terminal 03. The controller 21 is provided with a transistor M3. The drain of the transistor M3 is connected to the high voltage terminal VDD via the resistor R6, and the source is connected to the low voltage terminal VSS via the third output terminal 03. The gate of the transistor M3 is connected to a connection point between the resistor R4 and the resistor R5. The drain of the transistor M3 is connected to the second output terminal 02 via the inverter 42, and outputs a low side off signal. The second output terminal 02 is connected to the input terminal Loff of the low-side pre-driver 12, specifically, one input terminal of the NOR circuit 40.

  Next, the surge protection operation of the nitride FET by the protection circuit of the switching element configured as described above will be described with reference to the circuit diagram shown in FIG.

  First, a clamp operation when a voltage is supplied to the high voltage terminal VDD and the protection circuit of the switching element is operating will be described. When the diode D1 breaks due to the surge voltage being applied and the breakdown voltage is exceeded, current is supplied from the resistor R1 inside the controller 21 to the gate current supply line via the first output terminal 01. At this time, since a current also flows through the mirror circuit of the transistors Q1 and Q2, a divided voltage of the resistors R4 and R5 is applied to the gate of the transistor M3. For this reason, the transistor M3 is turned on, and the input side of the inverter 42 becomes L level. The L level is inverted by the inverter 42 and the H level is sent to the input terminal Loff of the low side pre-driver 12 via the second output terminal 02 as a low side off signal. That is, since the H level is input to the NOR circuit 40, the output of the NOR circuit 40 becomes the L level, and an L level signal is sent from the output terminal of the low-side predriver 12 to the gate of the transistor M2 via the buffer 41. The transistor M2 is turned off. As a result, an H level signal is supplied to the gate of the transistor Tr1, and the transistor Tr1 is turned on.

  Thus, since the controller 21 outputs the low side off signal for turning off the transistor M2 when the diode D1 breaks, the active clamping operation is performed without any problem.

  Next, a clamp operation when a voltage is not supplied to the high voltage terminal VDD and the switching element protection circuit is not operating will be described. When the diode D1 breaks due to the surge voltage being applied and the breakdown voltage is exceeded, current is supplied from the resistor R1 inside the controller 21 to the gate current supply line via the first output terminal 01. However, since the transistors M1 and M2 are off, the gate potential of the transistor Tr1 rises and an H level voltage is applied. As a result, the transistor Tr1 is turned on.

  Thus, the controller 21 outputs a low-side off signal for supplying current to the gate current supply line and turning off the low-side transistor M2 together with the break of the diode D1. Therefore, even when no voltage is applied to the high voltage terminal VDD of the protection circuit for the switching element, a current is supplied through the transistor Q1 and the resistor R1, so that the clamping operation is performed.

  The switching element protection circuit shown in FIG. 3 has the following advantages.

(1) Since the transistor M1 is not turned on, an excessive gate current is not generated even if there is no gate resistance. Therefore, the transistor Tr1 is clamped and can consume surge energy.

(2) Since the low-side off signal is output together with the clamping operation, generation of a through current is prevented.

(3) The low-side off signal to the low-side pre-driver 12 at the time of clamping can be sent regardless of the influence of dead time.

(4) Protection by clamping operation can be performed regardless of whether power is supplied to the protection circuit of the switching element. (5) In the modification, the current is controlled by the diode D2 instead of the gate resistance. . The diode D2 may be omitted or a resistor. In short, it depends on the circuit configuration.

  Further, by setting the gate resistance to zero, a high-speed switching operation can be performed, and the nitride FET element itself can perform a diode-like regenerative operation. When the gate-source of the nitride FET is short-circuited, the source is the anode terminal, the drain is the cathode terminal, and the threshold voltage Vth of the nitride FET is regarded as a forward voltage VF. The problem when the gate resistance described in the column of the problem to be solved exists can be avoided.

  The protection circuit for a switching element according to the second embodiment of the present invention is characterized in that a clamping diode D1 is embodied. As the diode D1, as shown in FIG. 4A, a high-breakdown-voltage diode can be used alone for clamping, but as shown in FIG. 4B, two diodes D2 having anodes connected to each other are used. , D3. Further, as shown in FIG. 4C, a capacitor C1 can be connected in parallel to one (upper stage) diode D4 of two diodes D4 and D5 connected in series. In this case, it is possible to perform the clamping operation without causing a delay when the surge is high dv / dt.

  In particular, when a diode is used in an IC as shown in FIG. 3, there are cases in which it is difficult to use a single high voltage diode because of limited elements. In this case, a high breakdown voltage can be realized by arranging Zener diodes in series.

  FIG. 5 is a circuit diagram illustrating a configuration of a protection circuit for a switching element according to the third embodiment of the present invention. In the protection circuit for a switching element according to the third embodiment, a GaN-FET is divided into a main (MAIN) transistor Tr1 and a sub (SUB) transistor Tr2 in one chip, and a resistor R7 is provided between the controller 21 and the transistor M2. Is connected. The area (current capacity) of the sub transistor Tr2 can be, for example, half or less of that of the main transistor Tr1. A gate terminal GATE MAIN is provided at the gate of the main transistor Tr1, and a gate terminal GATE SUB is provided at the gate of the sub transistor Tr2.

  Next, the surge protection operation of the nitride FET by the protection circuit of the switching element according to the third embodiment configured as described above will be described.

  The break current of the diode D1 flows through the path of the controller 21, the resistor R7, and the transistor M2, and the sub transistor Tr2 is turned on. As a result, a low-side off signal that instructs the transistor M2 to be turned off is output from the controller 21 and supplied to the low-side pre-driver 12. As a result, the main transistor Tr1 is also turned on.

  According to the protection circuit for a switching element according to the third embodiment, the surge protection operation can be started quickly by quickly turning on the sub transistor Tr2. Thereafter, since the main transistor Tr1 is turned on, the GaN-FET can be protected from the surge voltage. Although the gate resistance R7 of the sub transistor Tr2 is required, the gate resistance of the main transistor Tr1 is not necessary, so that the switching speed of the main transistor Tr1 can be increased. Note that a resistor or a diode may be inserted between the controller 21 and the gate of the sub transistor Tr2.

  The present invention is applicable to various circuits that require prevention of switching element destruction and high speed.

11 High-side pre-driver 12 Low-side pre-driver 21 Controller M1 High-side transistor (PMOS)
M2 Low side transistor (NMOS)
M3 transistor (NMOS)
Tr1, Tr2 transistors (switching elements)
D1-D5 Diode R1-R7 Resistor C1-C3 Capacitor Q1, Q2 Transistor (PNP)
IN input terminal VDD high voltage terminal VSS low voltage terminal DRAIN drain terminal GATE, GATE MAIN, GATE SUB gate terminal

Claims (1)

A high voltage side element and a low voltage side element connected in series;
A high-side pre-driver that outputs a signal for turning on and off the high-voltage side element;
A low-side pre-driver that outputs a signal for turning on and off the low-voltage element so as to be in an on / off state opposite to the high-voltage side element;
A main switching element having a control terminal connected to a connection point between the high voltage side element and the low voltage side element;
A sub switching element having a control terminal connected to a connection point between the high-voltage side element and the low-voltage side element via a resistor;
A diode having a cathode connected to one terminal of the main switching element;
An input terminal is connected to the anode of the diode, and a current is supplied to the control terminal of the sub switching element when the diode breaks, and a low-side off signal for instructing the low-voltage side element to be turned off is supplied to the low-side predriver. and a controller for,
A switching element protection circuit , wherein a current is supplied to a control terminal of the main switching element by turning off a low-voltage side element by a low-side pre-driver that has received a low-side off signal from the controller .

Images