CN112782803A

CN112782803A - Method for improving robustness of silicon-based optical waveguide process

Info

Publication number: CN112782803A
Application number: CN202110024201.5A
Authority: CN
Inventors: 朱继光; 宁宁; 吴月; 潘伯津
Original assignee: United Microelectronics Center Co Ltd
Current assignee: United Microelectronics Center Co Ltd
Priority date: 2021-01-08
Filing date: 2021-01-08
Publication date: 2021-05-11

Abstract

The invention provides a method for improving the robustness of a silicon-based optical waveguide process, which comprises the following steps: providing a substrate to be etched, wherein a designed waveguide pattern is defined on the substrate to be etched; determining an auxiliary graph area; performing first etching to form a designed waveguide pattern and an auxiliary pattern; and performing second etching to remove the auxiliary pattern. According to the method for improving the robustness of the silicon-based optical waveguide process, the auxiliary graph structure is added in the area where the virtual graph is not allowed to be added in the silicon-based design graph to form a uniform and dense graph structure, and then the auxiliary graph inside the graph is etched through secondary etching or multiple times of etching, so that the uniformity of the final graph of the wafer can be further improved on the basis of not influencing the original graph, the difference between the design and the process is reduced, the sparse waveguide can be protected, the product yield is improved to a certain extent, the process limit can be further improved, and the smaller waveguide size is achieved.

Description

Method for improving robustness of silicon-based optical waveguide process

Technical Field

The invention belongs to the field of silicon-based optical chips, and particularly relates to a method for improving the robustness of a silicon-based optical waveguide process.

Background

The waveguide size and the density degree in the design of the silicon optical device have larger design freedom, and the uncertainty of the waveguide width and the density has larger influence on exposure, development and etching, thereby influencing the final appearance of the waveguide on the silicon substrate. Conventional silicon-based optical waveguides have width tolerances in the range of ± a few nanometers, which requires very high processing accuracy and uniformity.

In order to improve the processing precision and uniformity of the waveguide, the pattern density is balanced by increasing the dummy pattern in the blank area without devices in the traditional process optimization, and in order to avoid unnecessary optical coupling effect, the distance between the dummy pattern area and the design pattern is at least 2 micrometers or more. For the areas which cannot be added with the virtual patterns, such as the areas with the waveguide spacing smaller than a few microns, defined in the design pattern, the pattern density of the areas has a certain difference from the pattern density of the areas added with the virtual patterns, and the exposure, development and etching have a larger fluctuation range for the finally formed patterns, so that the non-uniformity among the patterns is increased, the final waveguide morphology and the design value have a larger difference, and the device performance is deteriorated.

Therefore, if the uniformity of the pattern can be further improved, the difference between the design and the process can be greatly reduced, and better device performance can be achieved.

Disclosure of Invention

In view of the above disadvantages of the prior art, an object of the present invention is to provide a method for improving the robustness of a silicon-based optical waveguide process, which is used to solve the problems in the prior art that the uncertainty of the waveguide width and the density has a large influence on exposure, development and etching, thereby affecting the final morphology of the waveguide on the silicon substrate.

To achieve the above and other related objects, the present invention provides a method for improving process robustness of a silicon-based optical waveguide, the method comprising:

providing a substrate to be etched, wherein the substrate to be etched is provided with a designed waveguide pattern area;

determining an auxiliary pattern area, and expanding a preset distance outwards by taking the designed waveguide pattern area as a reference to form an expansion area, wherein the auxiliary pattern area is formed by the designed pattern area on the substrate to be etched and an area at the periphery of the expansion area;

performing first etching on the substrate to be etched based on a first mask to form a design waveguide in the design waveguide pattern area and form an auxiliary pattern in the auxiliary pattern area; and

and carrying out second etching on the substrate to be etched based on a second mask to remove the auxiliary pattern.

Optionally, the auxiliary graphics include a plurality of auxiliary graphics units, and the auxiliary graphics units are the same in size and shape and are arranged at uniform intervals.

As an example, the region corresponding to the design waveguide itself is formed to constitute the design waveguide pattern region.

Optionally, the feature size of the auxiliary pattern is equal to the feature size of the design pattern.

Optionally, the preset distance for forming the extension region is greater than the minimum coherence pitch of the first etching.

Optionally, a critical area surrounded by the design waveguide pattern exists on the substrate to be etched, the size of the critical area is smaller than 8 μm, and the auxiliary pattern is inserted in the critical area.

Optionally, the substrate to be etched includes a semiconductor substrate and a silicon material layer formed on the semiconductor substrate, and the designed waveguide pattern and the auxiliary pattern are both formed in the silicon material layer.

Optionally, the second etching process includes performing at least one etching process to remove the auxiliary pattern.

Optionally, the step of performing first etching on the substrate to be etched based on the first mask comprises a step of forming a first mask layer on the substrate to be etched through a first photolithography process; and performing second etching on the substrate to be etched based on the second mask plate, wherein the step of performing second etching on the substrate to be etched comprises a step of forming a second mask layer on the substrate to be etched through a second photoetching process.

Optionally, an adjacent device region and a non-device region are defined on the substrate to be etched, the device region includes a functional component preparation region and a scribe line region, and the auxiliary pattern region is located in the functional component preparation region.

Optionally, the design waveguide pattern includes a first density region and a second density region, the pattern density of the first density region is greater than the pattern density of the second density region, and the auxiliary pattern region is disposed in the second density region.

As described above, the method for improving the robustness of the silicon-based optical waveguide process adds the auxiliary pattern structure in the area where the virtual pattern is not allowed to be added in the silicon-based design pattern to form a uniform and dense pattern structure, and then etches the auxiliary pattern inside the pattern through secondary etching or multiple etching, so that the uniformity of the final pattern of the wafer can be further improved on the basis of not influencing the original pattern, the difference between the design and the process is reduced, the sparse waveguide can be protected, the product yield is improved to a certain extent, the process limit can be further improved, and the smaller waveguide size is achieved.

Drawings

Fig. 1 is a flow chart illustrating a method for improving the robustness of a silicon-based optical waveguide process according to the present invention.

FIG. 2 is a schematic diagram of providing a substrate to be etched during the process of improving the robustness of the silicon-based optical waveguide process according to the present invention.

Fig. 3 shows a graphical representation of a designed waveguide pattern region defined in the process of the present invention for improving the process robustness of a silicon-based optical waveguide.

Fig. 4 is a schematic diagram illustrating the determination of the auxiliary pattern region in the process of improving the robustness of the silicon-based optical waveguide process according to the present invention.

Fig. 5 is a schematic top view illustrating a designed waveguide pattern and an auxiliary pattern formed by a first etching process during the process of improving the robustness of the silicon-based optical waveguide according to the present invention.

Fig. 6 is a cross-sectional view illustrating a first etching process to form a design waveguide pattern and an auxiliary pattern during the process for improving the robustness of the silicon-based optical waveguide according to an exemplary embodiment of the present invention.

FIG. 7 is a schematic top view of a waveguide design pattern obtained by performing a second etch to remove the assist pattern during the process of improving robustness of the silicon-based optical waveguide process of the present invention.

Fig. 8 is a cross-sectional view taken at the position AB in fig. 7.

FIG. 9 is a schematic diagram of a substrate to be etched according to the present invention for improving the robustness of the silicon-based optical waveguide process.

Fig. 10 is a diagram illustrating an example of the presence of critical regions in the process of improving the process robustness of a silicon-based optical waveguide according to the present invention.

Description of the element reference numerals

100 substrate to be etched

101 first silicon substrate

102 intermediate silicon oxide layer

103 second silicon substrate

104 design waveguide pattern region

105 extension area

106 auxiliary pattern area

107 design waveguide pattern

108 auxiliary graphics

108a auxiliary graphics unit

S1-S4

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structures are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.

For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. In addition, "between … …" as used herein includes both endpoints.

In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.

It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed freely, and the layout of the components may be more complicated.

As shown in fig. 1, the present invention provides a method for improving robustness of a silicon-based optical waveguide process, which is used for solving the problem that uncertainty of waveguide width and density in the prior art has a large influence on exposure, development and etching, thereby affecting the final morphology of a waveguide on a silicon substrate. The method for improving the robustness of the silicon-based optical waveguide process comprises the following steps:

s1, providing a substrate to be etched, wherein the substrate to be etched is provided with a designed waveguide pattern area;

s2, determining an auxiliary pattern area, expanding outwards by a preset distance by taking the designed waveguide pattern area as a reference to form an expansion area, wherein the auxiliary pattern area is formed by the designed pattern area and an area outside the expansion area on the substrate to be etched;

s3, performing first etching on the substrate to be etched based on a first mask to form a design waveguide in the design waveguide pattern area and form an auxiliary pattern in the auxiliary pattern area; and

and S4, performing second etching on the substrate to be etched based on a second mask to remove the auxiliary pattern.

The method for improving the robustness of the silicon-based optical waveguide process of the present invention will be described in detail with reference to the accompanying drawings. Fig. 1 is a flow chart of a method for improving the robustness of a silicon-based optical waveguide process according to the present invention, and fig. 2 to 9 are schematic diagrams of steps of the improving method.

First, step S1 is performed, as shown in S1 of fig. 1 and fig. 2-3, a substrate 100 to be etched is provided, and the substrate 100 to be etched has a designed waveguide pattern region 104 thereon. Specifically, the substrate 100 to be etched is used for the subsequent preparation of a waveguide, for example, a waveguide used in a silicon optical device. The substrate 100 to be etched may be a single-layer material layer or a stacked structure formed by multiple material layers, and is selected according to actual process requirements.

As an example, the substrate to be etched 100 includes a semiconductor substrate and a silicon material layer formed on the semiconductor substrate, and the designed waveguide pattern and the auxiliary pattern are both formed in the silicon material layer. In an optional example, the substrate 100 to be etched sequentially includes, from bottom to top, a first silicon substrate 101, an intermediate silicon oxide layer 102, and a second silicon substrate 103, wherein a silicon waveguide is prepared by etching in the second silicon substrate 103, and in addition, a subsequent auxiliary pattern is also formed in the second silicon substrate and is finally etched away. Of course, other materials may be selected as the substrate to be etched.

In addition, the designed waveguide pattern region 104 on the substrate 100 to be etched may be a designed waveguide pattern region 104 defined according to requirements and subsequently used for preparing a waveguide, and in an example, a subsequently formed designed waveguide pattern for serving as a device waveguide structure is defined as the designed waveguide pattern region 104 here, that is, a region corresponding to the subsequently formed designed waveguide itself constitutes the designed waveguide pattern region 104.

Next, step S2 is performed, as shown in S2 of fig. 1 and fig. 4, to determine the auxiliary graphic area 106, which may be specifically: with the designed waveguide pattern region 104 as a reference, extending outward by a preset distance d1 to form an extension region 105, as shown by a dotted line in fig. 4, where the area on the substrate 100 to be etched around the designed pattern region 104 and the extension region 105 forms the auxiliary pattern region 106. Wherein figure 4 represents different areas with different fills in order to show the solution of the invention.

In a specific example, the extension region 105 is formed by extending a predetermined distance d1 from the periphery of the design waveguide pattern that is formed to be extendable in the plane of the substrate 100 to be etched. In an example, the preset distance d1 is greater than the minimum coherence pitch of the first subsequent etching (etching for simultaneously forming the design waveguide pattern and the auxiliary pattern), and further optionally, d1 × 2+ d2 (design pattern feature size) is greater than the minimum coherence pitch of the second subsequent etching (etching for removing the auxiliary pattern). In other examples, the value of d1 may be selected by considering the combination of the local transmittance and the overall transmittance in the case of designing under the above two conditions.

For example, in an alternative example, the predetermined distance d1 is in a range of 0.01-1 μm, and may be selected to be 0.02 μm, 0.05 μm, 0.1 μm, 0.15 μm, 0.2 μm, 0.5 μm, 0.8 μm, or 1.0 μm.

Next, step S3 is performed, as shown in S3 of fig. 1 and fig. 5-6, a first etching is performed on the substrate 100 to be etched based on a first mask (not shown in the figure) to form a designed waveguide 107 in the designed waveguide pattern region 104 and an auxiliary pattern 108 in the auxiliary pattern region 106. In fig. 5, different filling patterns are used to represent different etching patterns for displaying the etching structure, and the different filling patterns are actually the same result of etching the substrate to be etched.

That is, based on the etching process of this step, a design waveguide pattern 107 to be formed as a device waveguide structure and an auxiliary pattern 108 for improving the waveguide etching effect are correspondingly etched in the substrate 100 to be etched. The etching method includes, but is not limited to, dry etching.

As an example, the auxiliary graphic 108 includes a plurality of auxiliary graphic units 108a, and the auxiliary graphic units 108a have the same size and shape and are arranged at regular intervals. In an example, the shape of the auxiliary pattern 108 may be designed to be the same as or similar to the shape of the design waveguide pattern 107, as shown in fig. 5, showing an example of the auxiliary pattern 108. In addition, the auxiliary graphic unit 108a has a shape including, but not limited to, a bar shape, such as a square shape which may be arranged in a plurality of arrays.

In one example, the feature size of the auxiliary pattern 108 is the same as the feature size of the design pattern 107. It should be noted that, when the auxiliary graphic 108 includes a plurality of auxiliary graphic units 108a, the characteristic size of the auxiliary graphic 108 refers to the characteristic size of the auxiliary graphic 108 a. In an alternative example, as shown in FIG. 5, the width d2 of the design drawing 107 is equal to the width d3 of the auxiliary graphic element 108 a. Of course, in other examples, the size interval of the auxiliary pattern may also be adjusted in combination with the process capability and the transmittance requirement of the partial lithography etching, and the feature size of the auxiliary pattern 108 may not be equal to the feature size of the design pattern 107. In a preferred example, the width d2 of the design pattern 107, the width d3 of the auxiliary pattern unit 108a, the spacing between the auxiliary patterns 108 and the design pattern 107 (as shown in m1, m3, and m4 in fig. 5, and of course, there are other positions with similar spacing), and the spacing between the auxiliary patterns 108 (as shown in m2 in fig. 5) are all equal. The schematic cross-sectional structure obtained can be seen in fig. 6, so that the above-mentioned individual size intervals are as uniform as possible.

As an example, a critical region (shown by an oval dashed line frame in fig. 5) defined based on the design waveguide pattern 107 exists on the substrate 100 to be etched, where the critical region may be a region surrounded by the design waveguide pattern, for example, a region surrounded by the design waveguide itself; in other examples, as shown in fig. 10, there may be a region formed by the designed waveguide pattern 104 and other structures, such as a region surrounded by the designed waveguide and a conventional dummy pattern region, in which there is a key region 106a and a remaining auxiliary pattern region 106b outside the key region. Wherein the size of the key zone is smaller than 8 μm, wherein the auxiliary pattern 108 is inserted in the key zone. Here, the critical region size may refer to a minimum pitch formed by the design waveguide pattern 107 itself, as indicated by s in the drawing. In this example, the critical regions are less than 8 μm in size, and may be 0.15 μm, 0.2 μm, 0.5 μm, 0.8 μm, 1.0 μm, 1.5 μm, 2 μm, 3 μm, 6 μm. In these areas, dummy patterns cannot be added as in the prior art, and the design of the invention can effectively solve the problems of particularly caused etching nonuniformity and the like. In one example, the relationship between the key region and the auxiliary graphic region can be further understood, and the auxiliary graphic region is conventionally considered to have no size limitation in the existing design, and the key region can be understood to refer to the auxiliary graphic region less than 8um away from the design graphic.

Finally, step S4 is performed, as shown in S4 of fig. 1 and fig. 7-8, a second etching is performed on the substrate 100 to be etched based on a second mask (not shown in the figure) to remove the auxiliary pattern 108, so as to obtain the required waveguide design pattern 107.

By way of example, the second etching process includes, but is not limited to, a dry etching process, and may be optionally a wet etching process. In an alternative example, the second etching process includes a step of performing one etching or at least two etching processes to remove the auxiliary pattern 108, and by performing multiple etching processes, the precision requirement for a single reticle plate can be reduced, thereby saving the cost. That is to say, the second etching process includes but is not limited to etching once to remove the auxiliary pattern, when the requirement of the etching precision of one time is high, the auxiliary pattern can be removed by at least two times of etching, and through multiple times of etching, the requirement of the precision of a single photomask plate can be reduced, and the cost is saved.

As an example, the step of performing the first etching on the substrate to be etched based on the first mask includes a step of forming a first mask layer on the substrate to be etched through a first photolithography process, and the process of forming the first mask layer includes but is not limited to a photolithography process; and performing second etching on the substrate to be etched based on the second mask plate, wherein the step of performing second etching on the substrate to be etched comprises a step of forming a second mask layer on the substrate to be etched through a second photoetching process, and the process for forming the second mask layer comprises but is not limited to a photoetching process. The invention adds the auxiliary pattern to form a pattern on the chip through photoetching and etching, finally removes the auxiliary pattern through secondary or multiple times of etching, and can simultaneously control the uniformity of the design structure in multiple stages of exposure, development and etching.

The invention creatively provides a method for adding an auxiliary pattern in an optical waveguide design pattern and removing the auxiliary pattern through secondary etching, thereby improving the uniformity of the silicon-based optical waveguide pattern and improving the process robustness of the silicon-based optical waveguide. The invention can not only improve the uniformity of the waveguide and improve the process robustness, but also protect the sparse waveguide as the protection waveguide, thereby improving the product yield to a certain extent. The method for converting the sparse graph into the equidistant dense graph can further improve the process limit and generate the graph with smaller size. The invention can improve the film thickness uniformity in photoetching, improve the uniformity of the waveguide etching depth and the waveguide width in etching, finally improve the uniformity of the silicon-based optical waveguide and reduce the difference between design and process. The invention can further improve the process limit and achieve smaller waveguide size.

As an example, as shown in fig. 9, the substrate to be etched 100 has a device region C and a non-device region D defined thereon, where the device region C includes a functional component preparation region (e.g., a region for preparing the designed waveguide pattern 107) and a scribe line region, and the auxiliary pattern region 106 is located in the functional component preparation region. The non-device region D may be a blank region known to those skilled in the art, and of course, a dummy pattern with improved uniformity may be further formed in the non-device region D. In addition, the scribe lane region may be a scribe lane region for device cutting, testing, and the like, which is well known to those skilled in the art.

As an example, the design waveguide pattern 107 includes a first density region and a second density region, the pattern density of the first density region is greater than the pattern density of the second density region, where density is understood as a ratio of a pattern area of a design waveguide pattern portion to an area of an etched portion in a region of a same area, and the auxiliary pattern region is disposed in the second density region, that is, the auxiliary pattern is designed in a region where waveguides are sparser. Of course, in other examples, the two regions may be designed with auxiliary patterns, the size and shape spacing of the auxiliary patterns designed in the two density regions may be different according to the size of the auxiliary pattern region and the size of the design pattern, and finally, the pattern density difference between the two density patterns is smaller. .

Through the scheme of the invention, the auxiliary graphic area is determined firstly, and the auxiliary graphic adding area is determined by combining the original graphic area and the area which does not allow to add the virtual graphic. Expanding and negating the design pattern, reasonably selecting the space between the auxiliary pattern and the design pattern according to the process capability, and ensuring that the photoetching and etching process of the auxiliary pattern area cannot damage the design pattern; further designing and adding auxiliary patterns, and adding the auxiliary patterns in the auxiliary pattern area determined in the first step at equal intervals; performing inter-pattern logic processing, merging the added auxiliary patterns into a design pattern to be used as a first etching pattern, and independently using the determined auxiliary pattern area as an auxiliary etching mask layer to be used as a second etching pattern; and then carrying out first etching and second etching, wherein the first etching is adopted to etch a design pattern and an auxiliary waveguide pattern on the silicon-based chip, and the second etching is adopted to fully etch the auxiliary pattern, so as to finally obtain a desired design pattern.

In summary, according to the method for improving the robustness of the silicon-based optical waveguide process, the auxiliary pattern structure is added in the area where the virtual pattern is not allowed to be added in the silicon-based design pattern to form a uniform and dense pattern structure, and then the auxiliary pattern inside the pattern is etched away through secondary etching or multiple times of etching, so that the uniformity of the final pattern of the wafer can be further improved on the basis of not influencing the original pattern, the difference between the design and the process is reduced, the sparse waveguide can be protected, the product yield is improved to a certain extent, the process limit can be further improved, and the smaller waveguide size is achieved. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims

1. A method for improving process robustness of a silicon-based optical waveguide, the method comprising:

2. The method of claim 1, wherein the region corresponding to the designed waveguide itself is formed to form the designed waveguide pattern region.

3. The method of claim 1, wherein the auxiliary pattern comprises a plurality of auxiliary pattern units, and each auxiliary pattern unit has the same size and shape and is uniformly spaced.

4. The method of claim 1, wherein the assist feature has a feature size equal to a feature size of the design feature.

5. The method of claim 1, wherein the predetermined distance for forming the extension region is greater than a minimum coherence pitch of the first etch.

6. The method of claim 1, wherein a critical region defined based on the designed waveguide pattern exists on the substrate to be etched, the critical region has a size smaller than 8 μm, and the auxiliary pattern is inserted in the critical region.

7. The method according to claim 1, wherein the substrate to be etched comprises a semiconductor substrate and a silicon material layer formed on the semiconductor substrate, and the designed waveguide pattern and the auxiliary pattern are formed in the silicon material layer.

8. The method of claim 1, wherein the second etching process comprises at least one etching process to remove the auxiliary pattern.

9. The method of claim 1, wherein the step of first etching the substrate to be etched based on the first mask comprises a step of forming a first mask layer on the substrate to be etched by a first photolithography process; and performing second etching on the substrate to be etched based on the second mask plate, wherein the step of performing second etching on the substrate to be etched comprises a step of forming a second mask layer on the substrate to be etched through a second photoetching process.

10. The method of claim 1, wherein adjacent device regions and non-device regions are defined on the substrate to be etched, the device regions include a feature preparation region and a scribe lane region, and the auxiliary pattern region is located in the feature preparation region.

11. The method of any of claims 1-10, wherein the designed waveguide pattern comprises a first density region and a second density region, the pattern density of the first density region is greater than the pattern density of the second density region, and wherein the auxiliary pattern region is disposed in the second density region.