經濟部中央標準局員工消費合作社印製 SQ3325 Α7 _ Β7 五、發明説明（1 ) 本發明是有關於一種積體電路的隔絕製程（Isolation Process)，且特別是一種主動區罩幕（achVe iayei· fflask)的 ο又卩十方法，利用電腦輔助設計（CAD)導入虛置圖案（dummy pattern) ’並配合化學性機械研磨（chemica[ Machanical Polishing ’ CMP)程式，可使淺溝槽隔絕（shau〇w trench isolation)製程達全面性平坦化（gi〇ba〖 pUnarizati〇n)。 隨著積體電路設計趨於複雜，在製程中將線寬減少到1_ 以下，已使CMOS的溝槽式隔絕（trench isolation)發展有所限 制。因為圖案尺寸（Feature Size)的縮小，微影製程中所使用 的光源波長必須愈小，才能得到更佳的解析能力。但相對的，會 使聚焦深度（Depth of Focus)降低，而影響光罩上圖案的轉栘 精確能力。例如，使用由KrF雷射（Krypton Fluoride Laser) 所發出的波長為248nm的深紫外線（Deep ultra_Vi〇let Ray)為 曝光的光源，並使用傳統的光罩及曝光技術，來定義〇. 25…以 下的CMOS元件，所產生的聚焦深度將會低於。在這種限制 之下，傳統的溝槽式隔絕是無法在元件間距太大的區域完成全面 性平坦化（Global Planarization)的要求，因為習知利用化學 式機械研磨技術來達成平坦化的過程中，如果在底層 OmderUyer)的圖案有元件間距超過1〇/^以上，經研磨後會^ 此無兀件區域產生碟狀的凹#，而無法達到&全面平坦化的要 求。請參照第1A〜_所示，為習知傳統利用化學式機械研磨技 術的淺溝·槽隔絕製程的剖面圖，此習知的方法詳逑如下： 請參照第ΙΑ®，在-半導體基㈣表面形成—塾氧化層 2〇，接著形成一介電層30覆蓋在墊氧化層2〇上，例如是—氮化曰 本紙張尺度適用中國國家標準（CNS ) Α4規格（21〇χ297公釐） 批衣-- (請先閱讀背面之注意事項再填寫本頁) 、-=a 線----------- A7 B7 五、發明説明（2 ) 矽層，隨後上光阻並以光學微影和蝕刻程序而形成元件區u、 12、13，再利用此元件區上的光阻（未顯示）為罩幕，在矽基底 10上以非等向性蝕刻—定的深度而形成複數個溝槽。請參照第 1B圖，在該矽基底10表面利用化學氣相沈積法（CVD)沈積一氧化 層40，接著，利用化學式機械研磨法（CMp)研磨該氧化層並以第 一介電層30表面為終止層，而形成複數個溝槽隔離區、14、 U、16,結果如第1(：圖，接著去掉元件區介電層的殘留部份， 而在該矽基底表面形成閘氧化層50及複數晶矽層6〇，而完成了 溝槽隔絕製程。 然而，並非每一個溝槽隔絕區都等寬度，其間具有相當顯 著的差異，如圖示，溝槽隔絕區15就比溝槽隔絕區14大，於 是’在平坦化的製程中’複㈣觸填充於溝槽隔絕區14的部 份就可得難當平㈣表面，龍充於溝槽_區15的部份則呈 現—平'缓下凹的表胃，就習知的㈣，祇能達到局㉚平坦化 (local Planarizati0n)的效果，卻無法獲致全面平坦化 (global planarization)的目的。 經濟部中央標隼局員工消費合作社印11 (請先閱讀背面之注意事項再填寫本頁) 一有鑑於此，本發明的主要目的，在於提供一種全面性平坦 化隔絕’其利用化學式機械研磨法的淺溝槽隔絕製程，以及利用 電腦輔助設計（CAD)系統中，製作虛元件區光罩（d職y心〜 mask)的方法°SQ3325 Α7 _ Β7 printed by the Staff Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (1) The present invention relates to an isolation process for integrated circuits (Isolation Process), and in particular to an active area mask (achVe iayei · fflask) ο Another ten methods, using computer-aided design (CAD) to import dummy patterns (dummy patterns) and chemical mechanical polishing (chemica [Machanical Polishing 'CMP) program, can make shallow trench isolation (shau〇 w trench isolation) The process achieves comprehensive planarization (gi〇ba 〖pUnarizati〇n). As integrated circuit designs have become more complex, reducing the line width to less than 1 mm during the manufacturing process has limited the development of trench isolation in CMOS. Because of the reduction in feature size, the wavelength of the light source used in the lithography process must be smaller in order to obtain better resolution. But relatively, it will reduce the depth of focus (Depth of Focus) and affect the accuracy of the pattern on the reticle. For example, a deep ultraviolet light (Deep ultra_Violet Ray) with a wavelength of 248 nm emitted by KrF laser (Krypton Fluoride Laser) is used as a light source for exposure, and a traditional photomask and exposure technology are used to define 0.25 ... CMOS components, the resulting depth of focus will be lower. Under this limitation, the traditional trench isolation is unable to complete the global planarization (Global Planarization) requirement in the area where the element spacing is too large, because it is known to use chemical mechanical polishing technology to achieve the planarization process. If the pattern of the underlying layer (OmderUyer) has a device pitch of more than 10 / ^, after grinding, a dish-like concave will be generated in this element-free area, which cannot meet the requirements of & comprehensive planarization. Please refer to Sections 1A ~ _ for cross-sectional views of conventional shallow trench and trench isolation processes using chemical mechanical polishing technology. The details of this conventional method are as follows: Please refer to Section ΙΑ® on the surface of semiconductor base Forming-the oxide layer 20, and then forming a dielectric layer 30 covering the pad oxide layer 20, for example-Nitrided Japanese paper scale applicable China National Standards (CNS) A4 specifications (21〇 297 mm) approved Clothing-(Please read the precautions on the back before filling in this page),-= a line --------- A7 B7 V. Description of invention (2) Silicon layer, then apply photoresist and use Optical lithography and etching process to form element regions u, 12, 13 and then use the photoresist (not shown) on this element region as a mask to form anisotropic etching on silicon substrate 10 to a certain depth Plural grooves. Referring to FIG. 1B, an oxide layer 40 is deposited on the surface of the silicon substrate 10 by chemical vapor deposition (CVD), and then, the oxide layer is polished by chemical mechanical polishing (CMp) and the surface of the first dielectric layer 30 For the termination layer, a plurality of trench isolation regions, 14, U, and 16 are formed. The result is as shown in Fig. 1 (: Figure, and then the remaining part of the dielectric layer in the device region is removed, and a gate oxide layer 50 is formed on the surface of the silicon substrate And the multiple crystalline silicon layer 60, and the trench isolation process is completed. However, not every trench isolation region has the same width, and there are quite significant differences between them. As shown, the trench isolation region 15 is more isolated than the trench isolation. The area 14 is large, so 'in the planarization process', the part filled in the trench isolation area 14 can be difficult to be a flat surface, and the part filled with the groove _ area 15 is flat- The slowly dimpled surface stomach, as is known, can only achieve the effect of local planarization (local planarizati0n), but it cannot achieve the purpose of global planarization. The Ministry of Economic Affairs Central Standard Falcon Bureau Employee Consumer Cooperative Printed 11 (Please read the notes on the back first In view of this, the main objective of the present invention is to provide a comprehensive planarization isolation 'which uses a chemical mechanical polishing method of shallow trench isolation process, and uses a computer-aided design (CAD) system to produce virtual The method of the component area mask (d function y heart ~ mask) °
本發明的這些目的’可藉由—原始罩幕，其於 内包括擴散區圖案、複晶峨圖案、及井區圖案；將擴散區圖 案及複晶矽導線圖案均向外擴張一參數a的範圍，以及將井區圖 案的邊界線向内外各擴張一參數b的範圍，二者合稱為第一圖W 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X 297公釐） 經濟部中央標準局員工消費合作社印製 ^3925 A7 ------------___ 五、發明説明（3 ) 案；將主動區範圍扣除該第—圖案，得到—第二圖案；接著提供 一虛置陣列圖案，其與該第二圖案作AND處理，得到一第三圖 案；將該第二圖案向外擴張一參數c的範圍，得到一第四圖案； 將第四圖案與該擴散區圖案做〇R處理，即可得到含有虚置圖案的 主動區罩幕。 為讓本發明之上述和其他目的、特徵、和優點能更明顯易 懂，下文特舉—較佳實施例，並配合所附圖式，作詳細說明如 下： 圖式之簡單說明·： 第1A〜1D圖所示，為習知傳統利用化學式機械研磨技術平坦 化的淺溝槽隔絕製程的剖面圖； 第2A~2E圖係顯示用以說明本發明形成主動區罩幕設計方法 的頂視流程圖：以及 第3A~3D圖係顯示用以說明本發明形成主動區罩幕及配合化 學式機械研磨技術的淺溝槽隔絕製程的剖面流程圖。 實施例： 請參照第2A至2E圖，所示為根據本發明形成—具有虛置圖 案的主動區罩幕的頂視流程圖。首先，如第2A圖所示，—主動區 内包括第I區為擴散區圖案、第η區為複晶矽圖案、第瓜區為井 區圖案。首先，第I、η區均向外擴張一參數a的範圍，該參數& 之較佳貫施例可為1.4；^，第瓜區井區圖案的邊界線向內外各擴 張一參數b的範圍，該參數b之較佳實施例可為〇. ，若上述之 擴張範圍有互為重疊，則予以合併成同—區域，該第丨、n 區圖案擴張後之圖案合稱第一圖案區100。然後，將主動區範圍 5 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 糾衣------1T------^ (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消费合作社印製 293925 A7 _ B7 五、發明説明（4 ) 扣除該第一圖案區100後，得到一第二圖案區2〇〇，該實施例可 用色調反轉處理（reverse tone)完成。接著，如第26圖所示， 配合一虚置陣列圖案150做處理，此虛置陣列圖案15〇具有複數 區塊圖案160呈陣列（array)形式排列，而區塊圖案16〇間互以— 參數d的距離相隔，並各具有一參數e的寬度和參數f的長度，其 中，一較佳實施例中，參數d可為1.8〆參數e可為〇 2卿、及 參數f可為2. 2^。 然後，p青參照第2C圖，將第2A圖及第2B圖二者做"AND"的 運算，亦即選取第二圖案區200和虚置陴列圖案15〇二者重疊之 處，成一第三圖案區300，經此選取處理後之第三圖案區3〇〇含 有複數區塊350;再者，沿此第三圖案區3〇〇具有之各區塊35〇週 邊，向外擴張一參數c的範圍，即得如第2D圖所示之第四圖案區 400，然因第三圖案區300包含複數區塊35〇，是故第四圖案區 400亦包含複數個區塊450，所不同者是，區塊45〇係為沿區塊 350週邊向外延伸一參數c的範圍，此參數c的較佳實施例為 〇. 4；^。 最後’將第2D圖中的第四圖案區4〇〇與第2A圖中的擴散區圖 案I —者做"OR"處理，亦即將擴散區圖案依原相對位置置入第 四圖案區400內，得第2E圖所示的一主動區罩幕圖案5〇〇。然 後，再利用此一具有虛置圖案的主動區罩幕圖案5〇()來完成淺溝 槽隔絕製程之步驟。 請參照第3A至3D圖所示’為根據本發明形成的主動區罩幕 及利用化學式機械研磨（Cheical Mechanics Polishing)技術 的淺溝槽（sha 11 ow trench)隔絕製程的一實施例的剖面圖流程 6 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 扣衣------II------^ (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 A7 -----—— _B7__ 五、發明説明（5 ) ~ -—— 圖，首先，如第3A圖所示，在—矽基式11〇上形成—墊氧化層 120及一介電層130，隨後上光阻（未顯示）再利用上述具有虛置 圖案的王動區罩幕經光學微影程序後而定義元件區111、112、 113及虚置兀件區114、115、116。 隨後，利用非等向性蝕刻方式在該矽基底110表面蝕刻複數 個溝槽，並利用化學氣相沈積法（CVD)沈積一氧化層14〇，請參 照第3B圖，接著以化學機械研磨法（CMp)研磨該氧化層，並以該 介電層130表面為终止層，而形成複數個渠溝隔離117、118、 119、120、121及122，如第3C圖所示，而隨後去掉介電層13〇 的殘留部份，而在該矽基底形成閘極氧化層15〇及複晶矽閘極層 160，而完成了淺溝槽隔絕製程，如第汕圖所示之形狀。 綜上所述，根據本發明方法形成的淺溝槽隔絕的積體電路， 因藉由一虛置陣列圖案配合擴散區圖案、複晶矽圖案、及井區圖 案，形成的主動區圖案來達到全面性的平坦化，而其間之運算處 理更可佐以計算機輔助設計（CAD)而得，故於間距超過化學式機 械研磨（CMP)技術可平坦化之上限時，經本發明方法設置虛置陣 列£塊可減少其間距，因而獲得更多虛置元件，達到全面平坦的 要求。 事實上，每一圖案的擴張範圍參數是相互獨立的，而且與該 元件的圖案尺寸、設計方法、及特性有關。在實施例之中，如果 將虛置陣列的區塊間距及寬度都減少到丨.0^，則井深區的邊界 隔絕線寬最小可為1. ，而實際主動區及虛置主動區的隔絕寬 度亦能為1. 〇_，這樣的圖案尺寸將可適用於使用波長為248^ 的深紫外線（Deep Ultra-Violet Ray)為光源的曝光機，甚至 7 本紙張尺度適用中國國家標準（CNS)八4規格（210X 297公釐）· (請先閲讀背面之注意事項再填寫本頁) .裝· -6 線 A7 一____ B7 五、發明説明（6 ) 可選擇波長更賴光源來完成微影製程。 因此本發明能滿足下—世代圖案尺寸低於〇. 3、的積體電 路甚至於更咼密度的產品，對於全面平坦化的要求。 雖然本發明已以一較佳實施例揭露如上，然其並非用以限定 本發明’任何熟習此技藝者，在不脫離本發明之精神和範圍内’ 當可作些許之更動與潤飾，因此本發明之保護範圍當視後附之申 請專利範圍所界定者為準。 (请先閱讀背面之注意事續真填寫本 .裝.These objectives of the present invention can be achieved by-the original mask, which includes the diffusion area pattern, the polycrystalline E pattern, and the well area pattern; the diffusion area pattern and the polycrystalline silicon wire pattern are expanded outward by a parameter a The range, and the boundary of the well pattern are expanded inwards and outwards by a parameter b, which is collectively referred to as the first picture. W The paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) Ministry of Economic Affairs Printed by the Central Standards Bureau employee consumer cooperative ^ 3925 A7 ------------___ V. Description of the invention (3) case; deduct the first pattern from the active area to obtain the second pattern; then Providing a dummy array pattern, which is AND processed with the second pattern to obtain a third pattern; expanding the second pattern outward by a range of parameter c to obtain a fourth pattern; dispersing the fourth pattern and the diffusion If the area pattern is subjected to OR treatment, an active area mask with dummy patterns can be obtained. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the following is a list of preferred embodiments, in conjunction with the attached drawings, which are described in detail as follows: Brief description of the drawings ~ FIG. 1D is a cross-sectional view of a conventional shallow trench isolation process that is conventionally planarized using chemical mechanical polishing technology; FIGS. 2A-2E show a top-view process for illustrating the design method of forming an active area mask of the present invention Figures: and Figures 3A ~ 3D are cross-sectional flow charts illustrating the shallow trench isolation process used to form the active area mask and the chemical mechanical polishing technology of the present invention. Embodiment: Please refer to FIGS. 2A to 2E, which show a top view flow chart of an active area mask formed with a dummy pattern formed according to the present invention. First, as shown in FIG. 2A, the active region includes the first region as a diffusion region pattern, the nth region as a polycrystalline silicon pattern, and the second melon region as a well region pattern. First, both the I and η regions expand outward by a parameter a. The preferred embodiment of this parameter can be 1.4; ^, the boundary line of the well pattern in the second melon region expands by a parameter b inward and outward. Range, the preferred embodiment of the parameter b may be 0. If the above-mentioned expansion ranges overlap each other, they will be merged into the same-area, and the patterns after the expansion of the patterns in the 丨 and n areas are collectively called the first pattern area. 100. Then, the 5 paper scales in the active area are applicable to the Chinese National Standard (CNS) A4 specification (210X297mm). Corrective clothing ------ 1T ------ ^ (Please read the precautions on the back before filling in This page) Printed 293925 A7 _ B7 by the Staff Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy V. Description of the invention (4) After deducting the first pattern area 100, a second pattern area 200 is obtained. The processing (reverse tone) is completed. Next, as shown in FIG. 26, a dummy array pattern 150 is used for processing. The dummy array pattern 150 has a plurality of block patterns 160 arranged in an array, and the block patterns 160 are mutually inter- The distance of the parameter d is separated, and each has a width of the parameter e and a length of the parameter f, wherein, in a preferred embodiment, the parameter d may be 1.8 〆 parameter e may be 〇2 Qing, and the parameter f may be 2. 2 ^. Then, P Qing refers to FIG. 2C, and performs an " AND " operation on both FIG. 2A and FIG. 2B, that is, selects the overlap between the second pattern area 200 and the dummy column pattern 15. In the third pattern area 300, the third pattern area 300 after the selection process contains a plurality of blocks 350; further, along the periphery of each block 35 in the third pattern area 300, expand outward one The range of the parameter c is the fourth pattern area 400 as shown in FIG. 2D. However, since the third pattern area 300 includes a plurality of blocks 350, the fourth pattern area 400 also includes a plurality of blocks 450. The difference is that the block 45 is a range of a parameter c extending outward along the periphery of the block 350. The preferred embodiment of this parameter c is 0.4; ^. Finally, the fourth pattern area 400 in FIG. 2D and the diffusion area pattern I in FIG. 2A are subjected to " OR " processing, that is, the diffusion area pattern is placed in the fourth pattern area 400 according to the original relative position Inside, an active area mask pattern 500 shown in FIG. 2E is obtained. Then, the active area mask pattern 50 () with dummy patterns is used to complete the steps of the shallow trench isolation process. Please refer to FIGS. 3A to 3D. FIG. 3 is a cross-sectional view of an embodiment of an active area mask formed according to the present invention and a shallow trench (sha 11 ow trench) isolation process using chemical mechanical polishing (Cheical Mechanics Polishing) technology. Process 6 The size of this paper is in accordance with Chinese National Standard (CNS) A4 (210X297mm) Button buckle ------ II ------ ^ (Please read the precautions on the back before filling this page) Ministry of Economic Affairs Printed by the Central Standards Bureau employee consumer cooperative A7 --------- _B7__ V. Description of the invention (5) ~ ----- Figure, first, as shown in Figure 3A, a pad is formed on the silicon-based 11〇 The oxide layer 120 and a dielectric layer 130 are then coated with a photoresist (not shown) and then the above-mentioned mask with a dummy pattern is used to define the element regions 111, 112, 113 and dummy elements after an optical lithography process Pieces 114, 115, 116. Subsequently, a plurality of trenches are etched on the surface of the silicon substrate 110 by anisotropic etching, and an oxide layer 14 is deposited by chemical vapor deposition (CVD). Please refer to FIG. 3B, followed by chemical mechanical polishing (CMp) grinding the oxide layer and using the surface of the dielectric layer 130 as a stop layer to form a plurality of trench isolations 117, 118, 119, 120, 121 and 122, as shown in FIG. 3C, and then removing the dielectric The remaining part of the electrical layer 130 is formed with a gate oxide layer 15o and a polysilicon gate layer 160 on the silicon substrate, and the shallow trench isolation process is completed, as shown in the shape shown in the figure. To sum up, the shallow trench isolated integrated circuit formed according to the method of the present invention is achieved by forming an active area pattern through a dummy array pattern in combination with a diffusion area pattern, a polycrystalline silicon pattern, and a well area pattern Comprehensive planarization, and the calculation processing in between can be supplemented by computer-aided design (CAD), so when the spacing exceeds the upper limit of chemical mechanical polishing (CMP) technology can be planarized, the dummy array is set by the method of the present invention. Blocks can reduce their spacing, thereby obtaining more dummy components and meeting the requirements of overall flatness. In fact, the expansion range parameters of each pattern are independent of each other, and are related to the pattern size, design method, and characteristics of the device. In the embodiment, if the block spacing and width of the dummy array are reduced to 丨 .0 ^, the boundary isolation line width of the deep well area can be at least 1. The isolation of the actual active area and the dummy active area The width can also be 1. 〇_, such a pattern size will be applicable to the exposure machine using the deep ultraviolet (Deep Ultra-Violet Ray) with a wavelength of 248 ^ as the light source, and even 7 paper scales are applicable to the Chinese National Standard (CNS) 8.4 specifications (210X 297mm) · (please read the notes on the back before filling in this page). Install · -6 line A7 a ____ B7 5. Invention description (6) The choice of wavelength depends on the light source to complete the micro Shadow process. Therefore, the present invention can meet the requirements for the overall planarization of the integrated circuit with the next-generation pattern size of less than 0.3, and even the products with higher density. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. "Any person who is familiar with this skill, without departing from the spirit and scope of the present invention" can make some modifications and retouching, so this The scope of protection of an invention shall be deemed as defined by the scope of the attached patent application. (Please read the notes on the back to fill in this.
•1T 經濟部中央標準局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS > A4規格（210X297公釐）• Printed by the 1T Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs. This paper scale is applicable to the Chinese National Standard (CNS > A4 specification (210X297mm)