TWI483288B - Method for manufacturing a semiconductor device - Google Patents
Method for manufacturing a semiconductor device Download PDFInfo
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- TWI483288B TWI483288B TW097143032A TW97143032A TWI483288B TW I483288 B TWI483288 B TW I483288B TW 097143032 A TW097143032 A TW 097143032A TW 97143032 A TW97143032 A TW 97143032A TW I483288 B TWI483288 B TW I483288B
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/36—Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
- G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
- G03F7/70441—Optical proximity correction [OPC]
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Description
本發明分別主張於2007年12月20日及2008年5月28日所申請之第10-2007-0134549號及第10-2008-0049896號之韓國專利申請案之優先權,其中併入其全文供參照。The present invention claims the priority of Korean Patent Application No. 10-2007-0134549 and No. 10-2008-0049896, filed on Dec. 20, 2007 and May 28, 2008. For reference.
本發明係關於一種製造半導體元件之方法,以及更特別地是,關於一種製造可增加製程中之疊放邊限之半導體元件之方法,以得到一墊佈局,用以當施加負型SPT法時,有助於形成一相互連接區域。BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a method of fabricating a semiconductor device, and more particularly to a method of fabricating a semiconductor device that can increase the stacking margin in a process to obtain a pad layout for use in applying a negative SPT method. Helps to form an interconnected area.
由於半導體元件變得高度積體化,故需要降低用以形成電路之圖案尺寸及間距。依照Rayleigh之方程式,半導體元件中微細圖案之尺寸係正比於用於曝光製程之光波長,以及反比於用於該曝光製程之曝光器(exposer)內透鏡之尺寸。因此,己有人使用用以降低該曝光製程中之光波長或放大該曝光製程中所用之透鏡尺寸的方法以形成微細圖案。Since semiconductor elements become highly integrated, it is necessary to reduce the pattern size and pitch for forming circuits. According to Rayleigh's equation, the size of the fine pattern in the semiconductor component is proportional to the wavelength of the light used for the exposure process, and inversely proportional to the size of the lens within the exposer used for the exposure process. Therefore, a method for reducing the wavelength of light in the exposure process or enlarging the lens size used in the exposure process has been used to form a fine pattern.
各種光製程已克服半導體元件之製造中技術上的限制。例如,遮罩已被精細地設計用以調整經由該遮罩發射之光量;己發展出新的光阻材料;己發展出使用高數值孔徑之透鏡;以及已發展出轉移遮罩。Various optical processes have overcome the technical limitations in the manufacture of semiconductor components. For example, masks have been finely designed to adjust the amount of light emitted through the mask; new photoresist materials have been developed; lenses using high numerical aperture have been developed; and transfer masks have been developed.
然而,由於曝光及解析能力(使用目前可用的光源,例如KrF與ArF)之限制,故其難以形成期望之圖案寬度及間距。例如,己發展出用以製造約60nm之圖案之曝光技術,惟製造小於60nm之圖案變得不確定。However, due to the limitations of exposure and resolution capabilities (using currently available sources such as KrF and ArF), it is difficult to form the desired pattern width and spacing. For example, exposure techniques have been developed to fabricate patterns of about 60 nm, but making patterns of less than 60 nm becomes uncertain.
已實行各種研究以形成具微細尺寸及間距之光阻圖案。Various studies have been conducted to form photoresist patterns having fine sizes and pitches.
那些研究之一係說明執行雙重光製程之雙重圖案化技術(DPT),用以形成一圖案。One of those studies describes the dual patterning technique (DPT) that performs a dual light process to form a pattern.
在DPT之一個例示中,雙重曝光蝕刻技術(DE2T)包括曝光及蝕刻具有雙循環之一第一圖案,以及曝光及蝕刻於該等第一圖案間具有雙循環之一第二圖案。在DPT之另一例示中,一間隔物圖案化技術(SPT)包括使用一間隔物形成一圖案。該DE2T及該SPT二者均可使用負型及正型來執行。In one example of a DPT, a double exposure etch technique (DE2T) includes exposing and etching a first pattern having a double cycle, and exposing and etching a second pattern having a double cycle between the first patterns. In another illustration of DPT, a spacer patterning technique (SPT) involves forming a pattern using a spacer. Both the DE2T and the SPT can be performed using a negative type and a positive type.
在該負型DE2T中,於一第二遮罩製程中移除自第一遮罩製程獲得的圖案,以形成一期望圖案。在該正型DE2T中,結合自一第一遮罩製程及一第二遮罩製程所獲得的圖案,以形成一期望圖案。然而,使用二種不同的遮罩之該DE2T需要額外的製程以及會增加複雜度。同樣地,互相隔開的由第一遮罩製程及第二遮罩製程所獲得的圖案中,可能產生對準錯誤(mis-alignment)(其稱為疊放(overlay))。In the negative type DE2T, the pattern obtained from the first mask process is removed in a second mask process to form a desired pattern. In the positive type DE2T, a pattern obtained from a first mask process and a second mask process is combined to form a desired pattern. However, the use of two different masks for the DE2T requires additional processing and adds complexity. Similarly, in the patterns obtained by the first mask process and the second mask process which are spaced apart from each other, mis-alignment (which is called overlay) may occur.
另一方面,該SPT為一種自我對準方法,其包含執行一次遮罩製程,以將胞元(cell)區域圖案化,藉以防止對準錯誤。In another aspect, the SPT is a self-aligned method that includes performing a masking process to pattern cell regions to prevent alignment errors.
然而,為了於核心及周圍電路區域中形成墊圖案,特別是在胞元墊(mats)之外部區塊中,需要額外的遮罩製程以隔離每一墊圖案。一般來說,當藉由該SPT形成配置於該胞元墊之中央區塊內之複數線型微細圖案時,沒有將該胞元墊之外部區塊圖案化。在形成該等複數線型圖案於該中央區塊後,連接至每一線型微細圖案之該等墊圖案之每一者係藉由將該胞元墊之外部區塊圖案化而形成。當圖案化該外部區塊時,執行用以決定該等墊圖案之形狀之遮罩製程。接著,亦執行用以移除該外部區塊中之剩餘部分(odds and ends)的額外遮罩製程。同樣地,控制間隔物形成區域之沈積一致性及以間隔物蝕刻製程調整臨界尺寸(CD)是困難的。However, in order to form a pad pattern in the core and surrounding circuit regions, particularly in the outer blocks of the mats, an additional masking process is required to isolate each pad pattern. Generally, when the plurality of linear fine patterns disposed in the central block of the cell pad are formed by the SPT, the outer block of the cell pad is not patterned. After forming the plurality of line patterns in the central block, each of the pad patterns connected to each of the line type fine patterns is formed by patterning an outer block of the cell pad. When the outer block is patterned, a mask process for determining the shape of the pad patterns is performed. An additional masking process to remove the odds and ends in the outer block is also performed. Likewise, it is difficult to control the deposition uniformity of the spacer formation regions and to adjust the critical dimension (CD) by the spacer etching process.
雖然在包含線/間隔物的多層結構之情況下,該SPT係單獨應用至NAND快閃製程,但若磚形壁圖案係設置在一DRAM或複雜的圖案層中,則藉由使用該SPT來形成一圖案是困難的。在此情況下,一般使用該DE2T。Although in the case of a multilayer structure including lines/spacers, the SPT is applied separately to the NAND flash process, if the brick wall pattern is disposed in a DRAM or a complex pattern layer, by using the SPT Forming a pattern is difficult. In this case, the DE2T is generally used.
本發明之各種實施例係針對提供一種墊佈局以助於使用基本原理來形成一相互連接區域,其中當施加一負型SPT法時將間隔物沈積材料間所形成之填隙多晶矽(gap fill poly)之最終外形形成為具有一線(line)。Various embodiments of the present invention are directed to providing a pad layout to facilitate the use of a basic principle to form an interconnected region in which gap fill poly is formed between spacer deposition materials when a negative SPT process is applied. The final shape is formed to have a line.
本發明之各種實施例係針對當移除該填隙多晶矽以露出該間隔物沈積材料時,因可施加乾式回蝕刻或濕式移除製程而增加疊放邊限。Various embodiments of the present invention are directed to increasing stacking margins when a dry etchback or wet removal process can be applied when the interstitial polysilicon is removed to expose the spacer deposition material.
依照本發明之一實施例,製造一半導體元件之方法包括:於具有底層結構之半導體基板上方形成蝕刻目標層;於該蝕刻目標層上方形成第一遮罩圖案;於包含該第一遮罩圖案之該蝕刻目標層上方形成具有均勻厚度之間隔物材料層;形成一第二遮罩圖案於該間隔物材料層之缺口區域上;以及以該第一遮罩圖案及該第二遮罩圖案作為蝕刻遮罩,蝕刻該蝕刻目標層,以形成一微細圖案。According to an embodiment of the present invention, a method of fabricating a semiconductor device includes: forming an etch target layer over a semiconductor substrate having an underlying structure; forming a first mask pattern over the etch target layer; and including the first mask pattern Forming a spacer material layer having a uniform thickness over the etch target layer; forming a second mask pattern on the notch region of the spacer material layer; and using the first mask pattern and the second mask pattern as The mask is etched and the etch target layer is etched to form a fine pattern.
依照本發明之一實施例,製造一半導體元件之方法包括:於半導體基板上方依次形成蝕刻目標層、第一硬遮罩材料層、第一分隔材料層、以及第二硬遮罩材料層;選擇性蝕刻該第二硬遮罩材料層以形成第二硬遮罩圖案;以該第二硬遮罩圖案作為蝕刻遮罩,蝕刻該第一分隔材料層,以形成第一分隔;於包含該第一分隔之該第一硬遮罩材料層上方形成間隔物材料層及第二分隔材料層;部分蝕刻該間隔物材料層及該第二分隔材料層直到露出該第一分隔,藉以露出該間隔物材料層,以於該等第一分隔之間形成一第二分隔;以該第一分隔及該第二分隔作為蝕刻遮罩,蝕刻該間隔物材料層及該第一硬遮罩材料層,以形成一第一硬遮罩圖案;以及以該第一硬遮罩圖案作為蝕刻遮罩,蝕刻該蝕刻目標層,以形成一微細圖案。According to an embodiment of the invention, a method of fabricating a semiconductor device includes sequentially forming an etch target layer, a first hard mask material layer, a first spacer material layer, and a second hard mask material layer over the semiconductor substrate; Etching the second layer of hard mask material to form a second hard mask pattern; etching the first layer of spacer material with the second hard mask pattern as an etch mask to form a first spacer; Forming a spacer material layer and a second separation material layer over the first hard mask material layer; partially etching the spacer material layer and the second spacer material layer until the first separation is exposed, thereby exposing the spacer a layer of material to form a second spacer between the first spacers; to etch the spacer material layer and the first hard mask material layer by using the first spacer and the second spacer as an etch mask Forming a first hard mask pattern; and etching the etch target layer with the first hard mask pattern as an etch mask to form a fine pattern.
依照本發明之一實施例,製造一半導體元件之方法包括;於具有底層結構之半導體基板上方形成一蝕刻目標層;於該蝕刻目標層上方形成第一遮罩材料層並選擇性蝕刻該第一遮罩材料層,以形成包括墊圖案及線圖案之第一遮罩圖案;形成包括線圖案之第二遮罩圖案,其中該線圖案形成於該等第一遮罩圖案之間;形成第三遮罩圖案,其將該第二遮罩圖案連接至該第一遮罩圖案之該墊圖案;以及以該第一遮罩圖案、該第二遮罩圖案以及該第三遮罩圖案作為蝕刻遮罩,蝕刻該蝕刻目標層,以形成一微細圖案。According to an embodiment of the invention, a method of fabricating a semiconductor device includes: forming an etch target layer over a semiconductor substrate having an underlying structure; forming a first mask material layer over the etch target layer and selectively etching the first a mask material layer to form a first mask pattern including a pad pattern and a line pattern; forming a second mask pattern including a line pattern, wherein the line pattern is formed between the first mask patterns; forming a third a mask pattern connecting the second mask pattern to the pad pattern of the first mask pattern; and using the first mask pattern, the second mask pattern, and the third mask pattern as an etch mask A mask is etched to etch the target layer to form a fine pattern.
第1a至1h圖為說明負型間隔物圖案化技術(SPT)之剖面圖。第1a至1h圖係描繪當形成一快閃記憶體之控制閘極時之圖式。本發明可被用在該快閃記憶元件或其它類型之記憶元件內之其它結構。Figures 1a through 1h are cross-sectional views illustrating a negative spacer patterning technique (SPT). Figures 1a through 1h depict a diagram when forming a control gate of a flash memory. The invention can be used in other structures within the flash memory component or other type of memory component.
參照第1a圖,一元件隔離薄膜(沒有顯示)係界定一形成於一半導體基板(沒有顯示)中之主動區域。一氧化物/氮化物/氧化物(ONO)介電層(沒有顯示)係沈積在該半導體基板上方。同樣地,於該ONO介電層上沈積一閘極層(沒有顯示)。在此,該閘極層包括一多晶矽(poly)及矽化鎢。於該閘極層上方形成一第一氮氧化矽(SiON)薄膜110。在此,在該第一SiON薄膜110下方存有多重層,用以於該半導體基板上方構成該快閃記憶體之控制閘極。惟,在其它實施例中,該第一SiON薄膜110下方之蝕刻目標層可為包含於其它微細圖案(諸如電容器、導線等等)中之任何層。Referring to Figure 1a, an element isolation film (not shown) defines an active region formed in a semiconductor substrate (not shown). An oxide/nitride/oxide (ONO) dielectric layer (not shown) is deposited over the semiconductor substrate. Similarly, a gate layer (not shown) is deposited over the ONO dielectric layer. Here, the gate layer includes a polycrystalline germanium (poly) and tungsten germanium. A first silicon oxynitride (SiON) film 110 is formed over the gate layer. Here, multiple layers are disposed under the first SiON film 110 for forming a control gate of the flash memory over the semiconductor substrate. However, in other embodiments, the etch target layer under the first SiON film 110 may be any layer included in other fine patterns such as capacitors, wires, and the like.
第一正矽酸四乙酯(TEOS)薄膜112及第一多晶矽薄膜114係沈積在該第一SiON薄膜110上方作為一硬遮罩。A first tetraethyl orthosilicate (TEOS) film 112 and a first polysilicon film 114 are deposited over the first SiON film 110 as a hard mask.
一第一非晶碳116及一第二SiON薄膜118係於該第一多晶矽薄膜114上方形成為一硬遮罩,以蝕刻該第一多晶矽薄膜114。使用一光阻遮罩並不易蝕刻該第一多晶矽薄膜114。一底部抗反射塗布(BARC)薄膜119係於該第二SiON薄膜118上方形成。A first amorphous carbon 116 and a second SiON film 118 are formed as a hard mask over the first polysilicon film 114 to etch the first polysilicon film 114. The first polysilicon film 114 is not easily etched using a photoresist mask. A bottom anti-reflective coating (BARC) film 119 is formed over the second SiON film 118.
於該BARC薄膜119上方塗布一光阻薄膜(沒有顯示)。使用一遮罩(其中界定一具有如期望間距之二倍寬的間距之圖案),於該光阻薄膜上執行曝光及顯影製程以形成一光阻圖案120。例如,當不考慮蝕刻偏差(bias)時,若形成的線具有40nm的臨界尺寸(CD),則於二個相鄰線間形成具有120nm之CD的間隔物。亦即,該線對間隔物的比為1比3。A photoresist film (not shown) is applied over the BARC film 119. An exposure and development process is performed on the photoresist film to form a photoresist pattern 120 using a mask in which a pattern having a pitch as wide as twice the desired pitch is defined. For example, when the etching bias is not considered, if the formed line has a critical dimension (CD) of 40 nm, a spacer having a CD of 120 nm is formed between two adjacent lines. That is, the ratio of the line to the spacer is 1 to 3.
參照第1b圖,使用該光阻圖案120作為蝕刻遮罩,依序蝕刻該BARC薄膜119、該第二SiON薄膜118、該第一非晶碳116以及該第一多晶矽薄膜114,以形成一第一多晶矽圖案,其包括該第一多晶矽薄膜114之第一結構114a以及該第一多晶矽薄膜114之第二結構114b。該第一多晶矽圖案包括許多其它類似該第一及第二結構之其它結構。接著移除該殘餘光阻圖案120、該BARC薄膜119、該第二SiON薄膜118以及該非晶碳116。Referring to FIG. 1b, the photoresist pattern 120 is used as an etch mask, and the BARC film 119, the second SiON film 118, the first amorphous carbon 116, and the first polysilicon film 114 are sequentially etched to form A first polysilicon pattern includes a first structure 114a of the first polysilicon film 114 and a second structure 114b of the first polysilicon film 114. The first polysilicon pattern includes a number of other structures similar to the first and second structures. The residual photoresist pattern 120, the BARC film 119, the second SiON film 118, and the amorphous carbon 116 are then removed.
同樣地,根據在該第一TEOS 112上所形成之間隔物(稍後說明)厚度,部分蝕刻該第一TEOS 112之上部。為何部分蝕刻該上部的理由為:該第二多晶矽圖案(稍後說明)(其係藉由填滿該間隔物間的間隙而形成)之高度係大體上相同於該第一多晶矽圖案114a、114b之高度。若該第一及第二多晶矽圖案之高度不同,則使用該第一及第二多晶矽圖案兩者作為蝕刻遮罩之蝕刻製程是不穩定的,因為該蝕刻遮罩是不均勻的。此能使由該蝕刻製程所形成之蝕刻外形扭曲。為了防止此種扭曲現象,應蝕刻該第一TEOS 112之上部。Likewise, the upper portion of the first TEOS 112 is partially etched according to the thickness of the spacer (described later) formed on the first TEOS 112. The reason why the upper portion is partially etched is that the second polysilicon pattern (described later) (which is formed by filling the gap between the spacers) has a height substantially the same as that of the first polysilicon. The height of the patterns 114a, 114b. If the heights of the first and second polysilicon patterns are different, the etching process using both the first and second polysilicon patterns as an etch mask is unstable because the etching mask is uneven. . This can distort the etched shape formed by the etching process. In order to prevent such distortion, the upper portion of the first TEOS 112 should be etched.
參照第1c圖,於該第一TEOS 112及該第一多晶矽圖案114a、114b上方沈積一作為間隔物之第二TEOS 122。該第二TEOS 122應以低於該第一多晶矽圖案114a、114b之沈積溫度及該第一TEOS 112之沈積溫度來沈積,以防止薄膜抬起(lifting)現象(其由熱應力造成)。此外,因為用以作為該間隔物之沈積材料會影響半導體元件內之微細圖案的CD,故該第二TEOS 122最好使用具有良好階梯覆蓋性之材料來形成。在一實施例中,該第二TEOS 122係使用原子層沈積(ALD)製程來形成。在此,以均勻厚度(例如,大體上相同於該第一多晶矽圖案114a、114b之CD)沈積該第二TEOS 122是關鍵的。Referring to FIG. 1c, a second TEOS 122 as a spacer is deposited over the first TEOS 112 and the first polysilicon patterns 114a, 114b. The second TEOS 122 should be deposited below the deposition temperature of the first polysilicon pattern 114a, 114b and the deposition temperature of the first TEOS 112 to prevent film lift (which is caused by thermal stress). . Further, since the deposition material used as the spacer affects the CD of the fine pattern in the semiconductor element, the second TEOS 122 is preferably formed using a material having good step coverage. In one embodiment, the second TEOS 122 is formed using an atomic layer deposition (ALD) process. Here, depositing the second TEOS 122 with a uniform thickness (eg, substantially the same as the CD of the first polysilicon pattern 114a, 114b) is critical.
該第二TEOS 122應順應該經結合的第一TEOS 112與第一多晶矽圖案114a、114b之形狀,並且於該第一多晶矽圖案之該第一結構114a與第二結構114b之間界定一缺口區域(indented region)(或溝渠)123。該溝渠123之寬度應最好大體上相等於該第一結構114a(或第二結構114b)之寬度。The second TEOS 122 should conform to the shape of the combined first TEOS 112 and first polysilicon patterns 114a, 114b and between the first structure 114a and the second structure 114b of the first polysilicon pattern. An indented region (or ditch) 123 is defined. The width of the trench 123 should preferably be substantially equal to the width of the first structure 114a (or the second structure 114b).
參照第1d與1e圖,於該第二TEOS 122上方形成一第二多晶矽薄膜124,及填入該溝渠123。沈積足夠的第二多晶矽薄膜124以具有大體上相同的平坦化表面(參照第1d圖)是必要的。於該第二多晶矽薄膜124上執行一回蝕刻製程直到大體上露出該第二TEOS 122之上部。因此,如第1e圖中所示,形成一第二多晶矽圖案,其包括該第二多晶矽薄膜124之第一部分124a以及該第二多晶矽薄膜124之第二部分124b。Referring to FIGS. 1d and 1e, a second polysilicon film 124 is formed over the second TEOS 122, and the trench 123 is filled. It is necessary to deposit sufficient second polysilicon film 124 to have substantially the same planarized surface (see Figure 1d). An etch back process is performed on the second polysilicon film 124 until the upper portion of the second TEOS 122 is substantially exposed. Thus, as shown in FIG. 1e, a second polysilicon pattern is formed comprising a first portion 124a of the second polysilicon film 124 and a second portion 124b of the second polysilicon film 124.
參照第1f圖,部分蝕刻該第二TEOS 122以露出該第一多晶矽圖案114a、114b,使得該第二多晶矽圖案之第二部分124b偕同該第一多晶矽圖案之第一結構114a與第二結構114b一起形成線圖案。該第二TEOS 122係使用一回蝕刻製程及一濕式剝離製程來蝕刻。Referring to FIG. 1f, the second TEOS 122 is partially etched to expose the first polysilicon pattern 114a, 114b such that the second portion 124b of the second polysilicon pattern is identical to the first structure of the first polysilicon pattern. 114a forms a line pattern together with the second structure 114b. The second TEOS 122 is etched using an etch back process and a wet strip process.
參照第1g圖,分別使用該第一多晶矽圖案114a、114b及該第二多晶矽圖案124a、124b作為蝕刻遮罩,蝕刻該第一TEOS 112與該第二TEOS 122,以形成一第一TEOS圖案112a與一第二TEOS圖案122a。Referring to FIG. 1g, the first polysilicon pattern 114a, 114b and the second polysilicon pattern 124a, 124b are respectively used as an etch mask, and the first TEOS 112 and the second TEOS 122 are etched to form a first A TEOS pattern 112a and a second TEOS pattern 122a.
參照第1h圖,使用該第一TEOS圖案112a與該第二TEOS圖案122a作為蝕刻遮罩,蝕刻該第一SiON薄膜110、該ONO介電層(沒有顯示)以及該閘極層(沒有顯示),因而形成具有一小間距之微細圖案化第一SiON薄膜110a(其很難使用傳統的曝光製程來形成)。該經圖案化之第一SiON薄膜110a也可被用以蝕刻該基板100。Referring to FIG. 1h, the first TEOS pattern 112a and the second TEOS pattern 122a are used as an etch mask to etch the first SiON film 110, the ONO dielectric layer (not shown), and the gate layer (not shown). Thus, a finely patterned first SiON film 110a having a small pitch (which is difficult to form using a conventional exposure process) is formed. The patterned first SiON film 110a can also be used to etch the substrate 100.
第2圖為說明可實施本實施例之快閃記憶體之胞元區域之平面圖。特別地是,包含在一胞元區域中之複數控制閘極係形成於一具有複數條線形之圖案中,以及形成用以連接一源極選擇線或一汲極選擇線之相互連接區域,以具有配置於該等控制閘極之兩端上的墊形狀。Fig. 2 is a plan view showing a cell region in which the flash memory of the embodiment can be implemented. In particular, the plurality of control gates included in a cell region are formed in a pattern having a plurality of lines and forming interconnecting regions for connecting a source select line or a drain select line to There is a pad shape disposed on both ends of the control gates.
第3a至3g圖為說明依照本發明之實施例使用負型SPT以形成微細圖案之方法之圖解。第3a至3g圖係顯示該快閃記憶體之控制閘極的相互連接區域的製造。Figures 3a through 3g are diagrams illustrating a method of using a negative SPT to form a fine pattern in accordance with an embodiment of the present invention. Figures 3a through 3g show the fabrication of the interconnected regions of the control gates of the flash memory.
參照第3a圖,於一半導體基板(沒有顯示)上方配置一介電層(沒有顯示)。同樣地,於該介電層上沈積一閘極層(沒有顯示)。在此,該閘極層306包括一多晶矽及一矽化鎢。於該閘極層上方形成一第一氮氧化矽(SiON)薄膜310。Referring to Figure 3a, a dielectric layer (not shown) is disposed over a semiconductor substrate (not shown). Similarly, a gate layer (not shown) is deposited over the dielectric layer. Here, the gate layer 306 includes a polysilicon and a tungsten germanium. A first silicon oxynitride (SiON) film 310 is formed over the gate layer.
第一正矽酸四乙酯(TEOS)薄膜312及第一多晶矽薄膜314係沈積在該第一SiON薄膜310上方作為一硬遮罩。一第一非晶碳316及一第二SiON薄膜318係於該第一多晶矽薄膜314上方形成為一硬遮罩,以蝕刻該第一多晶矽薄膜314。A first tetraethyl orthophthalate (TEOS) film 312 and a first polysilicon film 314 are deposited over the first SiON film 310 as a hard mask. A first amorphous carbon 316 and a second SiON film 318 are formed as a hard mask over the first polysilicon film 314 to etch the first polysilicon film 314.
於該第二SiON薄膜318上方塗布一光阻薄膜(沒有顯示)。使用一遮罩(其中界定一具有如期望間距之二倍寬的間距之圖案),於該光阻薄膜上執行曝光及顯影製程以形成一光阻圖案320。為了防止該光阻圖案320於該曝光及顯影製程中被損壞,可於該第二SiON薄膜318及該光阻圖案320之間形成一底部抗反射塗布(BARC)薄膜(沒有顯示)。在此情況下,可於該BARC薄膜上方塗布該光阻薄膜。A photoresist film (not shown) is coated over the second SiON film 318. An exposure and development process is performed on the photoresist film to form a photoresist pattern 320 using a mask in which a pattern having a pitch as wide as twice the desired pitch is defined. In order to prevent the photoresist pattern 320 from being damaged during the exposure and development process, a bottom anti-reflective coating (BARC) film (not shown) may be formed between the second SiON film 318 and the photoresist pattern 320. In this case, the photoresist film can be coated over the BARC film.
參照第3a圖,當不考慮蝕刻偏差時,由該曝光及顯影製程所形成之該光阻圖案320具有1:3之線對間隔物比例。例如,若形成的線具有40nm的CD,則形成具有120nm之CD的間隔物。Referring to Fig. 3a, the photoresist pattern 320 formed by the exposure and development process has a line-to-spacer ratio of 1:3 when etching deviation is not considered. For example, if the formed line has a CD of 40 nm, a spacer having a CD of 120 nm is formed.
參照第3b圖,使用該光阻圖案320作為蝕刻遮罩,依序蝕刻該BARC薄膜(若存在的話)、該第二SiON薄膜318、該第一非晶碳316以及該第一多晶矽薄膜314,以形成一第一多晶矽圖案,其包括該第一多晶矽薄膜314之第一結構314a以及該第一多晶矽薄膜314之第二結構314b。接著移除該殘餘光阻圖案320、該BARC薄膜(若存在的話)、該第二SiON薄膜318以及第一非晶碳316。根據在該第一TEOS薄膜312上所形成之間隔物(稍後說明)厚度而部分蝕刻該第一TEOS薄膜312之上部。Referring to FIG. 3b, the photoresist pattern 320 is used as an etch mask, and the BARC film (if present), the second SiON film 318, the first amorphous carbon 316, and the first polysilicon film are sequentially etched. 314, to form a first polysilicon pattern, comprising a first structure 314a of the first polysilicon film 314 and a second structure 314b of the first polysilicon film 314. The residual photoresist pattern 320, the BARC film (if present), the second SiON film 318, and the first amorphous carbon 316 are then removed. The upper portion of the first TEOS film 312 is partially etched according to the thickness of a spacer (described later) formed on the first TEOS film 312.
參照第3c圖,於該第一TEOS薄膜312及該第一多晶矽圖案314a、314b上方沈積一作為間隔物材料之第二TEOS薄膜322。於該第一多晶矽圖案314a、314b上方所形成之第二TEOS薄膜322係於該第一多晶矽圖案之該第一結構314a與該第二結構314b之間界定一缺口區域(或溝渠)。一第二多晶矽薄膜324(其為一填隙硬遮罩)係於該第二TEOS薄膜322上方形成並填入該缺口區域。沈積該第二多晶矽薄膜324至一充分厚度以提供一大體上均勻的上表面。於該第二多晶矽薄膜324上執行一回蝕刻製程或化學機械研磨(CMP)製程,以露出該第二TEOS薄膜322之部分。所造成的第二多晶矽具有的區域數目係取決於經圖案化之線、相互連接區域、及其類似物的期望數目。例如,第3c圖係說明包括一第一部分324a、一第二部分324b、以及一第三部分324c之該第二多晶矽薄膜324。Referring to FIG. 3c, a second TEOS film 322 as a spacer material is deposited over the first TEOS film 312 and the first polysilicon pattern 314a, 314b. A second TEOS film 322 formed over the first polysilicon pattern 314a, 314b defines a notch region (or a trench) between the first structure 314a and the second structure 314b of the first polysilicon pattern. ). A second polysilicon film 324 (which is a gap-filled hard mask) is formed over the second TEOS film 322 and fills the gap region. The second polysilicon film 324 is deposited to a sufficient thickness to provide a substantially uniform upper surface. An etch back process or a chemical mechanical polishing (CMP) process is performed on the second polysilicon film 324 to expose portions of the second TEOS film 322. The resulting number of regions of the second polysilicon depends on the desired number of patterned lines, interconnected regions, and the like. For example, Figure 3c illustrates the second polysilicon film 324 including a first portion 324a, a second portion 324b, and a third portion 324c.
參照第3d圖,於該第二TEOS薄膜322上執行一回蝕刻製程或一化學機械研磨(CMP)製程。因此,露出該第一多晶矽圖案314a、314b。Referring to FIG. 3d, an etch back process or a chemical mechanical polishing (CMP) process is performed on the second TEOS film 322. Therefore, the first polysilicon patterns 314a, 314b are exposed.
參照第3e圖,於該第二多晶矽圖案324a、324b、324c,該第一多晶矽圖案314a、314b,以及該第二TEOS薄膜322已露出之部分的上方塗布一光阻薄膜(沒有顯示)。於該光阻薄膜上執行一曝光及顯影製程,以形成一第二光阻圖案326,其界定對應於一期望墊形狀之該第二多晶矽圖案324a、324b、324c的邊緣。為了將該第二多晶矽圖案324a、324b、324c形成為準確的墊形狀並防止該等期望墊之對準錯誤,必須精確地執行用以形成該第二光阻圖案326之遮罩製程。特別地,該第二光阻圖案326之形狀係由一對墊圖案決定,以及可為例如第3e圖中所示之階梯形狀。在此情況下,對於每一階梯來說:在水平方向(I-I’),該第二光阻圖案326係以約等於由該第一多晶矽薄膜314之一部分(例如314a)所形成之線圖案與該第一多晶矽薄膜314之該部分之兩側上的該第二TEOS薄膜322之部分之寬度的數量,以及以該第二多晶矽薄膜324之相鄰部分(例如324b)之寬度來延伸;在垂直方向,該第二光阻圖案326係以該等二個連接至二條線圖案之墊圖案所決定之數量來延伸-例如,該第二光阻圖案326可以等於由該第一多晶矽薄膜314之部分所形成之墊圖案長度、於該第一多晶矽薄膜314之該部分的兩側上之該第二TEOS薄膜322之部分的長度、以及該第二多晶矽薄膜324之相鄰部分的長度之數量來延伸。Referring to FIG. 3e, a photoresist film is coated on the second polysilicon pattern 324a, 324b, 324c, the first polysilicon pattern 314a, 314b, and the exposed portion of the second TEOS film 322. display). An exposure and development process is performed on the photoresist film to form a second photoresist pattern 326 defining edges of the second polysilicon patterns 324a, 324b, 324c corresponding to a desired pad shape. In order to form the second polysilicon pattern 324a, 324b, 324c into an accurate pad shape and prevent alignment errors of the desired pads, the mask process for forming the second photoresist pattern 326 must be accurately performed. In particular, the shape of the second photoresist pattern 326 is determined by a pair of pad patterns, and may be, for example, a stepped shape as shown in FIG. 3e. In this case, for each step: in the horizontal direction (I-I'), the second photoresist pattern 326 is formed to be approximately equal to a portion (for example, 314a) of the first polysilicon film 314. The number of widths of the line pattern and portions of the second TEOS film 322 on both sides of the portion of the first polysilicon film 314, and adjacent portions of the second polysilicon film 324 (eg, 324b) Width extends to extend; in the vertical direction, the second photoresist pattern 326 is extended by the number of the two pad patterns connected to the two line patterns - for example, the second photoresist pattern 326 may be equal to a pad pattern length formed by a portion of the first polysilicon film 314, a length of a portion of the second TEOS film 322 on both sides of the portion of the first polysilicon film 314, and the second plurality The number of lengths of adjacent portions of the wafer film 324 extends.
參照第3f圖,使用該光阻圖案326作為一蝕刻遮罩,蝕刻該第二多晶矽圖案324a之已露出部分及該第二TEOS薄膜322之對應部分,以露出該第一TEOS薄膜312。該光阻圖案326係接著被移除。Referring to FIG. 3f, the photoresist pattern 326 is used as an etch mask, and the exposed portion of the second polysilicon pattern 324a and the corresponding portion of the second TEOS film 322 are etched to expose the first TEOS film 312. The photoresist pattern 326 is then removed.
接著分別使用該第一多晶矽圖案314a及該第二多晶矽圖案324a作為蝕刻遮罩,蝕刻該第一TEOS薄膜312及該第二TEOS薄膜322,以於該第一SiON薄膜310上方形成一第一TEOS圖案312a及一第二TEOS圖案322a。Then, the first polysilicon pattern 314a and the second polysilicon pattern 324a are used as an etch mask to etch the first TEOS film 312 and the second TEOS film 322 to form over the first SiON film 310. A first TEOS pattern 312a and a second TEOS pattern 322a.
參照第3g圖,使用該第一TEOS圖案312a及該第二TEOS圖案322a作為蝕刻遮罩,蝕刻該第一SiON薄膜310,因而形成具有一小間距之微細圖案化第一SiON薄膜310a(其很難使用傳統的曝光製程來形成)。Referring to FIG. 3g, the first SiNOS pattern 312a and the second TEOS pattern 322a are used as an etch mask to etch the first SiON film 310, thereby forming a finely patterned first SiON film 310a having a small pitch (which is very Difficult to use the traditional exposure process to form).
形成第2圖中所示之微細圖案以具有複數單元圖案。每一單元圖案包括一對應於控制閘極之線圖案以及對應於一相互連接區域之墊圖案。在自第3a至3g圖所獲得之微細圖案中,形成選自該等單元圖案之第一單元圖案,其對應於該第一多晶矽圖案314a、314b,以及形成對應於該第二多晶矽圖案324a、324b、324c之第二單元圖案。該第一單元圖案及該第二單元圖案係以交替方式設置。The fine pattern shown in Fig. 2 is formed to have a complex unit pattern. Each of the unit patterns includes a line pattern corresponding to the control gate and a pad pattern corresponding to an interconnection region. In the fine pattern obtained from the 3a to 3g patterns, a first unit pattern selected from the unit patterns is formed, which corresponds to the first polysilicon pattern 314a, 314b, and is formed corresponding to the second polycrystal The second unit pattern of the 矽 patterns 324a, 324b, 324c. The first unit pattern and the second unit pattern are arranged in an alternating manner.
在上述實施例中,使用該第二TEOS圖案322a形成蝕刻遮罩,其可形成一微細圖案(其很難以使用光阻薄膜之微影技術來獲得)。然而,蝕刻邊限不大而使用該光阻圖案326以形成該等墊圖案可能具有挑戰性。墊之間的節距狹小而可能由於在曝光製程中使用該光阻圖案326而造成對準錯誤。若發生對準錯誤,則該第二多晶矽圖案324a、324b、324c不會被準確蝕刻,以致使墊圖案依然相互連接而造成元件內的缺陷。In the above embodiment, the second TEOS pattern 322a is used to form an etch mask which can form a fine pattern (which is difficult to obtain by lithography using a photoresist film). However, the etching edge is not large and the use of the photoresist pattern 326 to form the pad patterns can be challenging. The pitch between the pads is narrow and may cause alignment errors due to the use of the photoresist pattern 326 in the exposure process. If an alignment error occurs, the second polysilicon patterns 324a, 324b, 324c are not accurately etched such that the pad patterns are still interconnected to cause defects in the components.
第4a至4g圖為說明依照本發明之實施例使用負型SPT用以形成一微細圖案之方法之圖解。4a through 4g are diagrams illustrating a method of forming a fine pattern using a negative SPT in accordance with an embodiment of the present invention.
參照第4a圖,於一第二氮氧化矽(SiON)薄膜418上方形成具有與第3a圖之光阻圖案不同形狀之第一光阻圖案420。Referring to Fig. 4a, a first photoresist pattern 420 having a shape different from that of the photoresist pattern of Fig. 3a is formed over a second bismuth oxynitride (SiON) film 418.
參照第4a至4g圖,於一半導體基板400上方沈積一介電層(沒有顯示)。同樣地,於該介電層上沈積一閘極層。於該閘極層上方形成一第一氮氧化矽(SiON)薄膜410。Referring to Figures 4a through 4g, a dielectric layer (not shown) is deposited over a semiconductor substrate 400. Similarly, a gate layer is deposited over the dielectric layer. A first silicon oxynitride (SiON) film 410 is formed over the gate layer.
於該第一SiON薄膜410上方形成一第一TEOS 412及一第一多晶矽414作為硬遮罩。於該第一多晶矽414上方形成一第一非晶碳416。該第一非晶碳416及該第二SiON薄膜418係作用為硬遮罩以蝕刻該第一多晶矽414。可於該第二SiON薄膜418與該第一光阻圖案420之間形成一底部抗反射塗布(BARC)薄膜(沒有顯示)。A first TEOS 412 and a first polysilicon 414 are formed over the first SiON film 410 as a hard mask. A first amorphous carbon 416 is formed over the first polysilicon 414. The first amorphous carbon 416 and the second SiON film 418 act as a hard mask to etch the first polysilicon 414. A bottom anti-reflective coating (BARC) film (not shown) may be formed between the second SiON film 418 and the first photoresist pattern 420.
於該第二SiON薄膜418(或該BARC,若存在的話)上方塗布一光阻薄膜(沒有顯示)。使用一遮罩(其中界定一具有如期望間距之二倍寬的間距之控制閘極圖案以及配置於該控制閘極圖案之間的墊圖案),於該光阻薄膜上執行曝光及顯影製程。透過該曝光及顯影製程,所形成之該第一光阻圖案420包括:(1)第一部分420a,其具有其中形成該等控制閘極之線圖案以及其中形成相互連接區域之墊圖案;以及(2)第二部分420b,其具有該等墊圖案之一部分並且沒有線圖案。該第一光阻圖案420具有1:3的線對間隔物比。例如,當不考慮蝕刻偏差時,若形成的線具有40nm的臨界尺寸(CD),則於形成具有120nm之CD的間隔物。A photoresist film (not shown) is applied over the second SiON film 418 (or the BARC, if present). An exposure and development process is performed on the photoresist film using a mask in which a control gate pattern having a pitch as wide as twice the desired pitch and a pad pattern disposed between the control gate patterns are defined. Through the exposure and development process, the first photoresist pattern 420 is formed to include: (1) a first portion 420a having a line pattern in which the control gates are formed and a pad pattern in which interconnected regions are formed; and 2) A second portion 420b having a portion of the pad patterns and having no line pattern. The first photoresist pattern 420 has a line-to-spacer ratio of 1:3. For example, when the etching deviation is not considered, if the formed line has a critical dimension (CD) of 40 nm, a spacer having a CD of 120 nm is formed.
參照第4b圖,使用該第一光阻圖案420作為蝕刻遮罩,依序蝕刻該BARC薄膜(若存在的話)、該第二SiON薄膜418、該第一非晶碳416以及該第一多晶矽414,以形成一第一多晶矽圖案,其包括該第一多晶矽414之第一部分414a(具有對應於該第一光阻圖案420之該第一部分420a之形狀(亦即線圖案及墊圖案)的第一形狀),以及該第一多晶矽414之第二部分414b(具有對應於該第一光阻圖案420之該第二部分420b之形狀(亦即,部分墊圖案但沒有線圖案)的第二形狀)。接著移除該殘餘第一光阻圖案420、BARC(若存在的話)、第二SiON薄膜418以及非晶碳416。根據在該第一TEOS 412上所形成之間隔物(稍後說明)厚度而部分蝕刻該第一TEOS 412之上部。Referring to FIG. 4b, the first photoresist pattern 420 is used as an etch mask, and the BARC film (if present), the second SiON film 418, the first amorphous carbon 416, and the first polycrystal are sequentially etched.矽 414 to form a first polysilicon pattern including a first portion 414a of the first polysilicon 414 (having a shape corresponding to the first portion 420a of the first photoresist pattern 420 (ie, a line pattern and a first shape of the pad pattern), and a second portion 414b of the first polysilicon 414 (having a shape corresponding to the second portion 420b of the first photoresist pattern 420 (ie, a partial pad pattern but not The second shape of the line pattern). The residual first photoresist pattern 420, BARC (if present), second SiON film 418, and amorphous carbon 416 are then removed. The upper portion of the first TEOS 412 is partially etched according to the thickness of the spacer (described later) formed on the first TEOS 412.
參照第4c圖,於該第一TEOS 412之已露出部分及該第一多晶矽圖案414a、414b的上方沈積第二TEOS 422作為一間隔物材料。於第二TEOS 422上方形成一第二多晶矽424(其為一填隙硬遮罩)。與第1d圖中所示之充分沈積該第二多晶矽以具有一平坦化表面之製程不同的是,於該第二TEOS 422上方沈積具有一大體上均勻度厚度之該第二多晶矽424,使得於設置該第一多晶矽圖案414a、414b之區域中所形成之該第二多晶矽424比其它區域還高。Referring to FIG. 4c, a second TEOS 422 is deposited as a spacer material over the exposed portion of the first TEOS 412 and over the first polysilicon pattern 414a, 414b. A second polysilicon 424 (which is a shim hard mask) is formed over the second TEOS 422. Different from the process of sufficiently depositing the second polysilicon as shown in FIG. 1D to have a planarized surface, depositing the second polysilicon having a substantially uniform thickness over the second TEOS 422 424, such that the second polysilicon 424 formed in the region where the first polysilicon pattern 414a, 414b is disposed is higher than other regions.
接著於該第二TEOS 422及該第二多晶矽424上執行一乾式回蝕刻製程或濕式剝離製程。因此,於寬廣區域中所形成的具有較低高度之該第二多晶矽424之部分以及該第二TEOS 422之上部會被實質地移除。然而,該第二多晶矽424會殘餘在該等第一多晶矽圖案414a、414b之間之該第二TEOS 422之缺口區域中。此外,於該第一多晶矽414之該第一部分414a及該第二部分414b之間殘餘包括具有線形之該第二多晶矽424之部分的第二多晶矽圖案424a(亦即,該第二多晶矽圖案之線圖案會殘餘在該第一多晶矽圖案之線圖案之間)。參照第4d圖,接著蝕刻該第二TEOS 422,使得該第一多晶矽圖案414a、414b及該第二多晶矽圖案424a殘餘在該第一TEOS 412上方,並使得一第二TEOS圖案422a殘餘在該第二多晶矽圖案424a下方。A dry etch back process or a wet strip process is then performed on the second TEOS 422 and the second polysilicon 424. Therefore, the portion of the second polysilicon 424 having a lower height formed in the wide region and the upper portion of the second TEOS 422 are substantially removed. However, the second polysilicon 424 may remain in the notch region of the second TEOS 422 between the first polysilicon patterns 414a, 414b. In addition, a second polysilicon pattern 424a having a portion of the second polysilicon 424 having a line shape is left between the first portion 414a and the second portion 414b of the first polysilicon 414 (ie, the A line pattern of the second polysilicon pattern may remain between the line patterns of the first polysilicon pattern. Referring to FIG. 4d, the second TEOS 422 is then etched such that the first polysilicon pattern 414a, 414b and the second polysilicon pattern 424a remain above the first TEOS 412, and a second TEOS pattern 422a is caused. Remaining below the second polysilicon pattern 424a.
參照第4e圖,於用以相互連接該第二多晶矽圖案424a與該第一多晶矽414之該第二部分414b之區域中形成一第二光阻圖案428(亦即,相互連接該第二多晶矽圖案之線圖案與該第一多晶矽圖案之墊圖案之部分)。一般來說,該第二多晶矽圖案424a係使用一第二遮罩製程而連接至該第一多晶矽414之該第二部分414b。因為執行設計法則的元件用之SPT製程以克服傳統設備之顯影限制,故要求圖案疊放程度(overlaying degree)小於10nm。Referring to FIG. 4e, a second photoresist pattern 428 is formed in a region for interconnecting the second polysilicon pattern 424a and the second portion 414b of the first polysilicon 414 (ie, interconnecting the a line pattern of the second polysilicon pattern and a portion of the pad pattern of the first polysilicon pattern). Generally, the second polysilicon pattern 424a is coupled to the second portion 414b of the first polysilicon 414 using a second mask process. Since the components of the design rule are used in SPT processes to overcome the development limitations of conventional devices, the overlaying degree is required to be less than 10 nm.
透過該第二遮罩製程所形成之該第二光阻圖案428係與第3e圖中所示之該等第二光阻圖案326類似;然而,用以形成該第二光阻圖案428之製程邊限係更充裕。例如,該第二光阻圖案428之尺寸範圍可為自該第二多晶矽圖案424a與該第一多晶矽414之該第二部分414b之間的最小接觸,至包括該第二多晶矽圖案424a與該第一多晶矽414之該第二部分414b之尺寸。亦即,該第二光阻圖案428具有該最小接觸的必要條件,以及具有用以隔開該相互連接區域與鄰近圖案(亦即,該第一多晶矽414之第一部分414a)的充分條件。此外,若該第二光阻圖案428於上述範圍內具有適當尺寸,則該第二遮罩製程之對準邊限可獲改善。因此,該第二光阻圖案428此應藉由精確執行該曝光及顯影製程所形成之該第二光阻圖案326具有更多優點。The second photoresist pattern 428 formed by the second mask process is similar to the second photoresist pattern 326 shown in FIG. 3e; however, the process for forming the second photoresist pattern 428 The margin system is more abundant. For example, the second photoresist pattern 428 may have a size ranging from a minimum contact between the second polysilicon pattern 424a and the second portion 414b of the first polysilicon 414 to include the second poly The size of the second pattern 424b of the first polysilicon 414 is 矽 pattern 424a. That is, the second photoresist pattern 428 has the necessary conditions for the minimum contact, and has sufficient conditions for spacing the interconnected region and the adjacent pattern (ie, the first portion 414a of the first polysilicon 414). . In addition, if the second photoresist pattern 428 has an appropriate size within the above range, the alignment margin of the second mask process can be improved. Therefore, the second photoresist pattern 428 should have more advantages by precisely performing the exposure and development process of the second photoresist pattern 326.
參照第4f圖,使用該第一多晶矽圖案414a、414b、該第二多晶矽圖案424a以及該第二光阻圖案428作為蝕刻遮罩,蝕刻該第一TEOS 412,以形成一第一TEOS圖案412a。接著移除該第一多晶矽圖案414a、414b,該第二多晶矽圖案424a以及該第二光阻圖案428以露出該第一TEOS圖案412a與該第一SiON薄膜410。Referring to FIG. 4f, the first polysilicon pattern 414a, 414b, the second polysilicon pattern 424a, and the second photoresist pattern 428 are used as an etch mask to etch the first TEOS 412 to form a first TEOS pattern 412a. The first polysilicon pattern 414a, 414b, the second polysilicon pattern 424a and the second photoresist pattern 428 are then removed to expose the first TEOS pattern 412a and the first SiON film 410.
參照第4g圖,使用該第一TEOS圖案412a作為蝕刻遮罩,蝕刻該第一SiON薄膜410,因而形成具有一小間距之微細圖案化第一SiON薄膜410a(其無法使用傳統的曝光製程來形成)。將該微細圖案形成具有複數單元圖案。每一單元圖案包括對應於一控制閘極之線圖案以及對應於一相互連接區域之墊圖案。參照第4a至4f圖,該單元圖案包括:對應於該第一多晶矽圖案414a、414b之第一單元圖案與第二單元圖案之墊圖案;對應於該第一多晶矽圖案414a、414b之第一單元圖案之線圖案;以及對應於該第二多晶矽圖案424a之該等第二單元圖案之線圖案。該第二單元圖案之墊圖案及該線圖案係藉由使用該第二光阻圖案428之蝕刻製程而相互連接。Referring to FIG. 4g, the first SiOF pattern 412a is used as an etch mask to etch the first SiON film 410, thereby forming a finely patterned first SiON film 410a having a small pitch (which cannot be formed using a conventional exposure process) ). The fine pattern is formed to have a complex unit pattern. Each of the unit patterns includes a line pattern corresponding to a control gate and a pad pattern corresponding to an interconnection region. Referring to FIGS. 4a to 4f, the unit pattern includes: a pad pattern corresponding to the first unit pattern and the second unit pattern of the first polysilicon pattern 414a, 414b; corresponding to the first polysilicon pattern 414a, 414b a line pattern of the first unit pattern; and a line pattern corresponding to the second unit patterns of the second polysilicon pattern 424a. The pad pattern of the second unit pattern and the line pattern are connected to each other by an etching process using the second photoresist pattern 428.
在第4a至4g圖所示之實施例中,使用一蝕刻製程,形成配置於該第二TEOS圖案422a之部分間的第二多晶矽圖案424a,以具有一線形狀。利用此原理,以該第二光阻圖案428將該第二多晶矽圖案424a與該第一多晶矽414之第二部分414b連接起來,使得該第二多晶矽圖案424a與該第一多晶矽414之第二部分414b可被用來作為一蝕刻遮罩,以蝕刻該第一TEOS 412以及接下來的該第一SiON薄膜410。In the embodiment shown in FIGS. 4a to 4g, an etching process is used to form a second polysilicon pattern 424a disposed between portions of the second TEOS pattern 422a to have a line shape. Using the second photoresist pattern 428, the second polysilicon pattern 424a is connected to the second portion 414b of the first polysilicon 414 such that the second polysilicon pattern 424a and the first The second portion 414b of the polysilicon 414 can be used as an etch mask to etch the first TEOS 412 and the subsequent first SiON film 410.
相較於第3a至3g圖中所示之用以形成複數微細圖案(每一圖案包括一控制閘極圖案及一相互連接區域)之實施例,第4a至4g圖中所示之實施例,係使用該光阻圖案(其中使用該曝光製程僅圖案化該相互連接區域)而可於製程中增加配置於該等微細圖案之間之微細圖案的疊放邊限。換言之,藉由使用第4e圖中所示之該第二光阻圖案428之該蝕刻製程,比起藉由使用該光阻圖案326之該蝕刻製程來界定第3e圖中所示之該等微細圖案之墊區域的精確邊界來說,可更易於確保較大的操作邊限。Compared to the embodiment shown in FIGS. 3a to 3g for forming a plurality of fine patterns (each pattern including a control gate pattern and an interconnection region), the embodiments shown in FIGS. 4a to 4g, The photoresist pattern is used in which only the interconnection region is patterned using the exposure process, and the stacking margin of the fine pattern disposed between the fine patterns can be increased in the process. In other words, by using the etching process of the second photoresist pattern 428 shown in FIG. 4e, the fineness shown in FIG. 3e is defined compared to the etching process by using the photoresist pattern 326. The precise boundaries of the pad area of the pattern make it easier to ensure a large operating margin.
特別地是,將該第一多晶矽414之該第二部分414b形成為具有“”形,藉以使用該第二遮罩製程,於用以形成墊之製程中增加疊放邊限。將具有“「”形之圖案附著在該第二部分414b的旁邊,其將與該第二部分414b及該第二TEOS圖案422a連接。因此,可獲得一線圖案,其中包括具有“├”形之該第二多晶矽圖案424a(該第二多晶矽424係於隨後之回蝕刻或濕式移除製程中被蝕刻)。In particular, the second portion 414b of the first polysilicon 414 is formed to have " a shape by which the second mask process is used to increase the stacking margin in the process for forming the pad. A pattern having a "" shape is attached to the second portion 414b, which will be associated with the second The portion 414b and the second TEOS pattern 422a are connected. Thus, a line pattern can be obtained which includes the second polysilicon pattern 424a having a "├" shape (which is etched in a subsequent etch back or wet removal process).
如上所述,本發明提供一種墊佈局,以助於一使用基本原理而形成相互連接區域,其中當施加負型SPT法時,形成於間隔物沈積材料之間的填隙多晶矽的最終外形會被形成為具有線(line)。As described above, the present invention provides a pad layout to facilitate the formation of interconnected regions using a basic principle in which the final shape of the interstitial polysilicon formed between the spacer deposition materials is applied when the negative SPT method is applied. It is formed to have a line.
同樣地,因為在移除該填隙多晶矽以露出該間隔物沈積材料時,可施加一乾式回蝕刻或濕式移除製程,故本發明可增加疊放邊限。Likewise, the present invention can increase the stacking margin because a dry etchback or wet removal process can be applied when the interstitial polysilicon is removed to expose the spacer deposition material.
本發明之上述實施例係示範性而不侷限於此。各種改變及等效物均為可行的。本發明並不侷限於在此所述之沈積類型、蝕刻研磨、以及圖案化步驟。本發明也不侷限於任何特定類型之半導體元件。例如,本發明可被實施於動態隨機存取記憶體(DRAM)元件或非揮發性記憶體元件中。對本案所揭露之內容而言,其它附加、刪減、或修飾係顯而易見且將視為落入隨附申請專利範圍之範圍內。The above embodiments of the present invention are exemplary and not limited thereto. Various changes and equivalents are possible. The invention is not limited to the deposition types, etch grinding, and patterning steps described herein. The invention is also not limited to any particular type of semiconductor component. For example, the invention can be implemented in a dynamic random access memory (DRAM) component or a non-volatile memory component. Other additions, deletions, or modifications are obvious to the scope of the disclosure and will be considered to fall within the scope of the accompanying claims.
100...半導體基板100. . . Semiconductor substrate
110...第一SiON薄膜110. . . First SiON film
110a...已圖案化之第一SiON薄膜110a. . . Patterned first SiON film
112...第一正矽酸四乙酯(TEOS)薄膜112. . . First tetraethyl orthophthalate (TEOS) film
112a...第一TEOS圖案112a. . . First TEOS pattern
114...第一多晶矽薄膜114. . . First polysilicon film
114a...第一多晶矽薄膜之第一結構114a. . . First structure of the first polysilicon film
114b...第一多晶矽薄膜之第二結構114b. . . Second structure of the first polysilicon film
116...第一非晶碳116. . . First amorphous carbon
118...第二SiON薄膜118. . . Second SiON film
119...底部抗反射塗布(BARC)薄膜119. . . Bottom anti-reflective coating (BARC) film
120...光阻圖案120. . . Resistive pattern
122...第二TEOS122. . . Second TEOS
122a...第二TEOS圖案122a. . . Second TEOS pattern
123...缺口區域(或溝渠)123. . . Gap area (or ditch)
124...第二多晶矽薄膜124. . . Second polysilicon film
124a...第二多晶矽薄膜之第一部分124a. . . The first part of the second polysilicon film
124b...第二多晶矽薄膜之第二部分124b. . . The second part of the second polysilicon film
300...半導體基板300. . . Semiconductor substrate
310...第一SiON薄膜310. . . First SiON film
310a...己圖案化之第一SiON薄膜310a. . . Patterned first SiON film
312...第一正矽酸四乙酯(TEOS)薄膜312. . . First tetraethyl orthophthalate (TEOS) film
312a...第一TEOS圖案312a. . . First TEOS pattern
314...第一多晶矽薄膜314. . . First polysilicon film
314a...第一多晶矽之第一結構314a. . . First structure of the first polysilicon
314b...第一多晶矽之第二結構314b. . . Second structure of the first polysilicon
316...第一非晶碳316. . . First amorphous carbon
318...第二SiON薄膜318. . . Second SiON film
320...光阻圖案320. . . Resistive pattern
322...第二TEOS薄膜322. . . Second TEOS film
322a...第二TEOS圖案322a. . . Second TEOS pattern
324...第二多晶矽薄膜324. . . Second polysilicon film
324a...第二多晶矽薄膜之第一部分324a. . . The first part of the second polysilicon film
324b...第二多晶矽薄膜之第二部分324b. . . The second part of the second polysilicon film
324c...第二多晶矽薄膜之第三部分324c. . . The third part of the second polysilicon film
326...第二光阻圖案326. . . Second photoresist pattern
400...半導體基板400. . . Semiconductor substrate
410...第一氮氧化矽(SiON)薄膜410. . . First bismuth oxynitride (SiON) film
410a...已圖案化之第一SiON薄膜410a. . . Patterned first SiON film
412...第一TEOS412. . . First TEOS
412a...第一TEOS圖案412a. . . First TEOS pattern
414...第一多晶矽414. . . First polysilicon
414a...第一多晶矽之第一部分414a. . . The first part of the first polysilicon
414b...第一多晶矽之第二部分414b. . . The second part of the first polysilicon
416...第一非晶碳416. . . First amorphous carbon
418...第二氮氧化矽(SiON)薄膜418. . . Second bismuth oxynitride (SiON) film
420...第一光阻圖案420. . . First photoresist pattern
420a...第一光阻圖案之第一部分420a. . . The first part of the first photoresist pattern
420b...第一光阻圖案之第二部分420b. . . The second part of the first photoresist pattern
422...第二TEOS422. . . Second TEOS
422a...第二TEOS圖案422a. . . Second TEOS pattern
424...第二多晶矽424. . . Second polysilicon
424a...第二多晶矽圖案424a. . . Second polysilicon pattern
428...第二光阻圖案428. . . Second photoresist pattern
第1a至1h圖為說明負型間隔物圖案化技術(SPT)之剖面圖。Figures 1a through 1h are cross-sectional views illustrating a negative spacer patterning technique (SPT).
第2圖為說明快閃記憶體之胞元區域之平面圖。Figure 2 is a plan view showing the cell area of the flash memory.
第3a至3g圖為說明依照本發明之實施例藉由負型SPT用以形成微細圖案之方法之圖解。Figures 3a through 3g are diagrams illustrating a method for forming a fine pattern by a negative SPT in accordance with an embodiment of the present invention.
第4a至4g圖為說明依照本發明之實施例藉由負型SPT用以形成微細圖案之方法之圖解。4a through 4g are diagrams illustrating a method for forming a fine pattern by a negative SPT in accordance with an embodiment of the present invention.
410...第一氮氧化矽(SiON)薄膜410. . . First bismuth oxynitride (SiON) film
412...第一TEOS412. . . First TEOS
414...第一多晶矽薄膜414. . . First polysilicon film
416...第一非晶碳416. . . First amorphous carbon
418...第二氮氧化矽(SiON)薄膜418. . . Second bismuth oxynitride (SiON) film
420...第一光阻圖案420. . . First photoresist pattern
420a...第一光阻圖案之第一部分420a. . . The first part of the first photoresist pattern
420b...第一光阻圖案之第二部分420b. . . The second part of the first photoresist pattern
Claims (19)
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KR (1) | KR101024712B1 (en) |
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KR100966976B1 (en) * | 2007-12-28 | 2010-06-30 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device |
KR101565796B1 (en) * | 2008-12-24 | 2015-11-06 | 삼성전자주식회사 | Semiconductor device and method of forming patterns for semiconductor device |
US8222140B2 (en) * | 2009-12-23 | 2012-07-17 | Intel Corporation | Pitch division patterning techniques |
KR101120176B1 (en) * | 2010-04-13 | 2012-02-27 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device |
KR101139462B1 (en) | 2010-08-30 | 2012-05-02 | 에스케이하이닉스 주식회사 | Method for forming semiconductor device |
KR101150586B1 (en) * | 2010-10-05 | 2012-06-08 | 에스케이하이닉스 주식회사 | Method for forming semiconductor device |
CN103022085A (en) * | 2011-09-26 | 2013-04-03 | 朱江 | Semiconductor chip with ultra-junction structure and manufacturing method thereof |
CN103426810B (en) * | 2012-05-15 | 2015-09-30 | 中芯国际集成电路制造(上海)有限公司 | Double-patterning method in back-end process |
KR102389816B1 (en) | 2015-08-25 | 2022-04-22 | 삼성전자주식회사 | Semiconductor device and method of forming patterns for semiconductor device |
CN109427686B (en) * | 2017-08-29 | 2021-04-13 | 联华电子股份有限公司 | Isolation structure and forming method thereof |
KR20210041683A (en) * | 2019-10-07 | 2021-04-16 | 에스케이하이닉스 주식회사 | Method of forming patterns using double spacers |
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KR101024712B1 (en) | 2011-03-24 |
KR20090067016A (en) | 2009-06-24 |
JP2012216846A (en) | 2012-11-08 |
TW200939301A (en) | 2009-09-16 |
CN101465282B (en) | 2014-06-25 |
JP2009152613A (en) | 2009-07-09 |
CN101465282A (en) | 2009-06-24 |
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