TWI483288B - Method for manufacturing a semiconductor device - Google Patents

Description

Method of manufacturing a semiconductor component

The present invention claims the priority of Korean Patent Application No. 10-2007-0134549 and No. 10-2008-0049896, filed on Dec. 20, 2007 and May 28, 2008. For reference.

BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a method of fabricating a semiconductor device, and more particularly to a method of fabricating a semiconductor device that can increase the stacking margin in a process to obtain a pad layout for use in applying a negative SPT method. Helps to form an interconnected area.

Since semiconductor elements become highly integrated, it is necessary to reduce the pattern size and pitch for forming circuits. According to Rayleigh's equation, the size of the fine pattern in the semiconductor component is proportional to the wavelength of the light used for the exposure process, and inversely proportional to the size of the lens within the exposer used for the exposure process. Therefore, a method for reducing the wavelength of light in the exposure process or enlarging the lens size used in the exposure process has been used to form a fine pattern.

Various optical processes have overcome the technical limitations in the manufacture of semiconductor components. For example, masks have been finely designed to adjust the amount of light emitted through the mask; new photoresist materials have been developed; lenses using high numerical aperture have been developed; and transfer masks have been developed.

However, due to the limitations of exposure and resolution capabilities (using currently available sources such as KrF and ArF), it is difficult to form the desired pattern width and spacing. For example, exposure techniques have been developed to fabricate patterns of about 60 nm, but making patterns of less than 60 nm becomes uncertain.

Various studies have been conducted to form photoresist patterns having fine sizes and pitches.

One of those studies describes the dual patterning technique (DPT) that performs a dual light process to form a pattern.

In one example of a DPT, a double exposure etch technique (DE2T) includes exposing and etching a first pattern having a double cycle, and exposing and etching a second pattern having a double cycle between the first patterns. In another illustration of DPT, a spacer patterning technique (SPT) involves forming a pattern using a spacer. Both the DE2T and the SPT can be performed using a negative type and a positive type.

In the negative type DE2T, the pattern obtained from the first mask process is removed in a second mask process to form a desired pattern. In the positive type DE2T, a pattern obtained from a first mask process and a second mask process is combined to form a desired pattern. However, the use of two different masks for the DE2T requires additional processing and adds complexity. Similarly, in the patterns obtained by the first mask process and the second mask process which are spaced apart from each other, mis-alignment (which is called overlay) may occur.

In another aspect, the SPT is a self-aligned method that includes performing a masking process to pattern cell regions to prevent alignment errors.

However, in order to form a pad pattern in the core and surrounding circuit regions, particularly in the outer blocks of the mats, an additional masking process is required to isolate each pad pattern. Generally, when the plurality of linear fine patterns disposed in the central block of the cell pad are formed by the SPT, the outer block of the cell pad is not patterned. After forming the plurality of line patterns in the central block, each of the pad patterns connected to each of the line type fine patterns is formed by patterning an outer block of the cell pad. When the outer block is patterned, a mask process for determining the shape of the pad patterns is performed. An additional masking process to remove the odds and ends in the outer block is also performed. Likewise, it is difficult to control the deposition uniformity of the spacer formation regions and to adjust the critical dimension (CD) by the spacer etching process.

Although in the case of a multilayer structure including lines/spacers, the SPT is applied separately to the NAND flash process, if the brick wall pattern is disposed in a DRAM or a complex pattern layer, by using the SPT Forming a pattern is difficult. In this case, the DE2T is generally used.

Various embodiments of the present invention are directed to providing a pad layout to facilitate the use of a basic principle to form an interconnected region in which gap fill poly is formed between spacer deposition materials when a negative SPT process is applied. The final shape is formed to have a line.

Various embodiments of the present invention are directed to increasing stacking margins when a dry etchback or wet removal process can be applied when the interstitial polysilicon is removed to expose the spacer deposition material.

According to an embodiment of the present invention, a method of fabricating a semiconductor device includes: forming an etch target layer over a semiconductor substrate having an underlying structure; forming a first mask pattern over the etch target layer; and including the first mask pattern Forming a spacer material layer having a uniform thickness over the etch target layer; forming a second mask pattern on the notch region of the spacer material layer; and using the first mask pattern and the second mask pattern as The mask is etched and the etch target layer is etched to form a fine pattern.

According to an embodiment of the invention, a method of fabricating a semiconductor device includes sequentially forming an etch target layer, a first hard mask material layer, a first spacer material layer, and a second hard mask material layer over the semiconductor substrate; Etching the second layer of hard mask material to form a second hard mask pattern; etching the first layer of spacer material with the second hard mask pattern as an etch mask to form a first spacer; Forming a spacer material layer and a second separation material layer over the first hard mask material layer; partially etching the spacer material layer and the second spacer material layer until the first separation is exposed, thereby exposing the spacer a layer of material to form a second spacer between the first spacers; to etch the spacer material layer and the first hard mask material layer by using the first spacer and the second spacer as an etch mask Forming a first hard mask pattern; and etching the etch target layer with the first hard mask pattern as an etch mask to form a fine pattern.

According to an embodiment of the invention, a method of fabricating a semiconductor device includes: forming an etch target layer over a semiconductor substrate having an underlying structure; forming a first mask material layer over the etch target layer and selectively etching the first a mask material layer to form a first mask pattern including a pad pattern and a line pattern; forming a second mask pattern including a line pattern, wherein the line pattern is formed between the first mask patterns; forming a third a mask pattern connecting the second mask pattern to the pad pattern of the first mask pattern; and using the first mask pattern, the second mask pattern, and the third mask pattern as an etch mask A mask is etched to etch the target layer to form a fine pattern.

Figures 1a through 1h are cross-sectional views illustrating a negative spacer patterning technique (SPT). Figures 1a through 1h depict a diagram when forming a control gate of a flash memory. The invention can be used in other structures within the flash memory component or other type of memory component.

Referring to Figure 1a, an element isolation film (not shown) defines an active region formed in a semiconductor substrate (not shown). An oxide/nitride/oxide (ONO) dielectric layer (not shown) is deposited over the semiconductor substrate. Similarly, a gate layer (not shown) is deposited over the ONO dielectric layer. Here, the gate layer includes a polycrystalline germanium (poly) and tungsten germanium. A first silicon oxynitride (SiON) film 110 is formed over the gate layer. Here, multiple layers are disposed under the first SiON film 110 for forming a control gate of the flash memory over the semiconductor substrate. However, in other embodiments, the etch target layer under the first SiON film 110 may be any layer included in other fine patterns such as capacitors, wires, and the like.

A first tetraethyl orthosilicate (TEOS) film 112 and a first polysilicon film 114 are deposited over the first SiON film 110 as a hard mask.

A first amorphous carbon 116 and a second SiON film 118 are formed as a hard mask over the first polysilicon film 114 to etch the first polysilicon film 114. The first polysilicon film 114 is not easily etched using a photoresist mask. A bottom anti-reflective coating (BARC) film 119 is formed over the second SiON film 118.

A photoresist film (not shown) is applied over the BARC film 119. An exposure and development process is performed on the photoresist film to form a photoresist pattern 120 using a mask in which a pattern having a pitch as wide as twice the desired pitch is defined. For example, when the etching bias is not considered, if the formed line has a critical dimension (CD) of 40 nm, a spacer having a CD of 120 nm is formed between two adjacent lines. That is, the ratio of the line to the spacer is 1 to 3.

Referring to FIG. 1b, the photoresist pattern 120 is used as an etch mask, and the BARC film 119, the second SiON film 118, the first amorphous carbon 116, and the first polysilicon film 114 are sequentially etched to form A first polysilicon pattern includes a first structure 114a of the first polysilicon film 114 and a second structure 114b of the first polysilicon film 114. The first polysilicon pattern includes a number of other structures similar to the first and second structures. The residual photoresist pattern 120, the BARC film 119, the second SiON film 118, and the amorphous carbon 116 are then removed.

Likewise, the upper portion of the first TEOS 112 is partially etched according to the thickness of the spacer (described later) formed on the first TEOS 112. The reason why the upper portion is partially etched is that the second polysilicon pattern (described later) (which is formed by filling the gap between the spacers) has a height substantially the same as that of the first polysilicon. The height of the patterns 114a, 114b. If the heights of the first and second polysilicon patterns are different, the etching process using both the first and second polysilicon patterns as an etch mask is unstable because the etching mask is uneven. . This can distort the etched shape formed by the etching process. In order to prevent such distortion, the upper portion of the first TEOS 112 should be etched.

Referring to FIG. 1c, a second TEOS 122 as a spacer is deposited over the first TEOS 112 and the first polysilicon patterns 114a, 114b. The second TEOS 122 should be deposited below the deposition temperature of the first polysilicon pattern 114a, 114b and the deposition temperature of the first TEOS 112 to prevent film lift (which is caused by thermal stress). . Further, since the deposition material used as the spacer affects the CD of the fine pattern in the semiconductor element, the second TEOS 122 is preferably formed using a material having good step coverage. In one embodiment, the second TEOS 122 is formed using an atomic layer deposition (ALD) process. Here, depositing the second TEOS 122 with a uniform thickness (eg, substantially the same as the CD of the first polysilicon pattern 114a, 114b) is critical.

The second TEOS 122 should conform to the shape of the combined first TEOS 112 and first polysilicon patterns 114a, 114b and between the first structure 114a and the second structure 114b of the first polysilicon pattern. An indented region (or ditch) 123 is defined. The width of the trench 123 should preferably be substantially equal to the width of the first structure 114a (or the second structure 114b).

Referring to FIGS. 1d and 1e, a second polysilicon film 124 is formed over the second TEOS 122, and the trench 123 is filled. It is necessary to deposit sufficient second polysilicon film 124 to have substantially the same planarized surface (see Figure 1d). An etch back process is performed on the second polysilicon film 124 until the upper portion of the second TEOS 122 is substantially exposed. Thus, as shown in FIG. 1e, a second polysilicon pattern is formed comprising a first portion 124a of the second polysilicon film 124 and a second portion 124b of the second polysilicon film 124.

Referring to FIG. 1f, the second TEOS 122 is partially etched to expose the first polysilicon pattern 114a, 114b such that the second portion 124b of the second polysilicon pattern is identical to the first structure of the first polysilicon pattern. 114a forms a line pattern together with the second structure 114b. The second TEOS 122 is etched using an etch back process and a wet strip process.

Referring to FIG. 1g, the first polysilicon pattern 114a, 114b and the second polysilicon pattern 124a, 124b are respectively used as an etch mask, and the first TEOS 112 and the second TEOS 122 are etched to form a first A TEOS pattern 112a and a second TEOS pattern 122a.

Referring to FIG. 1h, the first TEOS pattern 112a and the second TEOS pattern 122a are used as an etch mask to etch the first SiON film 110, the ONO dielectric layer (not shown), and the gate layer (not shown). Thus, a finely patterned first SiON film 110a having a small pitch (which is difficult to form using a conventional exposure process) is formed. The patterned first SiON film 110a can also be used to etch the substrate 100.

Fig. 2 is a plan view showing a cell region in which the flash memory of the embodiment can be implemented. In particular, the plurality of control gates included in a cell region are formed in a pattern having a plurality of lines and forming interconnecting regions for connecting a source select line or a drain select line to There is a pad shape disposed on both ends of the control gates.

Figures 3a through 3g are diagrams illustrating a method of using a negative SPT to form a fine pattern in accordance with an embodiment of the present invention. Figures 3a through 3g show the fabrication of the interconnected regions of the control gates of the flash memory.

Referring to Figure 3a, a dielectric layer (not shown) is disposed over a semiconductor substrate (not shown). Similarly, a gate layer (not shown) is deposited over the dielectric layer. Here, the gate layer 306 includes a polysilicon and a tungsten germanium. A first silicon oxynitride (SiON) film 310 is formed over the gate layer.

A first tetraethyl orthophthalate (TEOS) film 312 and a first polysilicon film 314 are deposited over the first SiON film 310 as a hard mask. A first amorphous carbon 316 and a second SiON film 318 are formed as a hard mask over the first polysilicon film 314 to etch the first polysilicon film 314.

A photoresist film (not shown) is coated over the second SiON film 318. An exposure and development process is performed on the photoresist film to form a photoresist pattern 320 using a mask in which a pattern having a pitch as wide as twice the desired pitch is defined. In order to prevent the photoresist pattern 320 from being damaged during the exposure and development process, a bottom anti-reflective coating (BARC) film (not shown) may be formed between the second SiON film 318 and the photoresist pattern 320. In this case, the photoresist film can be coated over the BARC film.

Referring to Fig. 3a, the photoresist pattern 320 formed by the exposure and development process has a line-to-spacer ratio of 1:3 when etching deviation is not considered. For example, if the formed line has a CD of 40 nm, a spacer having a CD of 120 nm is formed.

Referring to FIG. 3b, the photoresist pattern 320 is used as an etch mask, and the BARC film (if present), the second SiON film 318, the first amorphous carbon 316, and the first polysilicon film are sequentially etched. 314, to form a first polysilicon pattern, comprising a first structure 314a of the first polysilicon film 314 and a second structure 314b of the first polysilicon film 314. The residual photoresist pattern 320, the BARC film (if present), the second SiON film 318, and the first amorphous carbon 316 are then removed. The upper portion of the first TEOS film 312 is partially etched according to the thickness of a spacer (described later) formed on the first TEOS film 312.

Referring to FIG. 3c, a second TEOS film 322 as a spacer material is deposited over the first TEOS film 312 and the first polysilicon pattern 314a, 314b. A second TEOS film 322 formed over the first polysilicon pattern 314a, 314b defines a notch region (or a trench) between the first structure 314a and the second structure 314b of the first polysilicon pattern. ). A second polysilicon film 324 (which is a gap-filled hard mask) is formed over the second TEOS film 322 and fills the gap region. The second polysilicon film 324 is deposited to a sufficient thickness to provide a substantially uniform upper surface. An etch back process or a chemical mechanical polishing (CMP) process is performed on the second polysilicon film 324 to expose portions of the second TEOS film 322. The resulting number of regions of the second polysilicon depends on the desired number of patterned lines, interconnected regions, and the like. For example, Figure 3c illustrates the second polysilicon film 324 including a first portion 324a, a second portion 324b, and a third portion 324c.

Referring to FIG. 3d, an etch back process or a chemical mechanical polishing (CMP) process is performed on the second TEOS film 322. Therefore, the first polysilicon patterns 314a, 314b are exposed.

Referring to FIG. 3e, a photoresist film is coated on the second polysilicon pattern 324a, 324b, 324c, the first polysilicon pattern 314a, 314b, and the exposed portion of the second TEOS film 322. display). An exposure and development process is performed on the photoresist film to form a second photoresist pattern 326 defining edges of the second polysilicon patterns 324a, 324b, 324c corresponding to a desired pad shape. In order to form the second polysilicon pattern 324a, 324b, 324c into an accurate pad shape and prevent alignment errors of the desired pads, the mask process for forming the second photoresist pattern 326 must be accurately performed. In particular, the shape of the second photoresist pattern 326 is determined by a pair of pad patterns, and may be, for example, a stepped shape as shown in FIG. 3e. In this case, for each step: in the horizontal direction (I-I'), the second photoresist pattern 326 is formed to be approximately equal to a portion (for example, 314a) of the first polysilicon film 314. The number of widths of the line pattern and portions of the second TEOS film 322 on both sides of the portion of the first polysilicon film 314, and adjacent portions of the second polysilicon film 324 (eg, 324b) Width extends to extend; in the vertical direction, the second photoresist pattern 326 is extended by the number of the two pad patterns connected to the two line patterns - for example, the second photoresist pattern 326 may be equal to a pad pattern length formed by a portion of the first polysilicon film 314, a length of a portion of the second TEOS film 322 on both sides of the portion of the first polysilicon film 314, and the second plurality The number of lengths of adjacent portions of the wafer film 324 extends.

Referring to FIG. 3f, the photoresist pattern 326 is used as an etch mask, and the exposed portion of the second polysilicon pattern 324a and the corresponding portion of the second TEOS film 322 are etched to expose the first TEOS film 312. The photoresist pattern 326 is then removed.

Then, the first polysilicon pattern 314a and the second polysilicon pattern 324a are used as an etch mask to etch the first TEOS film 312 and the second TEOS film 322 to form over the first SiON film 310. A first TEOS pattern 312a and a second TEOS pattern 322a.

Referring to FIG. 3g, the first SiNOS pattern 312a and the second TEOS pattern 322a are used as an etch mask to etch the first SiON film 310, thereby forming a finely patterned first SiON film 310a having a small pitch (which is very Difficult to use the traditional exposure process to form).

The fine pattern shown in Fig. 2 is formed to have a complex unit pattern. Each of the unit patterns includes a line pattern corresponding to the control gate and a pad pattern corresponding to an interconnection region. In the fine pattern obtained from the 3a to 3g patterns, a first unit pattern selected from the unit patterns is formed, which corresponds to the first polysilicon pattern 314a, 314b, and is formed corresponding to the second polycrystal The second unit pattern of the 矽 patterns 324a, 324b, 324c. The first unit pattern and the second unit pattern are arranged in an alternating manner.

In the above embodiment, the second TEOS pattern 322a is used to form an etch mask which can form a fine pattern (which is difficult to obtain by lithography using a photoresist film). However, the etching edge is not large and the use of the photoresist pattern 326 to form the pad patterns can be challenging. The pitch between the pads is narrow and may cause alignment errors due to the use of the photoresist pattern 326 in the exposure process. If an alignment error occurs, the second polysilicon patterns 324a, 324b, 324c are not accurately etched such that the pad patterns are still interconnected to cause defects in the components.

4a through 4g are diagrams illustrating a method of forming a fine pattern using a negative SPT in accordance with an embodiment of the present invention.

Referring to Fig. 4a, a first photoresist pattern 420 having a shape different from that of the photoresist pattern of Fig. 3a is formed over a second bismuth oxynitride (SiON) film 418.

Referring to Figures 4a through 4g, a dielectric layer (not shown) is deposited over a semiconductor substrate 400. Similarly, a gate layer is deposited over the dielectric layer. A first silicon oxynitride (SiON) film 410 is formed over the gate layer.

A first TEOS 412 and a first polysilicon 414 are formed over the first SiON film 410 as a hard mask. A first amorphous carbon 416 is formed over the first polysilicon 414. The first amorphous carbon 416 and the second SiON film 418 act as a hard mask to etch the first polysilicon 414. A bottom anti-reflective coating (BARC) film (not shown) may be formed between the second SiON film 418 and the first photoresist pattern 420.

A photoresist film (not shown) is applied over the second SiON film 418 (or the BARC, if present). An exposure and development process is performed on the photoresist film using a mask in which a control gate pattern having a pitch as wide as twice the desired pitch and a pad pattern disposed between the control gate patterns are defined. Through the exposure and development process, the first photoresist pattern 420 is formed to include: (1) a first portion 420a having a line pattern in which the control gates are formed and a pad pattern in which interconnected regions are formed; and 2) A second portion 420b having a portion of the pad patterns and having no line pattern. The first photoresist pattern 420 has a line-to-spacer ratio of 1:3. For example, when the etching deviation is not considered, if the formed line has a critical dimension (CD) of 40 nm, a spacer having a CD of 120 nm is formed.

Referring to FIG. 4b, the first photoresist pattern 420 is used as an etch mask, and the BARC film (if present), the second SiON film 418, the first amorphous carbon 416, and the first polycrystal are sequentially etched.矽 414 to form a first polysilicon pattern including a first portion 414a of the first polysilicon 414 (having a shape corresponding to the first portion 420a of the first photoresist pattern 420 (ie, a line pattern and a first shape of the pad pattern), and a second portion 414b of the first polysilicon 414 (having a shape corresponding to the second portion 420b of the first photoresist pattern 420 (ie, a partial pad pattern but not The second shape of the line pattern). The residual first photoresist pattern 420, BARC (if present), second SiON film 418, and amorphous carbon 416 are then removed. The upper portion of the first TEOS 412 is partially etched according to the thickness of the spacer (described later) formed on the first TEOS 412.

Referring to FIG. 4c, a second TEOS 422 is deposited as a spacer material over the exposed portion of the first TEOS 412 and over the first polysilicon pattern 414a, 414b. A second polysilicon 424 (which is a shim hard mask) is formed over the second TEOS 422. Different from the process of sufficiently depositing the second polysilicon as shown in FIG. 1D to have a planarized surface, depositing the second polysilicon having a substantially uniform thickness over the second TEOS 422 424, such that the second polysilicon 424 formed in the region where the first polysilicon pattern 414a, 414b is disposed is higher than other regions.

A dry etch back process or a wet strip process is then performed on the second TEOS 422 and the second polysilicon 424. Therefore, the portion of the second polysilicon 424 having a lower height formed in the wide region and the upper portion of the second TEOS 422 are substantially removed. However, the second polysilicon 424 may remain in the notch region of the second TEOS 422 between the first polysilicon patterns 414a, 414b. In addition, a second polysilicon pattern 424a having a portion of the second polysilicon 424 having a line shape is left between the first portion 414a and the second portion 414b of the first polysilicon 414 (ie, the A line pattern of the second polysilicon pattern may remain between the line patterns of the first polysilicon pattern. Referring to FIG. 4d, the second TEOS 422 is then etched such that the first polysilicon pattern 414a, 414b and the second polysilicon pattern 424a remain above the first TEOS 412, and a second TEOS pattern 422a is caused. Remaining below the second polysilicon pattern 424a.

Referring to FIG. 4e, a second photoresist pattern 428 is formed in a region for interconnecting the second polysilicon pattern 424a and the second portion 414b of the first polysilicon 414 (ie, interconnecting the a line pattern of the second polysilicon pattern and a portion of the pad pattern of the first polysilicon pattern). Generally, the second polysilicon pattern 424a is coupled to the second portion 414b of the first polysilicon 414 using a second mask process. Since the components of the design rule are used in SPT processes to overcome the development limitations of conventional devices, the overlaying degree is required to be less than 10 nm.

The second photoresist pattern 428 formed by the second mask process is similar to the second photoresist pattern 326 shown in FIG. 3e; however, the process for forming the second photoresist pattern 428 The margin system is more abundant. For example, the second photoresist pattern 428 may have a size ranging from a minimum contact between the second polysilicon pattern 424a and the second portion 414b of the first polysilicon 414 to include the second poly The size of the second pattern 424b of the first polysilicon 414 is 矽 pattern 424a. That is, the second photoresist pattern 428 has the necessary conditions for the minimum contact, and has sufficient conditions for spacing the interconnected region and the adjacent pattern (ie, the first portion 414a of the first polysilicon 414). . In addition, if the second photoresist pattern 428 has an appropriate size within the above range, the alignment margin of the second mask process can be improved. Therefore, the second photoresist pattern 428 should have more advantages by precisely performing the exposure and development process of the second photoresist pattern 326.

Referring to FIG. 4f, the first polysilicon pattern 414a, 414b, the second polysilicon pattern 424a, and the second photoresist pattern 428 are used as an etch mask to etch the first TEOS 412 to form a first TEOS pattern 412a. The first polysilicon pattern 414a, 414b, the second polysilicon pattern 424a and the second photoresist pattern 428 are then removed to expose the first TEOS pattern 412a and the first SiON film 410.

Referring to FIG. 4g, the first SiOF pattern 412a is used as an etch mask to etch the first SiON film 410, thereby forming a finely patterned first SiON film 410a having a small pitch (which cannot be formed using a conventional exposure process) ). The fine pattern is formed to have a complex unit pattern. Each of the unit patterns includes a line pattern corresponding to a control gate and a pad pattern corresponding to an interconnection region. Referring to FIGS. 4a to 4f, the unit pattern includes: a pad pattern corresponding to the first unit pattern and the second unit pattern of the first polysilicon pattern 414a, 414b; corresponding to the first polysilicon pattern 414a, 414b a line pattern of the first unit pattern; and a line pattern corresponding to the second unit patterns of the second polysilicon pattern 424a. The pad pattern of the second unit pattern and the line pattern are connected to each other by an etching process using the second photoresist pattern 428.

In the embodiment shown in FIGS. 4a to 4g, an etching process is used to form a second polysilicon pattern 424a disposed between portions of the second TEOS pattern 422a to have a line shape. Using the second photoresist pattern 428, the second polysilicon pattern 424a is connected to the second portion 414b of the first polysilicon 414 such that the second polysilicon pattern 424a and the first The second portion 414b of the polysilicon 414 can be used as an etch mask to etch the first TEOS 412 and the subsequent first SiON film 410.

Compared to the embodiment shown in FIGS. 3a to 3g for forming a plurality of fine patterns (each pattern including a control gate pattern and an interconnection region), the embodiments shown in FIGS. 4a to 4g, The photoresist pattern is used in which only the interconnection region is patterned using the exposure process, and the stacking margin of the fine pattern disposed between the fine patterns can be increased in the process. In other words, by using the etching process of the second photoresist pattern 428 shown in FIG. 4e, the fineness shown in FIG. 3e is defined compared to the etching process by using the photoresist pattern 326. The precise boundaries of the pad area of the pattern make it easier to ensure a large operating margin.

In particular, the second portion 414b of the first polysilicon 414 is formed to have " a shape by which the second mask process is used to increase the stacking margin in the process for forming the pad. A pattern having a "" shape is attached to the second portion 414b, which will be associated with the second The portion 414b and the second TEOS pattern 422a are connected. Thus, a line pattern can be obtained which includes the second polysilicon pattern 424a having a "├" shape (which is etched in a subsequent etch back or wet removal process).

As described above, the present invention provides a pad layout to facilitate the formation of interconnected regions using a basic principle in which the final shape of the interstitial polysilicon formed between the spacer deposition materials is applied when the negative SPT method is applied. It is formed to have a line.

Likewise, the present invention can increase the stacking margin because a dry etchback or wet removal process can be applied when the interstitial polysilicon is removed to expose the spacer deposition material.

The above embodiments of the present invention are exemplary and not limited thereto. Various changes and equivalents are possible. The invention is not limited to the deposition types, etch grinding, and patterning steps described herein. The invention is also not limited to any particular type of semiconductor component. For example, the invention can be implemented in a dynamic random access memory (DRAM) component or a non-volatile memory component. Other additions, deletions, or modifications are obvious to the scope of the disclosure and will be considered to fall within the scope of the accompanying claims.

100. . . Semiconductor substrate

110. . . First SiON film

110a. . . Patterned first SiON film

112. . . First tetraethyl orthophthalate (TEOS) film

112a. . . First TEOS pattern

114. . . First polysilicon film

114a. . . First structure of the first polysilicon film

114b. . . Second structure of the first polysilicon film

116. . . First amorphous carbon

118. . . Second SiON film

119. . . Bottom anti-reflective coating (BARC) film

120. . . Resistive pattern

122. . . Second TEOS

122a. . . Second TEOS pattern

123. . . Gap area (or ditch)

124. . . Second polysilicon film

124a. . . The first part of the second polysilicon film

124b. . . The second part of the second polysilicon film

300. . . Semiconductor substrate

310. . . First SiON film

310a. . . Patterned first SiON film

312. . . First tetraethyl orthophthalate (TEOS) film

312a. . . First TEOS pattern

314. . . First polysilicon film

314a. . . First structure of the first polysilicon

314b. . . Second structure of the first polysilicon

316. . . First amorphous carbon

318. . . Second SiON film

320. . . Resistive pattern

322. . . Second TEOS film

322a. . . Second TEOS pattern

324. . . Second polysilicon film

324a. . . The first part of the second polysilicon film

324b. . . The second part of the second polysilicon film

324c. . . The third part of the second polysilicon film

326. . . Second photoresist pattern

400. . . Semiconductor substrate

410. . . First bismuth oxynitride (SiON) film

410a. . . Patterned first SiON film

412. . . First TEOS

412a. . . First TEOS pattern

414. . . First polysilicon

414a. . . The first part of the first polysilicon

414b. . . The second part of the first polysilicon

416. . . First amorphous carbon

418. . . Second bismuth oxynitride (SiON) film

420. . . First photoresist pattern

420a. . . The first part of the first photoresist pattern

420b. . . The second part of the first photoresist pattern

422. . . Second TEOS

422a. . . Second TEOS pattern

424. . . Second polysilicon

424a. . . Second polysilicon pattern

428. . . Second photoresist pattern

Figures 1a through 1h are cross-sectional views illustrating a negative spacer patterning technique (SPT).

Figure 2 is a plan view showing the cell area of the flash memory.

Figures 3a through 3g are diagrams illustrating a method for forming a fine pattern by a negative SPT in accordance with an embodiment of the present invention.

4a through 4g are diagrams illustrating a method for forming a fine pattern by a negative SPT in accordance with an embodiment of the present invention.

410. . . First bismuth oxynitride (SiON) film

412. . . First TEOS

414. . . First polysilicon film

416. . . First amorphous carbon

418. . . Second bismuth oxynitride (SiON) film

420. . . First photoresist pattern

420a. . . The first part of the first photoresist pattern

420b. . . The second part of the first photoresist pattern

Claims (19)

A method of fabricating a semiconductor device, the method comprising: forming an etch target layer over a semiconductor substrate having an underlying structure; forming a first mask pattern over the etch target layer, the first mask pattern including a first portion and a second portion Forming a spacer material layer having a substantially uniform thickness over the etch target layer and the first mask pattern, the spacer material layer defining between the first portion and the second portion of the first mask pattern An indented region; forming a second mask pattern in the recess region defined by the spacer material layer; and etching the first mask pattern and the second mask pattern as an etch mask The target layer is etched to form an etch target layer having a desired pattern. The method of claim 1, wherein the forming the second mask pattern comprises: forming a second mask material layer over the gap region, the second mask material layer completely covering the spacer material layer; and etching The second layer of masking material exposes the upper portion of the layer of spacer material such that the second mask pattern is defined within the region of the recess. The method of claim 2, further comprising: etching the spacer material layer to expose the first mask pattern; and using a mask having a shape corresponding to the desired pattern, selective The second mask material layer is etched. The method of claim 1, wherein the desired pattern comprises a plurality of first unit patterns corresponding to the first mask pattern and a plurality of second unit patterns corresponding to the second mask pattern, wherein the first unit patterns And the second unit patterns are arranged in an alternating manner, wherein the first unit patterns and the second unit patterns have substantially the same width. The method of claim 1, wherein the desired pattern comprises: a plurality of first unit patterns including a pad pattern and a line pattern corresponding to the first mask pattern; and a plurality of second mask patterns, including corresponding to the first a pad pattern of the second mask pattern and a line pattern corresponding to the second mask pattern, wherein the pad patterns of the second unit patterns and the line patterns are mutually etched by using an additional mask etching process connection. A method of fabricating a semiconductor device, the method comprising: sequentially forming an etch target layer, a first hard mask material layer, a first spacer material layer, and a second hard mask material layer over the semiconductor substrate; selectively etching the second a layer of hard mask material to form a second hard mask pattern; using the second hard mask pattern as an etch mask, etching the first layer of spacer material to form a first spacer comprising the first portion and the second portion; Forming a spacer material layer and a second spacer material layer on the first hard mask material layer and the first partition; partially etching the spacer material layer and the second spacer material layer until Exposing the first portion and the second portion of the first spacer material layer, thereby partially exposing the spacer material layer and forming a second spacer disposed between the first and second portions of the first partition; The first portion and the exposed portion of the second partition serve as an etch mask, etching the spacer material layer and the first hard mask material layer to form a first hard mask pattern; and using the first hard mask The mask pattern serves as an etch mask, and the etch target layer is etched to form an etch target layer having a desired pattern. The method of claim 6, wherein the first partition has a pitch having a width that is twice the distance between the desired patterns, the method further comprising: forming a nitrogen oxide over the second hard mask pattern material layer.矽 film. The method of claim 7, further comprising forming a bottom anti-reflective coating (BARC) film over the yttrium oxynitride film. The method of claim 6, wherein the second layer of hard mask material comprises amorphous carbon. The method of claim 6, wherein the first layer of hard mask material and the layer of spacer material comprise the same material. The method of claim 10, wherein forming the first spacer further comprises etching the first hard mask material layer such that an upper surface of the spacer material layer and a bottom surface of the etched first spacer material layer Generally parallel. The method of claim 10, wherein the first hard mask material The layer and the spacer material layer contain TEOS. The method of claim 6, wherein the first separator material layer and the second separator material layer comprise the same material. The method of claim 13, wherein the first separator material layer and the second separator material layer comprise polycrystalline germanium. The method of claim 6, wherein the second spacer material layer is formed to have a substantially uniform thickness, wherein the second spacer is formed by partially etching a given depth of the second spacer material layer. The method of claim 15, wherein the spacer material layer and the second spacer material layer are partially etched by a dry etch back process, a wet etch process, or a CMP process. The method of claim 6, wherein the second separator material layer has a substantially planarized surface, wherein the first partition and the second partition have substantially the same pitch. A method of fabricating a semiconductor device, the method comprising: forming an etch target layer over a semiconductor substrate having an underlying structure; forming a first mask material layer over the etch target layer and selectively etching the first mask material layer to Forming a first mask pattern including a plurality of pad patterns and line patterns; forming a spacer material layer over the first mask pattern and the etch target layer; forming a second mask material layer over the spacer material layer; Etching the spacer material layer to expose the first mask pattern and form a second mask pattern including a line pattern, wherein the line pattern is formed between the line patterns of the first mask pattern; and a third mask pattern is formed in an area for the second The line pattern of the mask pattern is interconnected with a portion of the pad pattern of the first mask pattern; and the first mask pattern, the second mask pattern, and the third mask pattern are used as an etch mask, The etch target layer is etched to form a patterned etch target layer. The method of claim 18, wherein the forming the second mask pattern comprises: forming the pad pattern of the first mask pattern to have a concave shape, and forming the second mask pattern to have a connection to the The horizontal part of the vertical part.