CN103022085A - Semiconductor chip with ultra-junction structure and manufacturing method thereof - Google Patents

Semiconductor chip with ultra-junction structure and manufacturing method thereof Download PDF

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Publication number
CN103022085A
CN103022085A CN2011102873795A CN201110287379A CN103022085A CN 103022085 A CN103022085 A CN 103022085A CN 2011102873795 A CN2011102873795 A CN 2011102873795A CN 201110287379 A CN201110287379 A CN 201110287379A CN 103022085 A CN103022085 A CN 103022085A
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CN
China
Prior art keywords
semiconductor
layer
type semiconductor
conductive type
wafer
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Application number
CN2011102873795A
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Chinese (zh)
Inventor
朱江
盛况
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朱江
盛况
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Application filed by 朱江, 盛况 filed Critical 朱江
Priority to CN2011102873795A priority Critical patent/CN103022085A/en
Publication of CN103022085A publication Critical patent/CN103022085A/en

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Abstract

The invention discloses a semiconductor chip with an ultra-junction structure and a manufacturing method thereof. Relatively narrow and ideal columnar P-type semiconductor and N-type semiconductor areas can be achieved. Thus, relatively high impurity doping concentration of the columnar P-type semiconductor and N-type semiconductor areas can be achieved, and the electrical parameter characteristic and the reliability of an apparatus are improved.

Description

A kind of super-junction structure semiconductor wafer and preparation method thereof

Technical field

The present invention relates to a kind of super knot knot ditch semiconductor wafer, the invention still further relates to a kind of preparation method of super knot knot ditch semiconductor wafer.

Background technology

Energy realization height is withstand voltage and semiconductor chip structure low on-resistance is to present the P type semiconductor of column and the structure that the N type semiconductor zone alternately is arranged side by side, and the P type semiconductor of column and N type semiconductor are perpendicular to wafer surface.Be set as desired value by impurity concentration and width with P type semiconductor and N type semiconductor, when applying reverse pressure drop, can realize high withstand voltage.This kind structure is called super-junction structure.

Known super-junction structure semiconductor chip structure and manufacture method are as follows:

The first, the certain thickness N-type epitaxial loayer of deposit arranges mask and injects p type impurity, and annealing forms the P-type conduction layer.Then repeatedly repeat above-mentioned technological process, form alternate configurations P type semiconductor and N type semiconductor zone.The semiconductor wafer manufacture craft of this kind super-junction structure is loaded down with trivial details, needs about 7 times photoetching implantation annealing technique, and the PN junction face presents waveform, affects the reverse voltage endurance of wafer.

The second, by a plurality of grooves of formation in the N-type epitaxial loayer, thereby the angle-tilt ion implantation annealing that carries out p type impurity arranges P type columnar semiconductor zone, then imbeds dielectric between P type columnar semiconductor zone, obtains super-junction structure.The semiconductor wafer injection technology control difficulty of this kind super-junction structure is larger, easily forms in vertical direction inhomogeneous p type impurity CONCENTRATION DISTRIBUTION, thereby has influence on the wafer voltage endurance.,

The third carries out the N-type epitaxial loayer and forms, and etching forms groove, then carries out P type epitaxial loayer and forms, and etching forms groove, carries out the N-type epitaxial loayer again and forms, and etching forms groove, fills at last dielectric in groove.The manufacture craft of the semiconductor wafer of this kind super-junction structure needs more repeatedly anisotropic dry etch process to control P type semiconductor and the N type semiconductor area distribution of column, easily affect the columnar semiconductor planform, thereby affect wafer voltage endurance and reliability.

Summary of the invention

The present invention is directed to the problems referred to above and propose, a kind of super knot knot ditch semiconductor wafer and preparation method thereof is provided.

A kind of super-junction structure semiconductor wafer is characterized in that: comprising: substrate layer, a kind of conductive type semiconductor material; A plurality of the first semiconductor layers are separated from each other and are arranged on the substrate layer, are the first conductive type semiconductor material; A plurality of the second semiconductor layers are separated from each other and are arranged on the substrate layer, and with the alternately isolation of the first semiconductor layer, be the first conductive type semiconductor material; A plurality of the 3rd semiconductor layers between the first semiconductor layer and the second semiconductor layer, are the second conductive type semiconductor material; Wherein, be provided with a plurality of PN junctions with the semiconductor wafer surface vertical direction.

The preparation method of described super-junction structure semiconductor wafer is characterized in that: comprise the steps:

Form the first conductive type semiconductor material epitaxy layer in a kind of conductive type semiconductor material substrate; In epitaxial loayer, form a plurality of grooves; Form insulating barrier on the surface; Carry out anisotropic etch; Form the first conductive type semiconductor material epitaxy layer by directed outer layer growth; The erosion removal insulating barrier; Form the second conductive type semiconductor material epitaxy layer on the surface; Effects on surface carries out grinding and polishing, and the degree of depth of grinding and polishing is for to expose the first conductive type semiconductor material epitaxy layer in wafer surface.

Semiconductor wafer with super-junction structure of the present invention, the P type semiconductor of column and N type semiconductor zone are made of epitaxial loayer, can realize that the P type semiconductor of column and the impurity concentration in N type semiconductor zone evenly distribute in vertical direction, P type semiconductor and N type semiconductor zone form by an anisotropic dry etch process, be easier to control the column structure in P type semiconductor and N type semiconductor zone on the technique, can be perpendicular to semiconductor chip structure in the easy formation of the faying face of PN junction, therefore the evenly super pn junction p n wafer of expansion of a kind of depletion layer can be provided, improve the reverse voltage endurance of wafer and device reliability.

Preparation method with semiconductor wafer of super-junction structure of the present invention, can use less photoetching process and anisotropic dry etch process to realize the manufacturing of device, production technology is simpler, and product structure is compacter, reduce the production cycle of device, reduced the production cost of device.This kind preparation method is not so that the width of the second semiconductor layer and the 3rd semiconductor layer is subjected to the restriction of lithographic line width, realize column P type semiconductor and the N type semiconductor zone of relative narrower, thereby can realize relatively high impurity doping content to column P type semiconductor and N type semiconductor zone, resistance when reducing the device forward conduction, the current density of raising device forward conduction.

Description of drawings

Fig. 1 is a kind of generalized section with semiconductor wafer of super-junction structure of the present invention.

Fig. 2 is the generalized section of one embodiment of the present invention technique first step.

Fig. 3 is the generalized section of one embodiment of the present invention technique second step.

Fig. 4 is one embodiment of the present invention technique generalized section in the 3rd step.

Fig. 5 is one embodiment of the present invention technique generalized section in the 6th step.

Fig. 6 is one embodiment of the present invention technique generalized section in the 7th step.

Fig. 7 is one embodiment of the present invention technique generalized section in the 9th step.

Fig. 8 is one embodiment of the present invention technique generalized section in the 9th step.

Wherein,

1, substrate layer;

2, the first semiconductor layer;

3, the second semiconductor layer;

4, the 3rd semiconductor layer;

5, oxide layer.

Embodiment

Embodiment

Fig. 1 is a kind of generalized section with super-junction structure semiconductor wafer of the present invention, describes semiconductor device of the present invention in detail below in conjunction with Fig. 1.

A kind of semiconductor wafer with super-junction structure comprises: substrate layer 1, be N conductive type semiconductor silicon materials, and the doping content of phosphorus atoms is 1E20cm-3; The first semiconductor layer 2 is positioned on the substrate layer 1, is the semiconductor silicon material of N conduction type, and width is 2 μ m, and thickness is 20 μ m, and the doping content of phosphorus atoms is 1E16cm-3; The second semiconductor layer 3 between the first semiconductor layer 2, is the semiconductor silicon material of N conduction type, and width is 1 μ m, and thickness is 20 μ m, and the doping content of phosphorus atoms is 2E16cm-3; The 3rd semiconductor layer 4 between the first semiconductor layer 2 and the second semiconductor layer 3, is the semiconductor silicon material of P conduction type, and width is 1 μ m, and thickness is 20 μ m, and the doping content of phosphorus atoms is 2E16cm-3.

Its manufacture craft comprises the steps:

The first step, doping content at phosphorus atoms is 1E20cm-3 semiconductor silicon material substrate layer 1 superficial growth phosphorus atoms doped epitaxial layer, form the first semiconductor layer 2, then carry out high-temperature oxydation, form oxide layer 5 in epi-layer surface, remove surface portion oxide layer 5 by lithography corrosion process, as shown in Figure 2;

Second step by anisotropic dry etch process, forms a plurality of grooves in the first semiconductor layer 2, again carry out high-temperature oxydation, and remove the surface portion oxide layer, as shown in Figure 3;

In the 3rd step, form oxide layer 5 at surface deposition silicon dioxide, as shown in Figure 4;

In the 4th step, carry out the silicon dioxide anisotropic etch, as shown in Figure 5;

The 5th goes on foot, and forms the second semiconductor layer 3 of the doping of phosphorus atoms by directed outer layer growth, carries out the second semiconductor layer 3 semiconductor silicon materials and anti-carves erosion, as shown in Figure 6;

In the 6th step, erosion removal oxide layer 5 is carried out high-temperature oxydation, the erosion removal oxide layer, as shown in Figure 7;

In the 7th step, the atom doped epitaxial loayer of growth boron forms the 3rd semiconductor layer 4, as shown in Figure 8;

In the 8th step, effects on surface carries out grinding and polishing, and the degree of depth of grinding and polishing is exposing surface the first semiconductor layer 2 and the second semiconductor layer 3, as shown in Figure 1;

Semiconductor wafer with super-junction structure of the present invention, the P type semiconductor of column and N type semiconductor zone are made of epitaxial loayer, can realize that the P type semiconductor of column and the impurity concentration in N type semiconductor zone evenly distribute in vertical direction, P type semiconductor and N type semiconductor zone form by an anisotropic dry etch process, be easier to control the column structure in P type semiconductor and N type semiconductor zone on the technique, can perpendicular to semiconductor chip structure, improve the reverse voltage endurance of wafer and device reliability in the easy formation of the faying face of PN junction.Preparation method of the present invention is not so that the width of the second semiconductor layer and the 3rd semiconductor layer is subjected to the restriction of lithographic line width, realize column P type semiconductor and the N type semiconductor zone of relative narrower, thereby can realize relatively high impurity doping content to column P type semiconductor and N type semiconductor zone, resistance when reducing the device forward conduction, the current density of raising device forward conduction.

Preparation method with semiconductor wafer of super-junction structure of the present invention, can use less photoetching process and anisotropic dry etch process to realize the manufacturing of device, production technology is simpler, and product structure is compacter, reduce the production cycle of device, reduced the production cost of device.

Set forth the present invention by above-mentioned example, also can adopt other example to realize the present invention simultaneously, the present invention is not limited to above-mentioned instantiation, so the present invention is by the claims circumscription.

Claims (6)

1. super-junction structure semiconductor wafer is characterized in that: comprising:
Substrate layer, a kind of conductive type semiconductor material; A plurality of
The first semiconductor layer is separated from each other and is arranged on the substrate layer, is the first conductive type semiconductor material; A plurality of
The second semiconductor layer is separated from each other and is arranged on the substrate layer, and with the alternately isolation of the first semiconductor layer, be the first conductive type semiconductor material; A plurality of
The 3rd semiconductor layer between the first semiconductor layer and the second semiconductor layer, is the second conductive type semiconductor material;
Wherein, be provided with a plurality of PN junctions with the semiconductor wafer surface vertical direction.
2. semiconductor wafer as claimed in claim 1, it is characterized in that: described the 3rd semiconductor layer all contacts with the second semiconductor layer with the first semiconductor layer.
3. semiconductor wafer as claimed in claim 1, it is characterized in that: described the first semiconductor layer can not contact mutually with the second semiconductor layer.
4. the preparation method of super-junction structure semiconductor wafer as claimed in claim 1 is characterized in that: comprise the steps:
1) forms the first conductive type semiconductor material epitaxy layer in a kind of conductive type semiconductor material substrate;
2) in epitaxial loayer, form a plurality of grooves;
3) form insulating barrier on the surface;
4) carry out anisotropic etch;
5) form the first conductive type semiconductor material epitaxy layer by directed outer layer growth;
6) erosion removal insulating barrier;
7) form the second conductive type semiconductor material epitaxy layer on the surface;
8) effects on surface carries out grinding and polishing.
5. preparation method as claimed in claim 4, it is characterized in that: described epitaxial loayer in the vertical direction impurities concentration distribution is even.
6. preparation method as claimed in claim 4, it is characterized in that: the degree of depth of described grinding and polishing is for exposing the first conductive type semiconductor material epitaxy layer in wafer surface.
CN2011102873795A 2011-09-26 2011-09-26 Semiconductor chip with ultra-junction structure and manufacturing method thereof CN103022085A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
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Application Number Priority Date Filing Date Title
CN2011102873795A CN103022085A (en) 2011-09-26 2011-09-26 Semiconductor chip with ultra-junction structure and manufacturing method thereof

Publications (1)

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CN103022085A true CN103022085A (en) 2013-04-03

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060197152A1 (en) * 2005-03-01 2006-09-07 Kabushiki Kaisha Toshiba Semiconductor device
CN101388336A (en) * 2007-09-13 2009-03-18 三洋电机株式会社 Semiconductor crystal manufacture method
CN101465282A (en) * 2007-12-20 2009-06-24 海力士半导体有限公司 Method for manufacturing a semiconductor device
CN101465278A (en) * 2007-12-20 2009-06-24 海力士半导体有限公司 Method for manufacturing a semiconductor device
JP2009224606A (en) * 2008-03-17 2009-10-01 Shin Etsu Handotai Co Ltd Manufacturing method of semiconductor element having superjunction structure

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060197152A1 (en) * 2005-03-01 2006-09-07 Kabushiki Kaisha Toshiba Semiconductor device
CN101388336A (en) * 2007-09-13 2009-03-18 三洋电机株式会社 Semiconductor crystal manufacture method
CN101465282A (en) * 2007-12-20 2009-06-24 海力士半导体有限公司 Method for manufacturing a semiconductor device
CN101465278A (en) * 2007-12-20 2009-06-24 海力士半导体有限公司 Method for manufacturing a semiconductor device
JP2009224606A (en) * 2008-03-17 2009-10-01 Shin Etsu Handotai Co Ltd Manufacturing method of semiconductor element having superjunction structure

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