CN113900353A - Manufacturing method for improving etching efficiency - Google Patents
Manufacturing method for improving etching efficiency Download PDFInfo
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- CN113900353A CN113900353A CN202111219997.6A CN202111219997A CN113900353A CN 113900353 A CN113900353 A CN 113900353A CN 202111219997 A CN202111219997 A CN 202111219997A CN 113900353 A CN113900353 A CN 113900353A
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/68—Preparation processes not covered by groups G03F1/20 - G03F1/50
- G03F1/80—Etching
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- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
- G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
- G02B6/122—Basic optical elements, e.g. light-guiding paths
- G02B6/124—Geodesic lenses or integrated gratings
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- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
- G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
- G02B6/122—Basic optical elements, e.g. light-guiding paths
- G02B6/125—Bends, branchings or intersections
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- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
- G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
- G02B6/13—Integrated optical circuits characterised by the manufacturing method
- G02B6/132—Integrated optical circuits characterised by the manufacturing method by deposition of thin films
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- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
- G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
- G02B6/13—Integrated optical circuits characterised by the manufacturing method
- G02B6/136—Integrated optical circuits characterised by the manufacturing method by etching
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- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
- G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
- G02B2006/12166—Manufacturing methods
- G02B2006/12176—Etching
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Optics & Photonics (AREA)
- Optical Integrated Circuits (AREA)
Abstract
The invention provides a manufacturing method for improving etching efficiency, which is used for solving the problem that in the existing semiconductor chip manufacturing process, the etching process time is longer due to the fact that the blank area except a waveguide is larger. The method comprises the following steps: obtaining a design pattern according to the waveguide of the semiconductor chip, and designing a mosaic pattern around the design pattern to obtain a mask layout; and manufacturing a mask of the chip according to the mask. According to the invention, only when the mask layout is drawn, the mosaic is generated around the original mask layout, so that the etching process time can be effectively shortened and the etching efficiency is improved under the condition of not increasing the production process flow and the production cost, thereby improving the overall production efficiency of the semiconductor chip.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a manufacturing method for improving etching efficiency.
Background
In the technical field of semiconductors, a mask is an indispensable tool, a large number of blank areas are arranged around an optical waveguide in some layouts, and when positive photoresist is used for photoetching, the blank areas except the waveguide need to be etched. Due to the large number of blank areas, the etching process time is long, and the overall production efficiency of the semiconductor chip is low.
Disclosure of Invention
Aiming at the technical problem that the etching process time is longer due to larger blank area except for the waveguide in the manufacturing process of the conventional semiconductor chip, the invention provides the manufacturing method for improving the etching efficiency, and the manufacturing method only needs to add a proper mosaic pattern when a chip mask layout is drawn and does not introduce redundant processes, so that the overall production efficiency can be improved.
In order to achieve the purpose, the technical scheme of the invention is realized as follows: a manufacturing method for improving etching efficiency comprises the following steps:
step S1: obtaining a design pattern according to the waveguide of the semiconductor chip, and designing a mosaic pattern around the design pattern to obtain a mask layout;
step S2: and manufacturing a mask of the chip according to the mask of the step S1.
The method for obtaining the mask layout in the step S1 includes:
s1.1, determining the shape of the required semiconductor chip;
s1.2, generating an auxiliary graph around the outline shape and the waveguide;
s1.3, generating a blank area by subtracting the generated auxiliary graph from a rectangle larger than the semiconductor chip, and filling a mosaic graph of the protection chip in the blank area;
and S1.4, removing the auxiliary graph generated in the step S1.2, and forming a required final graph which is a mask layout.
The mosaic pattern is a shape covering a blank area or a filled oblique cross line.
The inclination angle of the inclined cross line is 30-60 degrees.
The distance between the edge of the mosaic pattern and the waveguide of the semiconductor chip ranges from 50 to 150 mu m.
The edge of the mosaic pattern is at a distance of 50, 100 or 150 μm from the waveguide of the semiconductor chip.
The semiconductor chip is one of a PLC type optical splitter, an array waveguide grating, a tunable optical attenuator chip, a customized delay line or a mixer.
The substrate of the semiconductor chip is a monocrystalline silicon wafer or a quartz wafer.
The PLC type optical splitter or the array waveguide grating is manufactured by the following steps:
s3.1, cleaning the surface of the substrate;
s3.2, generating a silicon dioxide lower cladding on the surface of the substrate through thermal oxidation;
s3.3, growing a germanium-doped silica waveguide core layer on the silica lower cladding layer by using a plasma enhanced chemical vapor deposition method;
s3.4, growing a polycrystalline silicon hard mask layer by using a low-pressure chemical vapor deposition method, wherein the polycrystalline silicon hard mask layer covers the silicon dioxide lower cladding layer and the germanium-doped silicon dioxide waveguide core layer;
s3.5, coating photoresist on the polycrystalline silicon hard mask layer, and transferring the graph, namely the mask pattern, on the photoetching plate to the photoresist;
s3.6, etching the polycrystalline silicon hard mask layer in the step S3.5, and removing useless photoresist;
s3.7, performing core area etching by using an inductively coupled plasma etching method to obtain a required waveguide core layer;
s3.8, removing the residual polysilicon hard mask layer;
s3.9, growing an upper cladding by using a low-stress boron-phosphorus-silicon glass doping method;
and S3.10, annealing the upper cladding, and finishing the manufacture of the PLC optical splitter or the array waveguide grating after annealing.
The thickness range of the silica lower cladding in the step S3.2 is 10-15 μm; the thickness range of the germanium-doped silicon dioxide waveguide core layer in the step S3.3 is 4-8 mu m, and the width range is 4-8 mu m; the thickness of the polycrystalline silicon hard mask layer in the step S3.4 is 1 mu m; s3.7, the etching depth of the core area is 0.3-0.4 μm larger than the thickness of the core area; in the step S3.9, the thickness range of the upper cladding is 10-25 μm; the annealing temperature in the step S3.10 is 900-1100 ℃, and the annealing time is 3-5 hours.
Compared with the prior art, the invention has the beneficial effects that: only when the layout is drawn, the mosaic is generated around the original layout, and under the condition of not increasing the production process flow and the production cost, the etching process time can be effectively shortened, the etching efficiency is improved, and the overall production efficiency of the semiconductor chip is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a manufacturing process of a mask layout according to the present invention, in which a is a semiconductor chip, b is an additional auxiliary pattern, c is a mosaic pattern, and d is a mask layout (filled mosaic).
Fig. 2 is a chip structure of the present invention with added cross-waveguide mosaic patterns.
Fig. 3 is a temperature distribution diagram of a chip without a mosaic pattern.
FIG. 4 is a graph of the temperature distribution of the chip with the mosaic pattern generated by the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without inventive effort based on the embodiments of the present invention, are within the scope of the present invention.
Example 1
A manufacturing method for improving etching efficiency comprises the following steps:
step S1: obtaining a design pattern according to the waveguide of the semiconductor chip, and designing a mosaic pattern around the design pattern to obtain a mask layout; the mosaic pattern protects the chip and correspondingly improves the etching efficiency.
After the mosaic pattern is added, the etching appearance of the chip is better; under the condition of no mosaic pattern, the blank area outside the waveguide needs to be etched and removed, after the mosaic is added, the etched area can be greatly reduced, the corresponding etching time can be reduced, and the etching efficiency is further correspondingly improved.
And determining a required chip, and drawing a required chip layout, namely a design graph according to the required chip.
The method for obtaining the mask layout comprises the following steps:
step S1.1, the shape of the required semiconductor chip is determined.
As in fig. 1aThe outer shape is shown as a specific shape of a chip, the outer shape of a semiconductor is a rectangle, and a Y-shaped waveguide is arranged in the center of the semiconductor, the Y-branched waveguide is only representative, and all waveguides are not provided with the Y-shaped waveguide in the center.
S1.2, generating an auxiliary graph around the waveguide; as in fig. 1bAn auxiliary pattern is shown around the waveguide, the auxiliary pattern being intended to create a mosaic.
Step S1.3, using a rectangle larger than the semiconductor chipAnd generating a blank area by the generated auxiliary pattern, and filling the blank area with a mosaic pattern for forming a protection chip. As in fig. 1cThe mosaic pattern is shown as a shape that covers the blank area. The mosaic is the simplest mosaic, is simple in design, and is suitable for simple chips such as a splitter.
Preferably, as shown in fig. 2, the mosaic pattern is a filled oblique crossing line, a frame is arranged between the oblique crossing line and the outline shape or the waveguide, and the mosaic pattern is a closed shape with a plurality of filled blank regions, and for the arrayed waveguide grating chip, the shape can improve the crosstalk performance of the chip. The mosaic may be of other shapes. The inclination angle of the inclined cross lines is 30-60 degrees, preferably 45 degrees, and compared with full filling, the crosstalk performance of the chip is improved.
The distance between the edge of the mosaic pattern and the waveguide of the semiconductor chip ranges from 50 to 150 mu m. The size of the mosaic distance waveguide is adjusted according to different refractive index differences, and the larger the refractive index difference is, the mosaic distance can be properly reduced. Preferably, the mosaic distance waveguide is generally 150 μm, and can be 100 μm or 50 μm for conventional 0.45% -0.75% refractive index.
Step S1.4, removing the auxiliary graph generated in step S1.2, as shown in FIG. 1dThe final pattern required for formation is shown as the mask layout.
Step S2: and manufacturing a photoetching mask plate of the chip according to the mask plate of the step S1.
Example 2
A manufacturing method for improving etching efficiency is characterized in that a semiconductor chip is one of a PLC type optical splitter, an Arrayed Waveguide Grating (AWG), a tunable optical attenuator chip, a customized delay line or a mixer.
Further, the substrate of the semiconductor chip is a general monocrystalline silicon wafer or a quartz wafer.
Further, the PLC type optical splitter or the arrayed waveguide grating is manufactured by the following steps:
s3.1, cleaning the surface of the substrate;
s3.2, generating a silicon dioxide lower cladding on the surface of the substrate through thermal oxidation; the thickness range of the silicon dioxide lower cladding is 10-15 mu m;
s3.3, growing a germanium-doped silica waveguide core layer on the silica lower cladding layer by using a plasma enhanced chemical vapor deposition method; the thickness range of the germanium-doped silicon dioxide waveguide core layer is 4-8 mu m, and the width range of the germanium-doped silicon dioxide waveguide core layer is 4-8 mu m;
s3.4, growing a polycrystalline silicon hard mask layer by using a low-pressure chemical vapor deposition method, wherein the polycrystalline silicon hard mask layer covers the silicon dioxide lower cladding layer and the germanium-doped silicon dioxide waveguide core layer; the thickness of the polysilicon hard mask layer is 1 mu m;
s3.5, coating photoresist on the polycrystalline silicon hard mask layer, and transferring the graph, namely the mask pattern, on the photoetching plate to the photoresist; the photolithography mask is a mask plate, and patterns on the mask plate can be transferred onto the photoresist through photoetching.
S3.6, etching the polycrystalline silicon hard mask layer in the step S3.5, and removing useless photoresist;
the mosaic pattern is designed in the mask pattern, so that the etching step time is shortened.
S3.7, performing core area etching by using an inductively coupled plasma etching method to obtain a required waveguide core layer; the etching depth of the core area is 0.3-0.4 mu m larger than the thickness of the core area;
s3.8, removing the residual polysilicon hard mask layer;
s3.9, growing an upper cladding by using a low-stress boron-phosphorus-silicon glass doping method; the thickness range of the upper cladding is 10-25 μm;
and S3.10, annealing the upper cladding, and finishing the manufacture of the PLC optical splitter or the array waveguide grating after annealing. The annealing temperature range is 900-1100 ℃, and the annealing time range is 3-5 hours.
The experimental results are as follows:
first, the thermal analysis with or without mosaic will be described.
In order to further understand, the FEA finite element analysis method is adopted to simulate the thermal stress analysis of the output end of the PLC chip when a mask layout has no mosaic graph, the thickness of the quartz substrate is 625 microns, the thickness of the lower cladding layer is 15 microns, the thickness of the core region is 7 microns, the distance from the mosaic graph to the waveguide is 150 microns, the materials of the substrate, the lower cladding layer and the core layer are all quartz during simulation, the thermal conductivity is 1.38W/(m.K), and the temperature distribution graph during the process of packaging when the mosaic graph exists or not can be obtained. The temperature distribution graph of the PLC chip without the mosaic graph is shown in FIG. 3; and the temperature distribution simulating the situation with (d in fig. 1) mosaic patterns under the same conditions is shown in fig. 4, and it can be seen from fig. 4 that after the mosaic patterns are added to the mask of the PLC chip, the temperature transmission of the chip is more uniform, so that the thermal stress of the chip is smaller.
Second, the etching time when comparing the existence of mosaic
When a 7-inch wafer (with the diameter of 150 mm) is in the structure of a in fig. 1, assuming that the etching time of a hard mask is t1 and the etching time of a core area is t2 under certain etching speed and etching process conditions (different etching speeds are different for chips with different types and different refractive index differences), when the whole wafer structure is in d in fig. 1, the etching time of the hard mask is t1-30 s-t 1-50s and the etching time of the core area is t2-30 s-t 2-50s under the condition that the etching speed and the etching process conditions are the same, the process is monitored, namely, the time of 60-100 s can be saved in each etching process, and the production efficiency can be improved for batch repetitive flow sheets.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (10)
1. A manufacturing method for improving etching efficiency is characterized by comprising the following steps:
step S1: obtaining a design pattern according to the waveguide of the semiconductor chip, and designing a mosaic pattern around the design pattern to obtain a mask layout;
step S2: and manufacturing a mask of the chip according to the mask of the step S1.
2. The manufacturing method for improving etching efficiency according to claim 1, wherein the method for obtaining the mask layout in step S1 includes:
s1.1, determining the shape of a required semiconductor chip;
s1.2, generating an auxiliary graph around the waveguide;
s1.3, generating a blank area by subtracting the generated auxiliary graph from a rectangle larger than the semiconductor chip, and filling a mosaic graph of the protection chip in the blank area;
and S1.4, removing the auxiliary graph generated in the step S1.2, and forming a required final graph which is a mask layout.
3. The manufacturing method for improving etching efficiency according to claim 2, wherein the mosaic pattern is a shape covering a blank region or a filled oblique cross line.
4. The manufacturing method for improving etching efficiency according to claim 3, wherein the inclination angle of the inclined cross line is 30-60 °.
5. The manufacturing method for improving etching efficiency according to claim 1 or 4, wherein the distance from the edge of the mosaic pattern to the waveguide of the semiconductor chip is in a range of 50 to 150 μm.
6. The manufacturing method for improving etching efficiency according to claim 5, wherein the distance from the edge of the mosaic pattern to the waveguide of the semiconductor chip is 50 μm, 100 μm or 150 μm.
7. The manufacturing method for improving etching efficiency according to any one of claims 1 to 4 and 5, wherein the semiconductor chip is one of a PLC type optical splitter, an arrayed waveguide grating, a tunable optical attenuator chip, a customized delay line or a mixer.
8. The manufacturing method for improving etching efficiency according to claim 7, wherein the substrate of the semiconductor chip is a monocrystalline silicon wafer or a quartz wafer.
9. The manufacturing method for improving etching efficiency according to claim 7, wherein the manufacturing steps of the PLC type optical splitter or the arrayed waveguide grating are as follows:
s3.1, cleaning the surface of the substrate;
s3.2, generating a silicon dioxide lower cladding on the surface of the substrate through thermal oxidation;
s3.3, growing a germanium-doped silica waveguide core layer on the silica lower cladding layer by using a plasma enhanced chemical vapor deposition method;
s3.4, growing a polycrystalline silicon hard mask layer by using a low-pressure chemical vapor deposition method, wherein the polycrystalline silicon hard mask layer covers the silicon dioxide lower cladding layer and the germanium-doped silicon dioxide waveguide core layer;
s3.5, coating photoresist on the polycrystalline silicon hard mask layer, and transferring a mask pattern on the photoetching plate to the photoresist;
s3.6, etching the polycrystalline silicon hard mask layer in the step S3.5, and removing useless photoresist;
s3.7, performing core area etching by using an inductively coupled plasma etching method to obtain a required waveguide core layer;
s3.8, removing the residual polysilicon hard mask layer;
s3.9, growing an upper cladding by using a low-stress boron-phosphorus-silicon glass doping method;
and S3.10, annealing the upper cladding, and finishing the manufacture of the PLC optical splitter or the array waveguide grating after annealing.
10. The manufacturing method for improving etching efficiency according to claim 9, wherein the thickness of the silica lower cladding in the step S3.2 is in a range of 10 to 15 μm; the thickness range of the germanium-doped silicon dioxide waveguide core layer in the step S3.3 is 4-8 mu m, and the width range is 4-8 mu m; the thickness of the polycrystalline silicon hard mask layer in the step S3.4 is 1 mu m; s3.7, the etching depth of the core area is 0.3-0.4 μm larger than the thickness of the core area; in the step S3.9, the thickness range of the upper cladding is 10-25 μm; the annealing temperature in the step S3.10 is 900-1100 ℃, and the annealing time is 3-5 hours.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003043273A (en) * | 2001-07-27 | 2003-02-13 | Hitachi Cable Ltd | Photonic crystal waveguide and method for manufacturing the same |
| US20050207705A1 (en) * | 2002-06-04 | 2005-09-22 | Christian Laurent-Lund | Optical component and a method of fabricating an optical component |
| CN112782803A (en) * | 2021-01-08 | 2021-05-11 | 联合微电子中心有限责任公司 | Method for improving robustness of silicon-based optical waveguide process |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003043273A (en) * | 2001-07-27 | 2003-02-13 | Hitachi Cable Ltd | Photonic crystal waveguide and method for manufacturing the same |
| US20050207705A1 (en) * | 2002-06-04 | 2005-09-22 | Christian Laurent-Lund | Optical component and a method of fabricating an optical component |
| CN112782803A (en) * | 2021-01-08 | 2021-05-11 | 联合微电子中心有限责任公司 | Method for improving robustness of silicon-based optical waveguide process |
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