CN112769613A - FPGA (field programmable Gate array) online upgrading system and online upgrading method thereof - Google Patents
FPGA (field programmable Gate array) online upgrading system and online upgrading method thereof Download PDFInfo
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- CN112769613A CN112769613A CN202110001538.4A CN202110001538A CN112769613A CN 112769613 A CN112769613 A CN 112769613A CN 202110001538 A CN202110001538 A CN 202110001538A CN 112769613 A CN112769613 A CN 112769613A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
- H04L41/08—Configuration management of networks or network elements
- H04L41/0803—Configuration setting
- H04L41/0813—Configuration setting characterised by the conditions triggering a change of settings
- H04L41/082—Configuration setting characterised by the conditions triggering a change of settings the condition being updates or upgrades of network functionality
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- H04L67/02—Protocols based on web technology, e.g. hypertext transfer protocol [HTTP]
- H04L67/025—Protocols based on web technology, e.g. hypertext transfer protocol [HTTP] for remote control or remote monitoring of applications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L67/00—Network arrangements or protocols for supporting network services or applications
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Abstract
The invention discloses a system and a method for on-line upgrading of an FPGA, wherein the system comprises the following steps: the system comprises a main controller, a memory, a channel switching circuit and an FPGA device, wherein the controller is connected with a remote computer and is connected with the FPGA device, and the channel switching circuit is respectively connected with the controller, the memory and the FPGA device; the controller is used for acquiring the upgrading configuration file from the remote computer, and after the upgrading configuration file passes verification, the controller opens a first data path between the controller and the channel switching circuit and stores the upgrading configuration file in the memory; the controller is also used for closing the first data path and opening a second data path between the FPGA device and the memory, and the FPGA device acquires the upgrading configuration file from the memory through the second data path. In the invention, when upgrading, a JTAG download line is not needed, a product shell is not needed to be disassembled on site, and FPGA remote communication control can be considered.
Description
Technical Field
The invention belongs to the technical field of file upgrading, and particularly relates to an FPGA (field programmable gate array) online upgrading system and an FPGA online upgrading method.
Background
FPGA (field Programmable Gate array) is a field Programmable Gate array, and is a product of further development on the basis of Programmable devices such as PAL, GAL and the like. The internal part comprises three parts of a configurable Logic module CLB (configurable Logic Block), an input Output module IOB (input Output Block) and an internal connection (Interconnect). Because the FPGA has the characteristics of abundant wiring resources, repeatable programming, high integration level and low investment, the FPGA is widely applied to the field of digital circuit design, such as: communication, video, AI, accelerator card, etc.
In the design stage, developers compile and generate configuration files by using corresponding comprehensive tools, and after the configuration files are loaded into the FPGA, expected logic functions can be realized; in the stage of research, development and design, a common product can upgrade the configuration file of the FPGA through a JTAG download cable to realize the update of the configuration file. However, some products are chassis shells, the shells need to be disassembled for upgrading the FPGA, or the products are already used in a client machine room, the FPGA is difficult to be upgraded by using a downloading cable, the upgrading is inconvenient and low in efficiency, and therefore the upgrading of the FPGA needs to be realized by using a more convenient and intelligent scheme, the engineering maintenance of the products is facilitated, the labor and the maintenance cost are saved, and the intelligent level of the products is improved.
In view of this, overcoming the deficiencies of the prior art products is an urgent problem to be solved in the art.
Disclosure of Invention
The invention provides a system for on-line upgrading of FPGA and an on-line upgrading method thereof, aiming at adopting the scheme of a controller, a channel switching circuit, a memory and an FPGA device, firstly storing an upgrading configuration file in the memory through a channel switching switch, then triggering the FPGA device to take the upgrading configuration file from the memory for upgrading, needing no JTAG download line, needing no on-site disassembly of a product shell, saving time and maintenance cost, considering FPGA remote communication control and improving the intelligent level of the product.
To achieve the above object, according to an aspect of the present invention, there is provided a system for on-line upgrade of an FPGA, including: the system comprises a main controller, a memory, a channel switching circuit and an FPGA device, wherein the controller is connected with a remote computer, the controller is connected with the FPGA device, and the channel switching circuit is respectively connected with the controller, the memory and the FPGA device;
the controller is used for acquiring an upgrade configuration file from the remote computer, and after the upgrade configuration file passes verification, the controller opens a first data path between the controller and the channel switching circuit and stores the upgrade configuration file in the memory;
the controller is used for closing a first data path and opening a second data path between the FPGA device and the memory, and the FPGA device acquires the upgrade configuration file from the memory through the second data path.
Preferably, the channel switching circuit includes a first switch and a second switch, the first switch and the second switch each include a common port, a first port, and a second port, the common port of the first switch is connected to the controller, the first port of the first switch is connected to the communication interface of the FPGA device, and the second port of the first switch is connected to the second port of the second switch;
the public end of the second change-over switch is connected with the memory, and the first port of the second change-over switch is connected with the configuration interface of the FPGA device;
the controller is used for controlling the communication between the common end of the first selector switch and the second port and controlling the communication between the common end of the second selector switch and the second port so as to open the first data path;
the controller is used for controlling the communication between the common end of the second selector switch and the first port so as to open the second data path.
Preferably, the first switch and the second switch each include a selection terminal, the controller is connected to the selection terminal of the first switch and the selection terminal of the second switch, respectively, and the controller selectively opens the first data path and the second data path by controlling a level of the selection terminals.
Preferably, the controller is further configured to send a preset signal to the FPGA device, so that the FPGA device obtains the upgrade configuration file from the memory through the second data path.
Preferably, the FPGA device is configured to output a feedback signal indicating whether the upgrade is successful or failed to the controller;
if the FPGA device fails to be upgraded, the controller is used for sending a preset signal to the FPGA device so that the FPGA device can acquire the upgrade configuration file again;
if the FPGA device is upgraded successfully, the controller is used for closing the second data path and opening the third data path to connect the communication interfaces of the controller and the FPGA device so as to realize communication control of the FPGA device
Preferably, the controller is connected to the remote computer through an ethernet, and the channel switching circuit is connected to the controller, the memory, and the FPGA device through an SPI bus, an I2C bus, a PCIE bus, or a UART bus.
To achieve the above object, according to an aspect of the present invention, there is provided an online upgrade method of a system according to the present invention, including:
the controller acquires an upgrade configuration file from the remote computer, and after the upgrade configuration file passes verification, the controller opens a first data path between the controller and the channel switching circuit and stores the upgrade configuration file in the memory;
the controller closes a first data path and opens a second data path between the FPGA device and the memory, and the FPGA device acquires the upgrade configuration file from the memory through the second data path.
Preferably, the controller closes a first data path and opens a second data path between the FPGA device and the memory, and the FPGA device acquires the upgrade configuration file from the memory through the second data path includes:
the controller closes a first data path and opens a second data path between the FPGA device and the memory;
and the controller sends a preset signal to the FPGA device, and the FPGA device acquires the upgrade configuration file from the memory through the second data path.
Preferably, the online upgrade method further includes:
after the FPGA device reads the upgrade configuration file and completes initialization configuration, a feedback signal of upgrade success or upgrade failure is output to the controller;
if the FPGA device fails to be upgraded, the controller sends a preset signal to the FPGA device so that the FPGA device can acquire the upgrade configuration file again;
and if the FPGA device is successfully upgraded, the controller closes the second data path and opens the third data path to connect the communication interfaces of the controller and the FPGA device, so as to realize communication control of the FPGA device.
Preferably, the channel switching circuit includes a first switch and a second switch, the first switch and the second switch each include a common port, a first port, and a second port, the common port of the first switch is connected to the controller, the first port of the first switch is connected to the communication interface of the FPGA device, and the second port of the first switch is connected to the second port of the second switch; the public end of the second change-over switch is connected with the memory, and the first port of the second change-over switch is connected with the configuration interface of the FPGA device;
the online upgrading method comprises the following steps:
the controller controls the common end of the first change-over switch to be communicated with the second port, and controls the common end of the second change-over switch to be communicated with the second port so as to open the first data path;
the controller controls the common end of the second selector switch to be communicated with the first port so as to open the second data path.
Generally, compared with the prior art, the technical scheme of the invention has the following beneficial effects: the invention provides a system and a method for on-line upgrading of an FPGA, comprising the following steps: the system comprises a main controller, a memory, a channel switching circuit and an FPGA device, wherein the controller is connected with a remote computer, the controller is connected with the FPGA device, and the channel switching circuit is respectively connected with the controller, the memory and the FPGA device; the controller is used for acquiring an upgrade configuration file from the remote computer, and after the upgrade configuration file passes verification, the controller opens a first data path between the controller and the channel switching circuit and stores the upgrade configuration file in the memory; the controller is used for closing a first data path and opening a second data path between the FPGA device and the memory, and the FPGA device acquires the upgrade configuration file from the memory through the second data path.
According to the invention, by adopting the scheme of the controller, the channel switching circuit, the memory and the FPGA device, the upgrade configuration file is stored in the memory through the channel switching switch, then the FPGA device is triggered to take the upgrade configuration file from the memory for upgrading, a JTAG download line is not needed, the product shell is not required to be disassembled on site, the time and the maintenance cost are saved, the FPGA remote communication control can be considered, and the intelligent level of the product is improved.
Drawings
Fig. 1 is a schematic structural diagram of a system for on-line upgrading an FPGA according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of another FPGA online upgrade system according to an embodiment of the present invention;
FIG. 3 is a flowchart illustrating an online upgrade method according to an embodiment of the present invention;
fig. 4 is a schematic flow chart of another online upgrade method according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
In the description of the present invention, the terms "inner", "outer", "longitudinal", "lateral", "upper", "lower", "top", "bottom", and the like indicate orientations or positional relationships based on those shown in the drawings, and are for convenience only to describe the present invention without requiring the present invention to be necessarily constructed and operated in a specific orientation, and thus should not be construed as limiting the present invention.
In addition, the technical features involved in the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
Example 1:
referring to fig. 1, the present embodiment provides a system for on-line upgrading an FPGA, where the system includes: the system comprises a main controller, a storage, a channel switching circuit and an FPGA device, wherein the controller is connected with a remote computer, the controller is connected with the FPGA device, and the channel switching circuit is respectively connected with the controller, the storage and the FPGA device. The memory can be a FLASH chip. The controller is connected to the remote computer through an ethernet, and the channel switching Circuit is connected to the controller, the memory, and the FPGA device through an SPI (Serial Peripheral Interface, abbreviated as SPI) bus, an I2C (Inter-Integrated Circuit, abbreviated as I2C) bus, a PCIE (Peripheral Component Interface Express, abbreviated as PCIE) bus, or a UART bus.
In a specific embodiment, the communication bus adopts an SPI bus, which ensures that the SPI bus interface voltage between the controller, the channel switching circuit, the FPGA device, and the memory is all 1.8V. Wherein, combine fig. 2, because the SPI bus has striden 2 change over switch, reserve 4.7K pull-up resistance respectively on the MOSI of SPI bus, MOSI, CLK, CS # signal, can promote the rising edge of signal, improve signal quality.
In practical use, the controller is configured to obtain an upgrade configuration file from the remote computer, and after the upgrade configuration file passes verification, the controller opens a first data path between the controller and the channel switching circuit, and stores the upgrade configuration file in the memory; after the upgrade configuration file is stored in the memory, the controller is configured to close a first data path and open a second data path between the FPGA device and the memory, and the FPGA device obtains the upgrade configuration file from the memory through the second data path.
In a specific application scenario, referring to fig. 2, the channel switching circuit includes a first switch and a second switch, where the first switch and the second switch both include a common terminal (COM), a first port (NO), and a second port (NC), the common terminal of the first switch is connected to the controller, the first port of the first switch is connected to the communication interface of the FPGA device, and the second port of the first switch is connected to the second port of the second switch; and the public end of the second change-over switch is connected with the memory, and the first port of the second change-over switch is connected with the configuration interface of the FPGA device. The first switch and the second switch are bus switches and can be controlled through an SPI bus, an I2C bus or a UART bus.
Further, the first switch and the second switch each include a selection terminal (SEL), the controller is connected to the selection terminal of the first switch and the selection terminal of the second switch, and the controller selectively opens the first data path and the second data path by controlling a level of the selection terminals.
In practical use, the controller is configured to control the common terminal of the first switch to communicate with the second port, and control the common terminal of the second switch to communicate with the second port, so as to open the first data path; the controller is used for controlling the communication between the common end of the second selector switch and the first port so as to open the second data path. Specifically, the controller selectively switches the common terminal to communicate with the first port or the second port by changing the level of the selection terminal input to the first switch and the second switch.
In this embodiment, the controller is connected to a communication interface of the FPGA device, and the first port of the second switch is connected to a configuration port of the FPGA device. The communication interface is used for communicating with the controller, the controller is a master device, and the FPGA device is a slave device; the configuration interface is used for actively reading the upgrade configuration file from the memory to complete the configuration upgrade of the FPGA, and the FPGA device adopts an AS loading mode.
In this embodiment, the controller is further configured to send a preset signal (e.g., an n _ CONFIG signal shown in fig. 2) to the FPGA device, so that the FPGA device obtains the upgrade configuration file from the memory through the second data path. Specifically, the controller pulls the n _ CONFIG signal low, the FPGA device is reset, and the FPGA device is released after a set time interval (i.e., the n _ CONFIG signal is pulled high), and the FPGA device automatically reacquires the upgrade configuration file.
In this embodiment, the FPGA device is in an AS mode (AS mode), where the AS mode refers to that the FPGA chip is used AS a controller each time the FPGA chip is powered on. The FPGA chip guides the configuration operation process, and controls the external memory and the FPGA device to be in an active state and the memory to be in a subordinate state during the initialization process. Configuration DATA for the memory is fed into the FPGA through DATA0 pins, and configuration DATA0 is latched on the rising edge of DCLK, transferring 1 bit of DATA for 1 clock cycle.
In this embodiment, the FPGA device outputs a feedback signal (such as the CONF _ DONE signal shown in fig. 2) indicating whether the upgrade is successful or failed to the controller; if the FPGA device fails to be upgraded, the controller is used for sending a preset signal to the FPGA device so that the FPGA device can acquire the upgrade configuration file again; and if the FPGA device is upgraded successfully, the controller is used for closing the second data path and opening the third data path so as to connect the communication interfaces of the controller and the FPGA device and realize the communication control of the FPGA device. The controller controls the common end of the first selector switch to be communicated with the first port so as to open the third data path.
The connection mode of the selector switch is determined by the level of the selection terminal SEL, for example, when the selection terminal SEL is at a low level, the common terminal COM is communicated with the second port NC; when the selection terminal SEL is in a high level: and the common end COM is communicated with the first two ports NC. As shown in table 1 below, the communication mode of the first switch and the second switch is shown, and the corresponding relationship between the first switch and the second switch and the data path is shown.
| Data path | First switch | Second change-over switch |
| A first data path: controller-memory | COM-NC | COM-NC |
| A second data path: configuration interface-memory for FPGA devices | / | COM-NO |
| The third data path: communication interface of controller-FPGA device | COM-NO | / |
TABLE 1 communication mode of first and second transfer switches
In this embodiment, the scheme of the controller + the channel switching circuit + the memory + the FPGA device is adopted, the upgrade configuration file is stored in the memory through the channel switching switch, then the FPGA device is triggered to take the upgrade configuration file from the memory for upgrading, a JTAG download line is not needed, the product shell does not need to be disassembled on site, time and maintenance cost are saved, the FPGA remote communication control can be considered, and the intelligent level of the product is improved.
In addition, the FPGA device actively reads the upgrading configuration file from the memory to complete configuration by adopting an AS loading mode, after the FPGA is upgraded, the controller switch realizes bus communication between the controller and the FPGA device, the logic of the FPGA can be controlled, and the upgrading configuration interface and the communication interface of the FPGA are independent respectively. In the embodiment, the bus control change-over switch is adopted, and the controller can realize the online upgrade and communication control of the FPGA by using 1 management bus, so that the bus resource of the CPU is saved, and the circuit is simple, stable and reliable.
Example 2:
based on the system of embodiment 1, this embodiment provides an online upgrade method, which is used to upgrade an FPGA device, and with reference to fig. 3, the online upgrade method includes the following steps:
step 101: the controller obtains an upgrade configuration file from the remote computer, and after the upgrade configuration file passes verification, the controller opens a first data path between the controller and the channel switching circuit and stores the upgrade configuration file in the memory.
Step 102: the controller closes a first data path and opens a second data path between the FPGA device and the memory, and the FPGA device acquires the upgrade configuration file from the memory through the second data path.
Specifically, after the upgrade configuration file is stored in the memory, the controller closes a first data path and opens a second data path between the FPGA device and the memory; and the controller sends a preset signal to the FPGA device, and the FPGA device acquires the upgrade configuration file from the memory through the second data path. Referring to fig. 2, the controller pulls the n _ CONFIG signal low, the FPGA device is reset, and the FPGA device is released (i.e., the n _ CONFIG signal is pulled high) after a set time interval, so that the FPGA can automatically obtain the configuration file from the memory.
Further, the online upgrade method further includes: after the FPGA device reads the upgrade configuration file and completes initialization configuration, a feedback signal of upgrade success or upgrade failure is output to the controller, and with reference to fig. 2, after the FPGA device reads the upgrade configuration file and completes initialization configuration, a CONF _ DONE signal is output to be a high level, and the controller can judge whether the FPGA device is upgraded successfully or not through the CONF _ DONE signal output by the FPGA device, and can also add other identifiers to judge. If the FPGA device fails to be upgraded, the controller is used for sending a preset signal to the FPGA device so that the FPGA device can obtain the upgrade configuration file again; and if the FPGA device is successfully upgraded, the controller closes the second data path and opens the third data path to connect the communication interfaces of the controller and the FPGA device, so as to realize communication control of the FPGA device.
In an actual application scenario, the channel switching circuit includes a first switch and a second switch, both the first switch and the second switch include a common end, a first port and a second port, the common end of the first switch is connected to the controller, the first port of the first switch is connected to the communication interface of the FPGA device, and the second port of the first switch is connected to the second port of the second switch; and the public end of the second change-over switch is connected with the memory, and the first port of the second change-over switch is connected with the configuration interface of the FPGA device. The controller controls the common end of the first change-over switch to be communicated with the second port, and controls the common end of the second change-over switch to be communicated with the second port so as to open the first data path; the controller controls the common end of the second selector switch to be communicated with the first port so as to open the second data path, and the controller controls the common end of the first selector switch to be communicated with the first port so as to open the third data path.
In an actual application scene, each time the system is powered on, the controller controls the common end COM of the first change-over switch to be communicated with the first port NO, the controller is communicated with the communication interface of the FPGA device, and at the moment, the controller can control the FPGA device; meanwhile, the controller controls the second change-over switch, the common end COM of the second change-over switch is communicated with the first port NO, the n _ CONFIG signal is pulled down and released after the interval is set for a long time, the FPGA device can automatically read the configuration file of the memory to complete initialization configuration in the AS mode, and the CONF _ DONE signal is changed from low level to high level after the FPGA device completes initialization. That is, sequential initialization configuration is performed each time the system is powered on.
The following describes an implementation process of the online upgrade method according to this embodiment with reference to fig. 4.
S1: the controller receives an upgrade configuration file through the Ethernet;
the controller receives the FPGA upgrading configuration file through the Ethernet and stores the FPGA upgrading configuration file in the memory;
s2: the controller controls the first change-over switch and the second change-over switch through the SPI bus, connects a data path between the controller and the memory, and writes the upgrade configuration file into the memory;
and the controller controls the communication between the public end of the first change-over switch and the second port, and controls the communication between the public end of the second change-over switch and the second port so as to open the first data path and write the upgrade configuration file into a memory. At the moment, the SPI bus of the controller is communicated with the SPI bus of the memory, and the communication interface of the controller and the FPGA device is disconnected at the moment;
s3: the controller checks whether the upgrade configuration file written in the memory is correct or not; if not, returning to the step of executing S2, and if so, continuing to execute S4;
s4: the controller controls the second change-over switch to be connected with a data path between the configuration interface of the FPGA device and the memory through the SPI bus;
the controller controls the common end of the second selector switch to be communicated with the first port so as to open the second data path;
s5: the controller pulls the n _ CONFIG signal low, and releases the signal after setting time interval;
the controller pulls the n _ CONFIG signal low and releases the signal after setting time interval, the FPGA device is in an AS mode, and the FPGA device can automatically read an upgrade configuration file from the memory and complete upgrade configuration;
s6: the FPGA device automatically reads the upgrade configuration file from the memory and completes upgrade configuration;
s7: the controller judges whether the FPGA device is successfully upgraded according to the CONF _ DONE signal; if not, the process returns to step S5, and if so, the process continues to step S8.
After the FPGA device reads the upgrade configuration file and completes initialization configuration, the CONF _ DONE signal is output to be high level, the controller can judge whether upgrade is successful or not through the CONF _ DONE signal output by the FPGA, and other marks can be added to judge.
S8: the controller controls the second change-over switch to be connected with a data path between the controller and the FPGA device through the SPI bus.
After the FPGA device is upgraded successfully, the controller controls the public end of the first change-over switch to be communicated with the first port so as to open the third data path, so that the communication interface of the controller and the FPGA device is communicated, and the communication control of the FPGA device can be realized through the controller.
In addition, each time the system is powered on, the controller controls the COM of the first change-over switch to be communicated with the NO, the controller is communicated with a communication interface of the FPGA device, and at the moment, the controller can control the FPGA device; meanwhile, the controller controls the second change-over switch to communicate COM and NO of the second change-over switch, then the n _ CONFIG signal is pulled down and released after the interval is set for a long time, the FPGA device can automatically read the configuration file of the memory to complete initialization configuration in the AS mode, and after the FPGA device completes initialization, the CONF _ DONE signal is changed from low level to high level.
In the embodiment, the FPGA is upgraded on line through the Ethernet and the controller, compared with the traditional upgrading mode of a JTAG download line, the upgrading can be easily realized only through network management such as a web/upper computer and the like, the remote online upgrading can be realized, the later maintenance cost of the product is greatly saved, and the maintainability and the intelligent level of the product are improved. The design of the switching circuit ensures that the controller can complete the file updating of the memory and the communication control of the FPGA device by only one management bus, saves the resources of the management bus and has great value for products lacking in the control bus resources.
It will be understood by those skilled in the art that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the invention, and that any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (10)
1. A system for FPGA online upgrade is characterized by comprising: the system comprises a main controller, a memory, a channel switching circuit and an FPGA device, wherein the controller is connected with a remote computer, the controller is connected with the FPGA device, and the channel switching circuit is respectively connected with the controller, the memory and the FPGA device;
the controller is used for acquiring an upgrade configuration file from the remote computer, and after the upgrade configuration file passes verification, the controller opens a first data path between the controller and the channel switching circuit and stores the upgrade configuration file in the memory;
the controller is further configured to close a first data path and open a second data path between the FPGA device and the memory, and the FPGA device obtains the upgrade configuration file from the memory through the second data path.
2. The system of claim 1, wherein the channel switching circuit comprises a first switch and a second switch, each of the first switch and the second switch comprises a common port, a first port, and a second port, the common port of the first switch is connected to the controller, the first port of the first switch is connected to the communication interface of the FPGA device, and the second port of the first switch is connected to the second port of the second switch;
the public end of the second change-over switch is connected with the memory, and the first port of the second change-over switch is connected with the configuration interface of the FPGA device;
the controller is used for controlling the communication between the common end of the first selector switch and the second port and controlling the communication between the common end of the second selector switch and the second port so as to open the first data path;
the controller is used for controlling the communication between the common end of the second selector switch and the first port so as to open the second data path.
3. The system of claim 2, wherein the first switch and the second switch each include a selection terminal, the controller is connected to the selection terminal of the first switch and the selection terminal of the second switch, respectively, and the controller selectively opens the first data path and the second data path by controlling a level of the selection terminals.
4. The system of claim 1, wherein the controller is further configured to send a preset signal to the FPGA device, and the FPGA device obtains the upgrade configuration file from the memory via the second data path.
5. The system of claim 1, wherein the FPGA device is configured to output a feedback signal of upgrade success or upgrade failure to the controller;
if the FPGA device fails to be upgraded, the controller is used for sending a preset signal to the FPGA device so that the FPGA device can acquire the upgrade configuration file again;
and if the FPGA device is upgraded successfully, the controller is used for closing the second data path and opening the third data path so as to connect the communication interfaces of the controller and the FPGA device and realize the communication control of the FPGA device.
6. The system of claim 1, wherein the controller is connected to the remote computer via an ethernet, and the channel switching circuit is connected to the controller, the memory, and the FPGA device via an SPI bus, an I2C bus, a PCIE bus, or a UART bus.
7. An online upgrade method for a system according to any one of claims 1 to 6, comprising:
the controller acquires an upgrade configuration file from the remote computer, and after the upgrade configuration file passes verification, the controller opens a first data path between the controller and the channel switching circuit and stores the upgrade configuration file in the memory;
the controller closes a first data path and opens a second data path between the FPGA device and the memory, and the FPGA device acquires the upgrade configuration file from the memory through the second data path.
8. The online upgrade method according to claim 7, wherein the controller closes a first data path and opens a second data path between the FPGA device and the memory, and the FPGA device obtains the upgrade configuration file from the memory through the second data path includes:
the controller closes a first data path and opens a second data path between the FPGA device and the memory;
and the controller sends a preset signal to the FPGA device, and the FPGA device acquires the upgrade configuration file from the memory through the second data path.
9. The online upgrade method according to claim 7, further comprising:
after the FPGA device reads the upgrade configuration file and completes initialization configuration, a feedback signal of upgrade success or upgrade failure is output to the controller;
if the FPGA device fails to be upgraded, the controller sends a preset signal to the FPGA device so that the FPGA device can acquire the upgrade configuration file again;
and if the FPGA device is successfully upgraded, the controller closes the second data path and opens the third data path to connect the communication interfaces of the controller and the FPGA device, so as to realize communication control of the FPGA device.
10. The online upgrade method according to claim 7, wherein the channel switching circuit includes a first switch and a second switch, the first switch and the second switch each include a common terminal, a first port, and a second port, the common terminal of the first switch is connected to the controller, the first port of the first switch is connected to the communication interface of the FPGA device, and the second port of the first switch is connected to the second port of the second switch; the public end of the second change-over switch is connected with the memory, and the first port of the second change-over switch is connected with the configuration interface of the FPGA device;
the online upgrading method comprises the following steps:
the controller controls the common end of the first change-over switch to be communicated with the second port, and controls the common end of the second change-over switch to be communicated with the second port so as to open the first data path;
the controller controls the common end of the second selector switch to be communicated with the first port so as to open the second data path.
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