CN114579155A - Online updating method and system for multi-FPGA system and computer equipment - Google Patents
Online updating method and system for multi-FPGA system and computer equipment Download PDFInfo
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- CN114579155A CN114579155A CN202210081927.7A CN202210081927A CN114579155A CN 114579155 A CN114579155 A CN 114579155A CN 202210081927 A CN202210081927 A CN 202210081927A CN 114579155 A CN114579155 A CN 114579155A
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- G06—COMPUTING; CALCULATING OR COUNTING
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- G06F8/00—Arrangements for software engineering
- G06F8/60—Software deployment
- G06F8/65—Updates
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/60—Software deployment
- G06F8/61—Installation
- G06F8/63—Image based installation; Cloning; Build to order
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention discloses a multi-FPGA system online updating method, a multi-FPGA system online updating system and computer equipment, wherein the multi-FPGA system comprises at least 2 FPGAs, a channel selection module and a storage module, a second FPGA is connected with the corresponding storage module through the corresponding channel selection module, a first FPGA is connected with the corresponding storage module through the channel selection module corresponding to the second FPGA, and the method comprises the following steps: the upper computer designates a first FPGA and a second FPGA; the first FPGA acquires update data from an upper computer, switches a channel selection module corresponding to the second FPGA to a first channel, and then sends the update data to a corresponding storage module through the first channel; the first FPGA sends an instruction to the second FPGA, the channel selection module corresponding to the second FPGA is switched to the second channel, and the second FPGA acquires the updating data from the storage module through the second channel and updates the updating data. The invention realizes more efficient and flexible online updating.
Description
Technical Field
The invention relates to a firmware updating method, in particular to an online updating method and system for a multi-FPGA system and computer equipment.
Background
With the rapid development of technology and market demand, more and more devices tend to have multiple functionalities and complexities, which means that many devices or systems include multiple FPGAs, and in addition to the limitation of application environment, how to rapidly perform online upgrade on the devices or systems becomes a critical issue. The current online updating mode mainly comprises:
1. and the download cable is used for connecting the JTAG port to carry out the update download of the program. However, in general, the JTAG download port is usually disposed on a board, and if the device needs to perform online update and download, the case or the housing needs to be disassembled to download the program using the JTAG download port. Therefore, the solution has too many limitations, for example, in some applications where the environment is harsh or where dismantling is not allowed, the solution cannot be used.
2. And the MCU is used as a controller to update the program of the FLASH of the FPGA. The scheme can solve the limitation of an application environment, only the upper computer is required to be communicated with the MCU through the Ethernet or a serial port, the upper computer issues a program updating package to the MCU, the MCU erases and writes a FLASH of the FPGA after verification, a required updating program is written into the FLASH, the FPGA is controlled by the GPIO to be powered off to be actively loaded again after updating is completed, and online upgrading is completed. However, the scheme also has some disadvantages, namely the updating speed is low, in a system with a plurality of FPGAs, the program updating package is very large, and the MCU is a serial processing system, which means that the MCU needs one FPGA to erase and write the FLASH; another disadvantage is that if the MCU is used, an additional MCU chip and FLASH related functions are required, and the software complexity is increased.
The patent CN105808290A discloses a remote dynamic update system and method for a multi-FPGA whole system, where a first FPGA receives a program update package from an upper computer, temporarily stores the program update package in an external SDRAM, after verification, writes data into an external FLASH, the FLASH stores all the programs of the FPGAs, and then the first FPGA loads at least one configuration file of a second FPGA from the FLASH to configure the second FPGAs.
Disclosure of Invention
The technical problems to be solved by the invention are as follows: aiming at the problems in the prior art, the multi-FPGA system online updating method, the multi-FPGA system online updating system and the computer equipment are provided, the defects of low updating speed, long loading time and the like of the existing scheme are overcome, the design difficulty is reduced, the operability of the system is improved, and more efficient and flexible online updating is realized.
In order to solve the technical problems, the invention adopts the technical scheme that:
the multi-FPGA system online updating method comprises the following steps of:
the method comprises the steps that a first FPGA acquires update data from an upper computer, a channel selection module corresponding to a second FPGA is switched to a first channel, and the first FPGA sends the update data to a storage module corresponding to the second FPGA through the first channel;
the first FPGA sends an instruction to the second FPGA, a channel selection module corresponding to the second FPGA is switched to a second channel, and the second FPGA acquires update data from a corresponding storage module through the corresponding second channel and updates the update data.
Further, after the channel selection module corresponding to the second FPGA is switched to the first channel, the method further includes a step of data verification, which specifically includes:
the first FPGA acquires a current frame of the updated data, checks the data of the current frame, sends the data of the current frame to a storage module corresponding to the second FPGA through the first channel if the checking is successful, discards the data of the current frame if the checking is unsuccessful, requests to resend the data of the current frame, and waits for the data of the current frame.
Or after the channel selection module corresponding to the second FPGA is switched to the first channel, the data verification step specifically includes:
the method comprises the steps that a first FPGA acquires a current frame of updated data, checks the data of the current frame, caches the data of the current frame into a DDR of the first FPGA if the checking is successful, discards the data of the current frame if the checking is unsuccessful, requests to resend the data of the current frame, and waits for the data of the current frame;
after all frames of the updated data are checked, the first FPGA sends the cache data in the DDR to the storage module corresponding to the second FPGA through the first channel.
Further, before the first FPGA sends the instruction to the second FPGA, the first FPGA reads the update data in the storage module corresponding to the second FPGA through the first channel, checks the read update data, if the update data which is not successfully checked exists, the corresponding storage module is used as a target storage module, requests to resend the update data, and after waiting and acquiring the update data, replaces the update data in the target storage module with the newly acquired update data through the first channel.
Further, the specific step of verifying the read update data includes: the first FPGA compares the read updating data with the updating data cached in the DDR of the first FPGA, if the read updating data is consistent with the updating data cached in the DDR of the first FPGA, the read updating data is successfully verified, and if the read updating data is inconsistent with the updating data cached in the DDR of the first FPGA, the read updating data is not successfully verified.
Further, the first FPGA is connected to a second FPGA through a GPIO interface, and the step of sending the instruction to the second FPGA by the first FPGA specifically includes:
the first FPGA controls the second FPGA to be in a reset state through a GPIO interface;
and after the channel selection module corresponding to the second FPGA is switched to a second channel, the first FPGA controls the second FPGA to reinitialize and reload through the GPIO interface.
Further, the method further comprises a step of updating the first FPGA, and specifically comprises: and writing the updating data into the storage unit corresponding to the first FPGA, switching the channel selection module corresponding to the first FPGA to the second channel, reading the updating data in the corresponding storage unit through the corresponding second channel by the first FPGA, and updating by using a MultiBoot mode.
The invention also provides a multi-FPGA system, which comprises a first FPGA, a second FPGA, a channel selection module and a storage module, wherein the first FPGA and the second FPGA are respectively connected with the corresponding storage module through the corresponding channel selection module, the first FPGA is also connected with the corresponding storage module through the channel selection module corresponding to the second FPGA, and the multi-FPGA system is also connected with an upper computer, wherein:
the first FPGA is used for acquiring update data from an external upper computer, switching a channel selection module corresponding to a second FPGA to a first channel, and then sending the update data to a storage module corresponding to the second FPGA through the first channel;
the first FPGA also sends an instruction to the second FPGA, and switches a channel selection module corresponding to the second FPGA to a second channel;
and the second FPGA is used for acquiring the updating data from the corresponding storage module through the corresponding second channel and updating.
Further, the first FPGA updates the data by using a MultiBoot method, and writes the updated data sent by the upper computer into a storage unit corresponding to the first FPGA, where the updated data is a MultiBoot Image. And the storage module also stores a program burnt when leaving the factory, the program is called Golden Image, if the FPGA fails to load the program after updating due to various problems in the updating process, the FPGA reloads the Golden Image, and the updating process is executed again.
The invention also provides computer equipment which comprises a multi-FPGA system and an upper computer, wherein the multi-FPGA system comprises at least 2 FPGAs, a channel selection module and a storage module, second FPGAs in the FPGAs are respectively connected with the corresponding storage modules through the corresponding channel selection modules, a first FPGA in the FPGAs is also connected with the corresponding storage modules of the second FPGAs through the channel selection modules corresponding to the second FPGAs, the multi-FPGA system is also connected with the upper computer, and the FPGAs are programmed or configured to execute any one of the multi-FPGA system online updating methods.
Compared with the prior art, the invention has the following advantages:
when the second FPGA is updated, the second FPGA can load update data to update according to the instruction by only sending the instruction to the second FPGA by the first FPGA and switching the channel selection module corresponding to the second FPGA to a correct channel, so that the execution efficiency of the loading process is greatly improved, and the time required by loading is effectively reduced.
According to the multi-FPGA system, the channel selection module is further arranged between the second FPGA and the corresponding storage module, so that the storage module has a data selection channel between the first FPGA and the corresponding second FPGA, and the storage module can realize writing of the first FPGA update data and reading of the second FPGA update data only by switching the data selection channel through the first FPGA, so that data transmission conflict is avoided.
In the scheme, data are transmitted between the FPGA and the storage module, and the first FPGA has a verification and request mechanism for updating the data, so that the next program updating can be performed after the failure of loading the program of the updated FPGA due to the data error written into the storage module caused by factors such as power failure or data transmission error. The problem that the FPGA needs to use JTAG to burn and write programs after writing error data is solved.
Drawings
Fig. 1 is a block diagram of a multi-FPGA system according to a first embodiment of the present invention.
Fig. 2 is a schematic step diagram of a method according to a first embodiment of the present invention.
Detailed Description
The invention is further described below with reference to the drawings and specific preferred embodiments of the description, without thereby limiting the scope of protection of the invention.
Example one
In order to solve the problems in the prior art, the present embodiment provides a multi-FPGA system, as shown in fig. 1, the multi-FPGA system in the present embodiment includes at least 2 FPGAs, and further includes a channel selection module and a storage module, second FPGAs in the FPGAs are connected to the corresponding storage modules through the corresponding channel selection modules, a first FPGA in the FPGAs is further connected to the storage module corresponding to each second FPGA through the channel selection module corresponding to each second FPGA, the first FPGA is connected to a reload related pin of the second FPGA through a GPIO, and the multi-FPGA system is further connected to an external upper computer.
In the multi-FPGA system of this embodiment, first FPGA does not have a channel selection module, only has a corresponding storage module, second FPGA all is provided with corresponding channel selection module and storage module, the channel selection module adopts a signal separator, the storage module adopts QSPI FLASH, QSPI FLASH to connect with first FPGA through the first channel of signal separator, and connect with corresponding second FPGA through the second channel of signal separator, under the condition of normal work, the second channel is opened by default to the signal separator of channel selection module, namely the channel between QSPI FLASH and the corresponding second FPGA, when electrifying this moment, each second FPGA will carry out active loading according to self active loading mode configuration.
In this embodiment, the first channel of the demultiplexer is used for writing data into the storage module corresponding to the demultiplexer by the first FPGA when updating is performed, so that data writing and data reading of the storage module can be performed respectively, thereby avoiding collision of data transmission.
In this embodiment, each FPGA is further provided with a DDR unit for caching data, so that data verification is facilitated, or the efficiency of data processing is improved.
When system updating is needed, the present embodiment provides an online updating method for a multi-FPGA system based on the multi-FPGA system, as shown in fig. 2, including the following steps:
the upper computer appoints a first FPGA and a second FPGA from each FPGA, and respectively configures storage modules corresponding to the first FPGA and the second FPGA and also configures a channel selection module corresponding to the second FPGA;
the method comprises the steps that a first FPGA acquires update data from an upper computer, a channel selection module corresponding to a second FPGA is switched to a first channel, and the first FPGA sends the update data to a storage module corresponding to the second FPGA through the first channel;
the first FPGA sends an instruction to the second FPGA, the channel selection module corresponding to the second FPGA is switched to the second channel, and the second FPGA acquires the updating data from the corresponding storage module through the corresponding second channel and updates the updating data.
Through the steps, when the second FPGA is updated, the second FPGA can load updated data to be updated according to the instruction by only needing the first FPGA to send the instruction to the second FPGA and switching the channel selection module corresponding to the second FPGA to a correct channel, so that the execution efficiency of the loading process is greatly improved, and the time required by loading is effectively reduced. Meanwhile, writing each storage module through one FPGA in the multi-FPGA system, wherein different data channels exist among the storage modules, the first FPGA and the second FPGA, when data are written into the storage modules, the first channel is opened, and after the data are written, the second channel is opened again to update the second FPGA. The method has the advantage that the steps can be repeated to update the program next time after the second FPGA fails to load due to data errors of the writing storage module caused by power failure or data transmission errors and the like. The problem that the FPGA needs to use JTAG to burn and write programs after writing error data is solved.
In the above steps, the upper computer specifies the control module and the updated FPGA in the multi-FPGA system of this embodiment, and the control module updates the updated FPGA after receiving the update data, it should be noted that the specification is for unspecified objects, and the number of the objects is also not constant, that is, a plurality of control modules and updated FPGAs may be specified, or one control module and a plurality of updated FPGAs may be specified, generally speaking, any one FPGA is specified as the control module, and the rest FPGAs are specified as the updated FPGA. The upper computer takes the first FPGA as a control module (in this embodiment, the first FPGA refers to the control module, and the second FPGA refers to the updated FPGA), and issues update data, and various ways are available, including but not limited to SerDes, serial ports, ethernet, and the like.
Next, after the first FPGA switches the channel selection module corresponding to the second FPGA to the first channel, data verification can be performed on the updated data, if the verification is unsuccessful, the upper computer is required to resend the data and verify the data again, if the verification is successful, the data is sent to the storage unit corresponding to the second FPGA through the first channel, and the data verification process comprises the following steps:
the first FPGA acquires a current frame of the updated data, checks the data of the current frame, sends the data of the current frame to a storage module corresponding to the second FPGA through a first channel if the checking is successful, discards the data of the current frame if the checking is unsuccessful, requests to resend the data of the current frame, and waits for the data of the current frame.
In this embodiment, before the first FPGA sends the instruction to the second FPGA, the first FPGA may perform verification again, read the update data in the storage module corresponding to the second FPGA through the first channel, and verify the read update data, if there is update data that is not verified, use the corresponding storage module as the target storage module, request to resend the update data, wait and obtain the update data, replace the update data in the target storage module with the newly obtained update data through the first channel, and the first FPGA repeats the above process until all the update data in the storage modules corresponding to the second FPGA are successfully verified.
After the two times of verification are completed, it is indicated that the updated data in the storage module corresponding to the second FPGA is correct, at this time, the first FPGA sends an instruction to the second FPGA, and the steps specifically include:
the first FPGA controls a configuration pin PROGRAM _ B of the second FPGA to be in a low level through a GPIO interface, so that the second FPGA is in a reset state;
then, according to the foregoing, the first FPGA controls the channel selection module corresponding to the second FPGA to switch to the second channel where the second FPGA is connected to the corresponding storage module, and after the channel selection module corresponding to the second FPGA is switched to the second channel, the first FPGA releases the configuration pin PROGRAM _ B of the second FPGA through the GPIO interface, so that the configuration pin PROGRAM _ B generates a low pulse, and at this time, the second FPGA performs reinitialization and reloading, that is, obtains update data from the corresponding storage module through the corresponding second channel and updates the update data.
For the update of the first FPGA, the update may be performed in a MultiBoot manner, and the steps include: and the first FPGA waits for the update data of the upper computer, then writes the update data into a storage module corresponding to the first FPGA, and updates by using a MultiBoot mode.
When the MultiBoot mode is used for updating, the updated data is MultiBoot Image. And the storage module also stores a program burned when leaving the factory, the program is called Golden Image, if the FPGA fails to load the program after updating due to various problems in the updating process, the FPGA reloads the Golden Image, and the updating process is executed again until the updating is successful.
The updating form of the MultiBoot can be switched to Golden Image after the updating of the equipment fails, and the equipment can be continuously updated after the updating fails.
Corresponding to the online updating method of the multi-FPGA system in this embodiment, in the multi-FPGA system of this embodiment, the upper computer is configured to designate the first FPGA and the second FPGA from each FPGA, and is further configured to configure the storage modules corresponding to the first FPGA and the second FPGA, respectively, and configure the channel selection module corresponding to the second FPGA, where the FPGAs are configured to execute:
when the FPGA is a first FPGA, acquiring updating data from an upper computer, switching a channel selection module corresponding to a second FPGA to a first channel, and sending the updating data to a storage module corresponding to the second FPGA through the first channel; the FPGA is also used for sending an instruction to the second FPGA and switching the channel selection module corresponding to the second FPGA to a second channel;
and when the FPGA is the second FPGA, acquiring the updating data from the corresponding storage module through the corresponding second channel and updating.
In this embodiment, the FPGA is further configured to perform: and when the FPGA is the first FPGA, waiting for the upper computer to write the update data into the corresponding storage unit, and updating by using a MultiBoot mode.
In addition, in the multi-FPGA system of the present embodiment, the FPGA is further configured to execute the steps or functions implemented by the first FPGA and the second FPGA in the online updating method of the multi-FPGA system.
The embodiment also provides computer equipment which comprises a multi-FPGA system and an upper computer, wherein the multi-FPGA system comprises at least 2 FPGAs, and further comprises a channel selection module and a storage module, second FPGAs in the FPGAs are respectively connected with the corresponding storage modules through the corresponding channel selection modules, a first FPGA in the FPGA is further connected with the storage module corresponding to each second FPGA through the channel selection module corresponding to each second FPGA, the multi-FPGA system is further connected with the upper computer, and the FPGAs in the multi-FPGA system are programmed or configured to execute the multi-FPGA system online updating method in the embodiment.
Example two
The present embodiment is basically the same as the first embodiment, except that in the online updating method of the multi-FPGA system of the present embodiment, after the first FPGA switches the channel selection module corresponding to the second FPGA to the first channel, the data verification process includes:
the first FPGA acquires a current frame of updated data, checks the data of the current frame, caches the data of the current frame into the DDR of the first FPGA if the checking is successful, discards the data of the current frame if the checking is unsuccessful, requests to resend the data of the current frame, and waits for the data of the current frame; after all frames of the updated data are checked, the first FPGA sends the cache data in the DDR to a storage module corresponding to the second FPGA through the first channel. Compared with the first embodiment, the data verification speed of the present embodiment is faster.
In this embodiment, before the first FPGA sends the instruction to the second FPGA, the first FPGA may also perform verification again, read the update data in the storage module corresponding to the second FPGA through the first channel, and verify the read update data, and the specific steps include:
the first FPGA compares the read updating data with the updating data cached in the DDR of the first FPGA, if the read updating data is consistent with the updating data cached in the DDR of the first FPGA, the read updating data is successfully verified, and if the read updating data is inconsistent with the updating data cached in the DDR of the first FPGA, the read updating data is not successfully verified;
for the update data which is not successfully verified, the first FPGA takes the storage module corresponding to the update data which is not successfully verified as a target storage module, requests to resend the update data, waits for and acquires the update data, replaces the update data in the target storage module with the newly acquired update data through the first channel, and then repeats the verification process until all the update data in the storage modules corresponding to the second FPGA are successfully verified.
The foregoing is considered as illustrative of the preferred embodiments of the invention and is not to be construed as limiting the invention in any way. Although the present invention has been described with reference to the preferred embodiments, it is not intended to be limited thereto. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical spirit of the present invention should fall within the protection scope of the technical scheme of the present invention, unless the technical spirit of the present invention departs from the content of the technical scheme of the present invention.
Claims (10)
1. The multi-FPGA system online updating method is characterized in that the multi-FPGA system comprises at least 2 FPGAs, a channel selection module and a storage module, wherein second FPGAs in the FPGAs are respectively connected with the corresponding storage modules through the corresponding channel selection modules, a first FPGA in the FPGAs is also connected with the corresponding storage modules of the second FPGAs through the channel selection modules corresponding to the second FPGAs, and the multi-FPGA system is also connected with an upper computer, and the method comprises the following steps:
the upper computer appoints a first FPGA and a second FPGA from each FPGA, and respectively configures storage modules corresponding to the first FPGA and the second FPGA and also configures a channel selection module corresponding to the second FPGA;
the first FPGA acquires update data from an upper computer, a channel selection module corresponding to the second FPGA is switched to a first channel, and the first FPGA sends the update data to a storage module corresponding to the second FPGA through the first channel;
the first FPGA sends an instruction to the second FPGA, the channel selection module corresponding to the second FPGA is switched to a second channel, and the second FPGA acquires update data from the corresponding storage module through the corresponding second channel and updates the update data.
2. The online updating method of the multi-FPGA system according to claim 1, further comprising a step of data verification after switching the channel selection module corresponding to the second FPGA to the first channel, specifically comprising:
the first FPGA acquires a current frame of the updated data, checks the data of the current frame, sends the data of the current frame to a storage module corresponding to the second FPGA through the first channel if the checking is successful, discards the data of the current frame if the checking is unsuccessful, requests to resend the data of the current frame, and waits for the data of the current frame.
3. The online updating method for the multi-FPGA system according to claim 1, further comprising a step of data verification after switching the channel selection module corresponding to the second FPGA to the first channel, specifically comprising:
the method comprises the steps that a first FPGA acquires a current frame of updated data, checks the data of the current frame, caches the data of the current frame into a DDR of the first FPGA if the checking is successful, discards the data of the current frame if the checking is unsuccessful, requests to resend the data of the current frame, and waits for the data of the current frame;
after all frames of the updated data are checked, the first FPGA sends the cache data in the DDR to the storage module corresponding to the second FPGA through the first channel.
4. The on-line updating method of the multi-FPGA system according to claim 1, wherein before the first FPGA sends the instruction to the second FPGA, the first FPGA further reads the update data in the storage module corresponding to the second FPGA through the first channel, checks the read update data, if the update data which is not successfully checked exists, takes the corresponding storage module as a target storage module, requests to resend the update data, and after waiting and acquiring the update data, replaces the update data in the target storage module with the newly acquired update data through the first channel.
5. The multi-FPGA system online updating method of claim 4, wherein the specific step of verifying the read update data comprises: the first FPGA compares the read updating data with the updating data cached in the DDR of the first FPGA, if the read updating data is consistent with the updating data cached in the DDR of the first FPGA, the read updating data is successfully verified, and if the read updating data is inconsistent with the updating data cached in the DDR of the first FPGA, the read updating data is not successfully verified.
6. The multi-FPGA system online updating method of claim 1, wherein the first FPGA is connected to the second FPGA through a GPIO interface, and the step of sending the instruction to the second FPGA by the first FPGA specifically comprises:
the first FPGA controls the second FPGA to be in a reset state through a GPIO interface;
and after the channel selection module corresponding to the second FPGA is switched to a second channel, the first FPGA controls the second FPGA to reinitialize and reload through the GPIO interface.
7. The multi-FPGA system online updating method of claim 1, further comprising the step of updating the first FPGA, specifically comprising: and the first FPGA writes the updating data into the corresponding storage module and updates the updating data by using a MultiBoot mode.
8. The utility model provides a many FPGA system, its characterized in that, many FPGA system includes 2 at least FPGAs, still includes channel selection module and storage module, second FPGA in the FPGA selects the module and connects with the storage module that corresponds through the channel that corresponds respectively, first FPGA in the FPGA still selects the module and the storage module that every second FPGA corresponds through the channel that every second FPGA corresponds and connects, many FPGA system still with the host computer connection, wherein:
the upper computer is used for appointing a first FPGA and a second FPGA from each FPGA, respectively configuring storage modules corresponding to the first FPGA and the second FPGA, and also configuring a channel selection module corresponding to the second FPGA;
when the FPGA is a first FPGA, the FPGA is used for acquiring update data from an upper computer, switching a channel selection module corresponding to the second FPGA to a first channel, and sending the update data to a storage module corresponding to the second FPGA through the first channel; the FPGA is also used for sending an instruction to the second FPGA and switching the channel selection module corresponding to the second FPGA to a second channel;
and when the FPGA is the second FPGA, the FPGA is used for acquiring the updating data from the corresponding storage module through the corresponding second channel and updating.
9. The multi-FPGA system of claim 8, wherein when the FPGA is the first FPGA, the FPGA is further configured to write the update data into the corresponding storage module, and update the update data using a MultiBoot method.
10. A computer device is characterized by comprising a multi-FPGA system and an upper computer, wherein the multi-FPGA system comprises at least 2 FPGAs, a channel selection module and a storage module, second FPGAs in the FPGAs are respectively connected with the corresponding storage modules through the corresponding channel selection modules, a first FPGA in the FPGAs is further connected with the corresponding storage module of each second FPGA through the channel selection module corresponding to each second FPGA, the multi-FPGA system is further connected with the upper computer, and the FPGAs are programmed or configured to execute the multi-FPGA system online updating method according to any one of claims 1-7.
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| CN115167885A (en) * | 2022-08-03 | 2022-10-11 | 江苏新质信息科技有限公司 | Method and system for loading programs after power-on of multi-FPGA system |
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| CN115167885A (en) * | 2022-08-03 | 2022-10-11 | 江苏新质信息科技有限公司 | Method and system for loading programs after power-on of multi-FPGA system |
| CN115167885B (en) * | 2022-08-03 | 2024-02-06 | 江苏新质信息科技有限公司 | Method and system for loading program after power-on of multi-FPGA system |
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