CN116150064A

CN116150064A - Hot plug method of NVME storage device, backboard and computing device

Info

Publication number: CN116150064A
Application number: CN202211496754.1A
Authority: CN
Inventors: 曾柏杞
Original assignee: XFusion Digital Technologies Co Ltd
Current assignee: XFusion Digital Technologies Co Ltd
Priority date: 2022-11-24
Filing date: 2022-11-24
Publication date: 2023-05-23

Abstract

The application provides a hot plug method, a backboard and a computing device of NVME storage equipment, relates to the technical field of computing equipment, and can realize violent hot plug of the NVME storage equipment under the condition of opening without depending on VMD. The method is applied to a first logic device of a backboard, one end of the first logic device is coupled with a processor, and the other end of the first logic device can be coupled with NVME storage equipment through a hard disk interface, and the method comprises the following steps: a first logic device of the backboard acquires an in-place signal of NVME storage equipment; in the case where the bit signal indicates that the NVME storage device is plugged in, the first logic device of the backplane controls the NVME storage device to power up and sends a drive load signal to the processor to cause the processor to load a drive of the NVME storage device; in the event that the bit signal indicates that the NVME storage device is unplugged, the first logic device of the backplane controls the NVME storage device to power down and sends a drive off-load signal to the processor to cause the processor to off-load the drive of the NVME storage device.

Description

Hot plug method of NVME storage device, backboard and computing device

Technical Field

The application relates to the technical field of computing equipment, in particular to a hot plug method of NVME storage equipment, a backboard and the computing equipment.

Background

Hot plug (hot plug) refers to the fact that a plate, a daughter card, a hard disk and the like in the computing equipment are directly plugged or unplugged under the condition that the computing equipment is not reset and powered down, normal operation of the computing equipment is not affected, and the purpose of plug and play is achieved. Non-volatile memory host controller interface (NVME) storage devices are hard disks that conform to the new generation of protocols, and have a faster read speed and a higher transmission efficiency than conventional hard disks, and thus are increasingly being used.

Hot plug of storage devices is often a frequent operation in the process of maintaining hardware of a computing device, and currently, for NVME storage devices, the hot plug method mainly comprises two steps: notification hot plug scheme with volume management device (volume management device, VMD) closed and violent hot plug scheme with VMD open.

For the notification type hot plug scheme, when the NVME storage device is pulled out, a user is required to firstly issue a command to control the NVME disk to be powered down and unload the drive of the NVME storage device when the NVME storage device is pulled out, and the NVME storage device cannot be pulled out smoothly under the condition of inconvenient operation of the user. For the violent hot plug scheme, the VMD function needs to be supported for implementation, but only a specific model of operating system can support the VMD to be started at present. In view of the above, there is currently a lack of a convenient and versatile hot plug solution.

Disclosure of Invention

The application provides a hot plug method, a back plate and a computing device of NVME storage equipment, which can realize violent hot plug of the NVME storage equipment under the condition of not depending on starting of VMD.

In a first aspect, the present application provides a hot plug method of an NVME storage device, applied to a first logic device of a backplane, where one end of the first logic device is coupled to a processor, and the other end of the first logic device may be coupled to the NVME storage device through a hard disk interface, where the method includes: a first logic device of the backboard acquires an in-place signal of NVME storage equipment; in the case where the bit signal indicates that the NVME storage device is plugged in, the first logic device of the backplane controls the NVME storage device to power up and sends a drive load signal to the processor to cause the processor to load a drive of the NVME storage device; in the event that the bit signal indicates that the NVME storage device is unplugged, the first logic device of the backplane controls the NVME storage device to power down and sends a drive off-load signal to the processor to cause the processor to off-load the drive of the NVME storage device.

According to the hot plug method for the NVME storage device, the power on/off and the loading or unloading driving of the storage device are controlled based on the in-place signal of the NVME storage device, so that the plug-and-play function of violent hot plug is realized. Compared with the notification type hot plug in the prior art, the automatic power-down of the NVME storage device can be realized without manually issuing a command by a user. Compared with the violent hot plug mode for starting the VMD in the prior art, the violent hot plug can be realized without supporting the VMD by an operating system. Therefore, the hot plug method of the NVME storage device greatly facilitates field operation of a user and improves replacement and maintenance efficiency of the hard disk. Moreover, the method is not limited by the specific model of operating system, and has stronger universality.

In one possible implementation, a first logic device of a backplane controls power-up of an NVME storage device, including: the first logic device of the back plate enables a power supply control signal to instruct the back plate to power on the NVME storage device; the first logic device of the back plate controls the NVME storage device to be powered down, comprising: the first logic device of the backplane disables the power control signal to instruct the backplane to power down the NVME storage device.

In another possible implementation manner, the method further includes: the first logic device of the backboard receives Virtual Pin Port (VPP) information from the processor; the first logic device of the backboard analyzes the VPP information to obtain a lighting control signal; based on the lighting control signal, the first logic device of the backboard controls the fault indicator lamp on the backboard to be on or off in a preset mode.

In yet another possible implementation manner, the method further includes: the first logic device of the backboard obtains first indication information and second indication information from a basic input output system BIOS; the first indication information is used for indicating the state of the VMD, and the second indication information is used for indicating the plugging mode of the NVME storage device; the first logic device of the back plate obtains a bit signal of the NVME storage device, and the first logic device comprises: when the first indication information indicates that the state of the VMD is in a closed state and the second indication information indicates that the plugging mode of the NVME storage device is violent hot plugging, the first logic device of the backboard acquires an in-place signal of the NVME storage device.

In yet another possible implementation, the first logic device of the backplane is coupled with a second logic device of the motherboard, the second logic device being coupled with a baseboard management controller (baseboard management controller, BMC); the first indication information and the second indication information are issued to the first logic device of the backboard by the BIOS through the BMC and the second logic device.

In a second aspect, the present application provides a back plane, including a first logic device and a hard disk interface, where the hard disk interface supports insertion or extraction of an NVME storage device; the first logic device comprises a register management unit, a first logic circuit and a second logic circuit; one end of the first logic circuit is coupled with the hard disk interface, and the other end of the first logic circuit is coupled with the register management unit; one end of the second logic circuit is coupled with the hard disk interface, and the other end of the second logic circuit is coupled with the first logic circuit; the first logic circuit is used for acquiring a bit signal of the NVME storage device; the second logic circuit is used for controlling the NVME storage device to be powered on under the condition that the bit signal indicates that the NVME storage device is inserted; or controlling the NVME storage device to be powered down under the condition that the bit signal indicates that the NVME storage device is unplugged; the register management unit is used for sending a drive loading signal to the processor to enable the processor to load the drive of the NVME storage device under the condition that the bit signal indicates that the NVME storage device is inserted; alternatively, in the event that the bit signal indicates that the NVME storage device is unplugged, a drive off-load signal is sent to the processor to cause the processor to off-load the drive of the NVME storage device.

In a possible implementation manner, the back plate further includes: a fault indicator light; the first logic device further includes: a third logic circuit; one end of the third logic circuit is coupled with the fault indicator lamp, and the other end of the third logic circuit is coupled with the register management unit; the register management unit is further configured to receive Virtual Pin Port (VPP) information from the processor, and parse the VPP information to obtain a lighting control signal; the third logic circuit is used for controlling the fault indicator lamp on the backboard to be on or off in a preset mode based on the lighting control signal.

In another possible implementation, the first logic device is a complex programmable logic device (complex programmable logic device, CPLD) or a field-programmable gate array (field-programmable gate array, FPGA).

In a third aspect, the present application provides a hot plug apparatus, the apparatus comprising: the device comprises an acquisition module and a processing module. The acquisition module is used for acquiring an in-place signal of the NVME storage device; the processing module is used for controlling the NVME storage device to be powered on and sending a drive loading signal to the processor under the condition that the bit signal indicates that the NVME storage device is inserted, so that the processor loads the drive of the NVME storage device; in the event that the bit signal indicates that the NVME storage device is unplugged, controlling the NVME storage device to power down, and sending a drive off-load signal to the processor to cause the processor to off-load the drive of the NVME storage device.

In one possible implementation, the processing module is specifically configured to enable the power supply control signal to instruct the backplane to power up the NVME storage device; the power control signal is disabled to instruct the backplane to power down the NVME storage device.

In another possible implementation manner, the obtaining module is further configured to receive virtual pin port VPP information from the processor; the processing module is also used for analyzing the VPP information to obtain a lighting control signal; based on the lighting control signal, the fault indicator lamp on the backboard is controlled to be on or off in a preset mode.

In yet another possible implementation manner, the obtaining module is further configured to obtain the first indication information and the second indication information from a basic input output system BIOS; the first indication information is used for indicating the state of the VMD, and the second indication information is used for indicating the plugging mode of the NVME storage device. The acquisition module is specifically configured to acquire, by using the first logic device of the back plate, an in-place signal of the NVME storage device when the first indication information indicates that the state of the VMD is a closed state and the second indication information indicates that the insertion mode of the NVME storage device is violent hot insertion.

In a fourth aspect, the present application provides a computing device comprising a back plane and a motherboard; the backboard comprises a first logic device and a hard disk interface; the hard disk interface supports the insertion or extraction of the NVME storage device; the main board comprises a processor, a BMC and a second logic device; the BMC is coupled with the second logic device, and the second logic device is coupled with the first logic device; one end of the first logic device is coupled with the processor, and the other end of the first logic device is coupled with the hard disk interface; the first logic device is configured to perform the hot plug method of the NVME storage device described in the first aspect.

In a fifth aspect, the present application provides a computing device comprising a back plane and a motherboard; the backboard comprises a first logic device and a hard disk interface; the hard disk interface supports the insertion or extraction of the NVME storage device; the main board comprises a processor, a BMC and a second logic device; the BMC is coupled with the second logic device, and the second logic device is coupled with the first logic device; the first logic device includes: a register management unit, a first logic circuit and a second logic circuit; the register management unit is coupled with the processor; one end of the first logic circuit is coupled with the hard disk interface, and the other end of the first logic circuit is coupled with the register management unit; one end of the second logic circuit is coupled with the hard disk interface, and the other end of the second logic circuit is coupled with the first logic circuit; the register management unit, the first logic circuit, and the second logic circuit cooperate with each other so that the first logic device performs the hot plug method of the NVME storage device described in the first aspect.

In a sixth aspect, the present application provides a computing device comprising: a processor and a memory; the memory stores instructions executable by the processor; the processor is configured to execute the instructions to cause the computing device to implement the method of the first aspect described above.

In a seventh aspect, the present application provides a computer-readable storage medium comprising: computer software instructions; the computer software instructions, when executed in a computing device, cause the computing device to implement the method of the first aspect described above.

In an eighth aspect, the present application provides a computer program product which, when run on a computer, causes the computer to perform the steps of the related method described in the first aspect above to carry out the method of the first aspect above.

The advantageous effects of the second aspect to the eighth aspect may refer to corresponding descriptions of the first aspect, and are not repeated.

Drawings

FIG. 1 is a schematic architecture diagram of a computing device provided herein;

FIG. 2 is a schematic diagram of the composition of a computing device provided herein;

FIG. 3 is a schematic view of the composition of a back plate provided in the present application;

FIG. 4 is a schematic flow chart of a hot plug method of NVME storage device provided in the present application;

FIG. 5 is a logic block diagram of a hot plug method for NVME storage device provided in the present application;

FIG. 6 is a flow chart of a method for detecting an in-situ signal provided by the present application;

FIG. 7 is a flowchart illustrating a hot plug method of another NVME storage device provided in the present application

FIG. 8 is a flow chart of a method for closing a violent hot plug of a VMD according to the present disclosure;

FIG. 9 is a schematic flow chart of a notification hot plug for closing a VMD provided in the present application;

FIG. 10 is a flow chart of a method for opening a violent hot plug of a VMD according to the present disclosure;

FIG. 11 is a schematic diagram illustrating a hot plug device according to the present disclosure;

FIG. 12 is a schematic diagram of the composition of another computing device provided herein.

Detailed Description

The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.

It should be noted that, in the embodiments of the present application, words such as "exemplary" or "such as" are used to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "for example" should not be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete fashion.

In order to clearly describe the technical solutions of the embodiments of the present application, in the embodiments of the present application, the terms "first", "second", and the like are used to distinguish the same item or similar items having substantially the same function and effect, and those skilled in the art will understand that the terms "first", "second", and the like are not limited in number and execution order.

1. Hot plug: the plug-and-play operation method refers to external devices such as a board card, a daughter card and a hard disk in the computing device, and the operations such as plug-in and pull-out are performed under the condition that the computing device is not reset and powered down, but the normal operation of the computing device is not affected, and the plug-and-play effect is realized.

2. NVME: the non-volatile memory host controller interface specification (non-volatile memory express) is a new generation of logical device interface specifications. The NVME storage device is a storage device conforming to the NVME protocol, and can directly communicate with the processor through a high-speed serial computer expansion bus standard (peripheral component interconnect express, PCIe) bus, so that the communication efficiency is high.

As described in the background, in the course of a computing device maintenance upgrade, an upgrade or replacement of a hardware device is often involved. In order to ensure the maintenance and upgrade efficiency, most of the storage devices support hot plug at present, and replacement and upgrade of the storage devices can be realized without shutdown or restarting of the computing device. For NVME storage devices, there are two schemes currently supporting hot plug: one is a notification hot plug mode that turns off the volume management device (volume management device, VMD), and the other is a violent hot plug mode that turns on the VMD.

VMD is a deployment solution pushed by a storage device, which supports hot upgrade and replacement (replacement may include insertion and extraction) of an NVMe storage device from a PCIe bus, without shutting down a computing device, and at the same time standardizing a process of lighting a hard disk, which can help a user to more quickly identify an operating state of an NMVE storage device.

For the notification type hot plug mode of closing the VMD, in the process of extracting the NVME storage device, a user firstly needs to control the NVME storage device to be powered down and unload the drive of the NVME disk by issuing a command in an operating system, then the operation is complicated, and the hot plug cannot be successfully completed under the condition of inconvenient operation of the user.

For the manner of opening the violent hot plug of the VMD, the VMD function may implement direct plug of the NVME storage device, but not all operating systems may support the VMD. That is, only a specific type of operating system can use a manner of opening a violent hot plug of the VMD, resulting in a weak versatility of the manner.

In view of the above, there is currently a lack of a convenient and versatile hot plug method.

Under the background technology, the embodiment of the application provides a hot plug method of NVME storage equipment, which automatically controls the NVME storage equipment to be electrified or instructs a processor to load a drive based on an in-place signal of the NVME storage equipment, so that the normal use of the NVME storage equipment is ensured. In addition, the NVME storage device is automatically controlled to be powered down or the processor is instructed to unload the drive based on the in-place information, so that the normal pulling-out flow of the NVME storage device is ensured. By the method, the violent hot plug of the NVME storage device can be realized without depending on the starting of the VMD.

The hot plug method of the NVME storage device can be applied to the computing device shown in the figure 1. The hardware portion of the computing device includes at least a processor and an out-of-band controller, and the software portion mainly includes an out-of-band management module BMC, processor firmware, and an Operating System (OS).

The out-of-band management module BMC is located in the out-of-band controller, and the operating system OS runs in the processor, and the processor firmware may be located in the processor (as shown in fig. 1), or the processor firmware may also be located in a firmware chip (not shown in fig. 1) outside the processor. In addition, the VMD in the embodiment of the present application is a software program, which may be located in the processor shown in fig. 1 (not shown in fig. 1), and controlled by the operating system OS.

The out-of-band management module may be a management unit of a non-business module. For example, an out-of-band management module, which is completely independent of the operating system of the computing device, may communicate with the BIOS and OS (or OS management unit) through an out-of-band management interface of the computing device, for remote maintenance and management of the computing device through a dedicated data channel.

It should be noted that, the out-of-band management module described in the following embodiments performs a certain step, which can be understood as: the out-of-band controller invokes the out-of-band management module to perform this step.

By way of example, the processor Firmware (also referred to as a processor Firmware program) may be Firmware such as Firmware, basic input output system (basic input output system, BIOS), manageability engine (management engine, ME), microcode, or intelligent management unit (intelligent management unit, IMU). It should be noted that the embodiments of the present application are not limited to the specific form of the processor firmware, and the above are merely exemplary illustrations. In the following embodiments, only the BIOS is taken as an example for the processor firmware.

It should be noted that, the system architecture and the application scenario described in the embodiments of the present application are for more clearly describing the technical solution of the embodiments of the present application, and do not constitute a limitation on the technical solution provided in the embodiments of the present application, and those skilled in the art can know that, with the evolution of the system architecture and the appearance of a new service scenario, the technical solution provided in the embodiments of the present application is also applicable to similar technical problems.

Fig. 2 is a schematic diagram of a composition of a computing device according to an embodiment of the present application, where the computing device includes a back plate and a motherboard. As shown in fig. 2, the back board includes a first logic device and a hard disk interface, and the hard disk interface supports insertion or extraction of the NVME storage device. The main board comprises a processor, a BMC and a second logic device.

Wherein the BMC is coupled to the second logic device, the second logic device is coupled to the first logic device; one end of the first logic device is coupled with the processor, and the other end of the first logic device is coupled with the hard disk interface.

The violent hot plug storage equipment can be put into use after being plugged in, and can be used after being pulled out, so that other extra operations of a user are not needed, and the normal operation of the computing equipment is not influenced. In some embodiments, the first logic device may be coupled to the NVME storage device through a hard disk interface, and may obtain an in-place signal of the NVME storage device, and control powering up of the NVME storage device and instructing loading of the driver by the processor, or control powering down of the NVME storage device and instructing unloading of the driver by the processor, based on an indication state (insertion or extraction) of the in-place signal, to implement violent hot plug of the NVME storage device.

Fig. 3 is a schematic diagram of a back plate according to an embodiment of the present application, where the back plate includes a first logic device and a hard disk interface, and the hard disk interface supports insertion or extraction of an NVME storage device. The first logic device includes a register management unit, a first logic circuit (which may be described as logic 1), and a second logic circuit (which may be described as logic 2).

One end of the first logic circuit is coupled with the hard disk interface, and the other end of the first logic circuit is coupled with the register management unit; one end of the second logic circuit is coupled with the hard disk interface, and the other end of the second logic circuit is coupled with the first logic circuit.

The logic circuit is a virtual circuit implemented by codes inside the logic device, and can implement a specific control function according to a signal instruction. The register management unit is a virtual unit inside the logic device, and can be connected with a Virtual Pin Port (VPP) on the processor through an I2C bus to realize the communication function of the first logic device and the processor. For example, the register management unit may be a virtual unit of the logic device obtained by simulating the function of the model PCA9555 chip.

In some embodiments, the first logic is to obtain a bit signal of the NVME storage device; the second logic circuit is used for controlling the NVME storage device to be powered on under the condition that the bit signal indicates that the NVME storage device is inserted; or controlling the NVME storage device to be powered down under the condition that the bit signal indicates that the NVME storage device is unplugged; the register management unit is used for sending a drive loading signal to the processor to enable the processor to load the drive of the NVME storage device under the condition that the bit signal indicates that the NVME storage device is inserted; alternatively, in the event that the bit signal indicates that the NVME storage device is unplugged, a drive off-load signal is sent to the processor to cause the processor to off-load the drive of the NVME storage device.

In some embodiments, the back plate further comprises: fault indicator light (which may be denoted as fault light). The first logic device further includes: a third logic circuit (which may be denoted logic 3); one end of the third logic circuit is coupled with the fault indicator lamp, and the other end of the third logic circuit is coupled with the register management unit.

The register management unit is also used for receiving the VPP information from the processor and analyzing the VPP information to obtain a lighting control signal; the third logic circuit is used for controlling the fault indicator lamp on the backboard to be on or off in a preset mode based on the lighting control signal. The VPP information is standard lighting information for PCIe management.

In some embodiments, the first logic device may be a CPLD or an FPGA. Similarly, the second logic device on the motherboard may also be a CPLD or FPGA.

It can be seen that the computing device and the back plate provided in the present application are mainly described above in terms of hardware structures. The hot plug method of the NVME storage device provided by the application is described below with reference to specific drawings and embodiments.

Fig. 4 is a flow chart of a hot plug method of an NVME storage device according to an embodiment of the present application. The hot plug method of the NVME storage device provided by the application can be applied to the computing device shown in fig. 2 or the backboard shown in fig. 3.

As shown in fig. 4, the hot plug method of the NVME storage device provided in the present application specifically may include the following steps:

s401, a first logic device of the backboard obtains a bit signal of the NVME storage device.

The in-place signal can be used for indicating whether the external devices such as the board card, the daughter card, the hard disk and the like are inserted into the computing device, and in the embodiment of the application, whether the hot plug flow is executed is judged mainly through the in-place signal of the NVME storage device. As described above, the first logic device is coupled to the hard disk interface, so that the first logic device can obtain the in-place signal generated by the hard disk interface, and further determine whether the NVME storage device is in place, i.e. plugged in or plugged out, based on the in-place signal.

For example, the hard disk interface may generate a high level on-bit signal when the NVME storage device is inserted into the hard disk interface, and the hard disk interface may generate a low level on-bit signal when the NVME storage device is pulled out of the hard disk interface.

For example, fig. 5 is taken as an example with reference to fig. 2 and fig. 3. As shown in fig. 5, the first logic device on the back board includes a first logic circuit, and one end of the first logic circuit is coupled to the hard disk interface, so as to obtain the bit signal of the NVME storage device. Specifically, the bit signal may be transmitted through IFDET and Present pins.

In other embodiments, S401 as shown in fig. 6 may specifically include the following: S4011-S4012.

S4011, a first logic device BIOS of the backboard obtains first indication information and second indication information.

The first indication information is used for indicating the state of the VMD, and the second indication information is used for indicating the plugging mode of the NVME storage device.

It should be noted that, the state of the VMD includes an on state or an off state, and in a specific scenario, a user may configure the on or off state of the VMD according to the requirement of the user. The plugging mode of the NVME storage device comprises a notification type hot plugging mode or a violent hot plugging mode.

As described above, the current hot plug scheme includes a notification hot plug and a violent hot plug, and the configuration item of the current BIOS includes first indication information indicating the state of the VMD, so that the user may set the VMD to be turned off or turned on in a BIOS setup (setup) interface during the process of starting the computing device to enter the BIOS. If the VMD is opened, the plugging mode of the NVME storage device is a violent hot plugging mode, and if the VMD is closed, the plugging mode of the NVME storage device is a notification hot plugging mode.

The present application is mainly aimed at using a violent hot plug mode without depending on a VMD, so that, for a BIOS newly added configuration item, namely the second instruction information, to instruct a plug mode of an NVME storage device, a user can select, by configuring the first instruction information and the second instruction information, a violent hot plug mode of opening the VMD, a notification hot plug mode of closing the VMD, or a violent hot plug mode of closing the VMD.

For example, the first indication information may be described using vmd_mode, and the second indication information may be described using hotplug_surrise. Vmd_mode=0 and hotplug_surrise=0 may represent a notification hot plug Mode to shut down the VMD. Vmd_mode=0, hotplug_surrise=1 may represent a brute force hot plug Mode to shut down the VMD. Vmd_mode=1 may represent a brute force hot plug Mode to turn on the VMD.

In some embodiments, as shown in fig. 2, a first logic device of the backplane is coupled with a second logic device of the motherboard, the second logic device being coupled with the BMC. The first indication information and the second indication information may be issued by the BIOS to the first logic device of the backplane through the BMC and the second logic device. For example, a user may enter a setup interface of the BIOS during a computing device start-up process to configure the first indication information and the second indication information. The BIOS may then send the first and second indication information to the BMC, which may further write the information to a second logic device (e.g., motherboard CPLD) via a local bus (local bus), and the second logic device may then communicate the first and second indication information to the first logic device of the backplane via SGPIO signals.

S4012, when the first indication information indicates that the state of the VMD is a closed state and the second indication information indicates that the plugging mode of the NVME storage device is violent hot plugging, the first logic device of the backboard obtains an in-place signal of the NVME storage device.

In some embodiments, when the state of the VMD is the closed state and the plugging mode of the NVME storage device is the violent hot plug, the first logic device acquires the in-place signal to determine the plugging or unplugging state of the NVME storage device. For example, after the first logic circuit in the first logic device acquires the bit signal, the level value of the bit signal may be determined to change, thereby determining the bit situation. For example, if the level value of the bit signal changes from 0 to 1, the first logic device may determine that the NVME storage device is inserted, i.e., in bit. If the level value of the bit signal changes from 1 to 0, the first logic device may determine that the NVME storage device is unplugged, i.e., out of bit.

S402, controlling the NVME storage device to be powered on by the first logic device of the backboard under the condition that the bit signal indicates that the NVME storage device is inserted, and sending a drive loading signal to the processor so that the processor loads the drive of the NMVE storage device.

It should be appreciated that NVME storage devices implement hot plug, requiring power support as well as drive support. The power supply enables the NVME storage device to run, and the driver is a bridge built between hardware of the computing device and an operating system, so that the operating system can correctly identify, manage and use corresponding hardware. Thus, loading the drive of the NVME storage device may allow an operating system or processor of the computing device to identify the NVME storage device and access to transfer data.

The violent hot plug is mainly aimed at realizing the effect of plug and play, namely, after the storage device is inserted into the computing device, the computing device can automatically complete the power-on and corresponding driving loading operation of the storage device, or after the storage device is pulled out from the computing device, the computing device can automatically complete the power-off and corresponding driving unloading operation of the storage device, and other operations do not need to be additionally carried out by a user. Therefore, the first logic device in the embodiment of the application controls the NVME storage device to be inserted, namely, automatically powered on and loads the driver based on the in-place signal, so that the NVME storage device can enter a normal use state without other operations of a user after being inserted.

The case of NVME storage device insertion is described below with reference to the accompanying drawings.

Specifically, the first logic device of the backplane controls the NVME storage device to be powered on, which may include: the first logic device of the backplane enables a power control signal to instruct the backplane to power up the NVME storage device.

Continuing with the description of fig. 5, it can be seen that the present application establishes an association between the bit signal and the power supply control signal (pwr_en in the figure) by configuring the first logic circuit to be coupled to the second logic circuit. When the NVME storage device is inserted, the second logic circuit pulls up the level value of the power control signal based on the level value 1 even if the power control signal is enabled, when the bit signal is high, i.e., the level value is 1. The second logic circuit of the first logic device may therefore instruct the back plane to power up the NMVE storage device by enabling the functional control signal.

In addition, in FIG. 5, a first logic device is coupled to the processor, the first logic device may send a driver load signal to the processor so that the processor may load a driver of the NVME storage device to establish a PCIe connection between the processor and the NVME storage device.

Specifically, the first logic device includes a register management unit, and the coupling of the first logic device to the processor is implemented through a connection established between the register management unit and an I2C bus on the VPP of the processor. Thus, the first logic device may implement sending a drive load signal to the processor by reporting the value of a particular register (register 2 in the figure) in the register management unit to the processor.

It can be seen that the register 2 in the register management unit of fig. 5 is coupled to the first logic circuit, i.e. the drive control signal (BUTTON#, in the figure) is also associated with the bit signal. Illustratively, when the NVME storage device is plugged into the computing device, the level value of the drive control signal is also pulled high to 1, and the corresponding value of register 2 is rewritten to 1. Thus, the first logic device reporting the value 1 of register 2 to the processor may be understood as sending a drive load signal, such that the processor responds to the drive load signal and loads the drive of the NVME storage device to establish a PCIe connection with the NVME storage device.

S403, controlling the NVME storage device to be powered down by the first logic device of the backboard under the condition that the bit signal indicates that the NVME storage device is pulled out, and sending a drive unloading signal to the processor so that the processor can unload the drive of the NVME storage device.

In the process of extracting the NVME storage device, if the power is not turned off or the driver is not timely unloaded, incomplete data reading or writing tasks may exist, but at this time, the NVME storage device is already extracted, and in this case, the normal operation of the computing device is easily affected. Therefore, the embodiment of the application controls the NVME storage device to be pulled out, namely automatically powering down and unloading the drive based on the in-place signal, so that the NVME storage device can be pulled out to normally finish the use.

The case of the NVME storage device being unplugged will be described below with reference to the accompanying drawings.

Specifically, the first logic device of the backplane controls the NVME storage device to be powered down, which may include: the first logic device of the backplane disables the power control signal to instruct the backplane to power down the NVME storage device.

In connection with the foregoing description, when the NVME storage device is unplugged, the second logic circuit may pull down the level value corresponding to the power control signal (pwr_en in the drawing) to 0, i.e., disable the power control signal, based on the level value 0 when the bit signal is at the low level. The second logic circuit of the first logic device may therefore instruct the back plane to power down the NMVE storage device by disabling the functional control signal.

In addition, when the NVME storage device is unplugged from the computing device, the level value of the drive control signal is also pulled down to 0, and the value of the corresponding register 2 in the register management unit is also rewritten to 0, for example. Thus, the register management unit may report a value of 0 for register 2 to the processor that may be considered to send a drive offload signal, causing the processor to respond to the drive offload signal and offload the drive of the NVME storage device to disconnect the PCIe connection with the NVME storage device.

The first logic device of the back plate may also perform an operation of lighting the hard disk, so as to intuitively reflect the operation state of the hard disk to the user by controlling a light-emitting diode (LED) indicator on the back plate. Specifically, in connection with FIG. 4, as shown in FIG. 7, the first logic device of the backplane may also perform S404-S406 as follows.

S404, the first logic device of the backboard receives VPP information from the processor.

S405, the first logic device of the backboard analyzes the VPP information to obtain a lighting control signal.

S406, based on the lighting control signal, the first logic device of the backboard controls the fault indicator lamp on the backboard to be turned on or off in a preset mode.

The VPP information is standard lighting information for PCIe management.

In some embodiments, the first logic device of the backplane may report bit information to the processor, as shown in fig. 5, and the first logic circuit sends a bit state (e.g., prsnt#, as shown) to the register 3 in the register management unit to overwrite the value of the register 3. Further, the register management unit reports the value of the register 3, so that the processor can acquire the bit state of the NVME storage device. The processor may then issue VPP information via the I2C bus according to the bit status, where the VPP information includes information related to the lighting of the hard disk. As described above, the register management unit in the first logic device is coupled to the third logic circuit, and after receiving the VPP information, the register management unit can analyze the VPP information to obtain a lighting control signal (PWRLED in fig. 3), and based on this signal, the third logic circuit can control the fault indicator lamp (fault lamp) on the back panel to be turned on or off in a preset manner.

It should be noted that the preset manner may indicate different operation states of the NVME storage device. For example, the NVME storage device is in place and has no fault, or is performing a read/write operation, or is out of place, the fault indicator light is off. When the NVME storage device fails, the fault indicator light is normally on. The NVME storage device is in the hot plug process and the fault indicator lights flash at a specific frequency. Specific control modes can be referred to in related technical documents of VPP information, and embodiments of the present application will not be described in detail.

Optionally, as shown in fig. 5, an operation lamp (Active lamp) is further provided on the back board to indicate the power-on condition of the NVME storage device. The running light is controlled by a running light control signal (ACT in fig. 5) of the NVME storage device. Specifically, after the NVME storage device is powered on, the NVME may send a running light control signal to the first logic device of the backplane, and the first logic device of the backplane may control the running light to be turned on based on the running light control signal to indicate to the user that the NVME storage device is powered on.

The technical scheme provided by the embodiment at least brings the following beneficial effects, and the hot plug method for the NVME storage device provided by the embodiment of the application controls the power on/off and the loading or unloading driving of the storage device based on the in-place signal of the NVME storage device so as to realize the plug-and-play function of violent hot plug. Compared with the notification type hot plug in the prior art, the automatic power-down of the NVME storage device can be realized without manually issuing a command by a user. Compared with the violent hot plug mode for starting the VMD in the prior art, the violent hot plug can be realized without supporting the VMD by an operating system. Therefore, the hot plug method of the NVME storage device greatly facilitates field operation of a user and improves replacement and maintenance efficiency of the hard disk. Moreover, the method is not limited by the specific model of operating system, and has stronger universality.

Furthermore, the function of hard disk lighting can be reserved, and a user can intuitively judge the running state of the NVME storage device based on the indicator lamp conveniently. In addition, through configuration of the BIOS interface, a user can independently select a proper hot plug mode, and the method can be applied to most of scenes of computing equipment maintenance.

Fig. 8 is a schematic flow chart of a violent hot plug for closing a VMD according to an embodiment of the present application. As shown in fig. 8, a user may configure vmd_mode=0 and hotplug_Surpise=1 in the BIOS, and then the BIOS reports the configuration to the BMC, and the BMC further writes the configuration into the second logic device of the motherboard, and the second logic device writes the configuration into the first logic device of the backplane through the SGPIO signal. The first logic device controls the powering on and powering off and loading or unloading of the NVME storage device based on the configuration, and analyzes VPP information to realize hard disk lighting.

Fig. 9 is a schematic flow chart of a notification hot plug for closing a VMD according to an embodiment of the present application. As shown in fig. 9, the user may configure vmd_mode=0 and hotplug_Surpise=0 in the BIOS, and then the BIOS reports the configuration to the BMC, and the BMC further writes the configuration to the second logic device of the motherboard, and the second logic device writes the configuration to the first logic device of the backplane through the SGPIO signal. The first logic device informs the processor of the presence based on the configuration in a notification type hot plug mode, and the processor controls the NVME storage device to be powered on and powered off and controls the hard disk to be lighted.

Fig. 10 is a schematic flow chart of a violent hot plug for starting a VMD according to an embodiment of the present application. As shown in fig. 10, the user may configure vmd_mode=1 in the BIOS, and then the BIOS reports the configuration to the BMC, and the BMC further writes the configuration to the second logic device of the motherboard, and the second logic device writes the configuration to the first logic device of the backplane through the SGPIO signal. The first logic device controls the NVME storage device to be powered on and powered off and controls the hard disk to be lighted through a VMD function according to the mode of violent hot plug started by the VMD based on the configuration.

It can be seen that the foregoing description of the solution provided by the embodiments of the present application has been presented mainly from a method perspective. To achieve the above-mentioned functions, embodiments of the present application provide corresponding hardware structures and/or software modules that perform the respective functions. Those of skill in the art will readily appreciate that the various illustrative modules and algorithm steps described in connection with the embodiments disclosed herein may be implemented as hardware or combinations of hardware and computer software. Whether a function is implemented as hardware or computer software driven hardware depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

In an exemplary embodiment, the present application further provides a hot plug device, which may be the first logic device of the above-mentioned backplane. The hot plug apparatus may include one or more functional components for implementing the hot plug method of the NVME storage device of the above method embodiment.

For example, fig. 11 is a schematic diagram of the composition of a computing device according to an embodiment of the present application. As shown in fig. 11, the hot plug apparatus includes: the device comprises: the acquisition module 1101 and the processing module 1102.

The obtaining module 1101 is configured to obtain an in-bit signal of the NVME storage device; the processing module 1102 is configured to control the NVME storage device to power up and send a drive load signal to the processor to cause the processor to load a drive of the NVME storage device if the bit signal indicates that the NVME storage device is inserted; in the event that the bit signal indicates that the NVME storage device is unplugged, controlling the NVME storage device to power down, and sending a drive off-load signal to the processor to cause the processor to off-load the drive of the NVME storage device.

In some embodiments, processing module 1102 is specifically configured to enable a power control signal to instruct the backplane to power up the NVME storage device; the power control signal is disabled to instruct the backplane to power down the NVME storage device.

In some embodiments, the obtaining module 1101 is further configured to receive virtual pin port VPP information from a processor; the processing module 1102 is further configured to parse VPP information to obtain a lighting control signal; based on the lighting control signal, the fault indicator lamp on the backboard is controlled to be on or off in a preset mode.

In some embodiments, the obtaining module 1101 is further configured to obtain the first indication information and the second indication information from a basic input output system BIOS; the first indication information is used for indicating the state of the VMD, and the second indication information is used for indicating the plugging mode of the NVME storage device. The obtaining module 1101 is specifically configured to obtain, when the first indication information indicates that the state of the VMD is a closed state and the second indication information indicates that the insertion mode of the NVME storage device is violent hot insertion, an in-place signal of the NVME storage device by using the first logic device of the back board.

In the case of implementing the functions of the integrated modules described above in the form of hardware, the embodiments of the present application provide a schematic diagram of the composition of yet another computing device. As shown in fig. 12, the computing device 1200 includes: a processor 1202, a communication interface 1203, and a bus 1204. Optionally, the computing device may also include a memory 1201.

The processor 1202 may be a processor that implements or performs the various illustrative logical blocks, modules, and circuits described in connection with the disclosure herein. The processor 1202 may be a central processor, a general purpose processor, a digital signal processor, an application specific integrated circuit, a field programmable gate array or other programmable logic device, a transistor logic device, a hardware component, or any combination thereof. Which may implement or perform the various exemplary logic blocks, modules, and circuits described in connection with this disclosure. The processor 1202 may also be a combination that performs computing functions, such as including one or more microprocessors, a combination of a DSP and a microprocessor, or the like.

A communication interface 1203 is configured to connect with other devices via a communication network. The communication network may be an ethernet, a radio access network, a wireless local area network (wireless local area networks, WLAN), etc.

The memory 1201 may be, but is not limited to, a read-only memory (ROM) or other type of static storage device that can store static information and instructions, a random access memory (random access memory, RAM) or other type of dynamic storage device that can store information and instructions, or an electrically erasable programmable read-only memory (electrically erasable programmable read-only memory, EEPROM), magnetic disk storage or other magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer.

As a possible implementation, the memory 1201 may exist separately from the processor 1202, and the memory 1201 may be connected to the processor 1202 by the bus 1204 for storing instructions or program code. The processor 1202, when calling and executing instructions or program code stored in the memory 1201, can implement the hot plug method of the NVME storage device provided in the embodiments of the present application.

In another possible implementation, the memory 1201 may also be integrated with the processor 1202.

Bus 1204, which may be an extended industry standard architecture (extended industry standard architecture, EISA) bus, or the like. Bus 1204 may be classified as an address bus, a data bus, a control bus, etc. For ease of illustration, only one thick line is shown in fig. 12, but not only one bus or one type of bus.

From the foregoing description of the embodiments, it will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-described division of functional modules is illustrated, and in practical application, the above-described functional allocation may be performed by different functional modules according to needs, i.e. the internal structure of the computing device is divided into different functional modules to perform all or part of the functions described above.

Embodiments of the present application also provide a computer-readable storage medium. All or part of the flow in the above method embodiments may be implemented by computer instructions to instruct related hardware, and the program may be stored in the above computer readable storage medium, and the program may include the flow in the above method embodiments when executed. The computer readable storage medium may be any of the foregoing embodiments or memory. The computer readable storage medium may also be an external storage device of the computing device, such as a plug-in hard disk provided on the computing device, a Smart Media Card (SMC), a Secure Digital (SD) card, a flash card, or the like. Further, the computer-readable storage medium may also include both an internal storage unit and an external storage device of the computing device. The computer readable storage medium is used to store the computer program and other programs and data required by the computing device. The above-described computer-readable storage medium may also be used to temporarily store data that has been output or is to be output.

Embodiments of the present application also provide a computer program product comprising a computer program that, when run on a computing device, causes the computing device to perform the method of hot plug of any one of the NVME storage devices provided in the embodiments above.

Although the present application has been described herein in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed application, from a review of the figures, the disclosure, and the appended claims. In the claims, the word "Comprising" does not exclude other elements or steps, and the "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Although the present application has been described in connection with specific features and embodiments thereof, it will be apparent that various modifications and combinations can be made without departing from the spirit and scope of the application. Accordingly, the specification and drawings are merely exemplary illustrations of the present application as defined in the appended claims and are considered to cover any and all modifications, variations, combinations, or equivalents that fall within the scope of the present application. It will be apparent to those skilled in the art that various modifications and variations can be made in the present application without departing from the spirit or scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims and the equivalents thereof, the present application is intended to cover such modifications and variations.

The foregoing is merely a specific embodiment of the present application, but the protection scope of the present application is not limited thereto, and any changes or substitutions within the technical scope of the present disclosure should be covered in the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A method for hot plug of an NVME storage device, applied to a first logic device of a backplane, one end of the first logic device being coupled to a processor, and the other end of the first logic device being couplable to the NVME storage device through a hard disk interface, the method comprising:

a first logic device of the backboard obtains an in-place signal of the NVME storage device;

in the event that the bit signal indicates that the NVME storage device is plugged in, the first logic device of the backplane controls the NVME storage device to power up and sends a drive load signal to the processor to cause the processor to load a drive of the NVME storage device;

and if the bit signal indicates that the NVME storage device is unplugged, the first logic device of the backboard controls the NVME storage device to be powered down, and sends a drive uninstall signal to the processor so that the processor uninstalls the drive of the NVME storage device.

2. The method of claim 1, wherein the step of determining the position of the substrate comprises,

the first logic device of the back plane controls the NVME storage device to power up, including:

a first logic device of the backplane enables a power supply control signal to instruct the backplane to power up the NVME storage device;

the first logic device of the back plate controls the NVME storage device to be powered down, including:

the first logic device of the backplane disables the power control signal to instruct the backplane to power down the NVME storage device.

3. The method according to claim 1 or 2, characterized in that the method further comprises:

the first logic device of the back plate receives virtual pin port VPP information from the processor;

the first logic device of the backboard analyzes the VPP information to obtain a lighting control signal;

based on the lighting control signal, the first logic device of the backboard controls the fault indicator lamp on the backboard to be turned on or off in a preset mode.

4. A method according to any one of claims 1-3, wherein the method further comprises:

the first logic device of the backboard obtains first indication information and second indication information from a basic input output system BIOS; the first indication information is used for indicating the state of the VMD, and the second indication information is used for indicating the plugging mode of the NVME storage device;

The first logic device of the back plane obtains the bit signal of the NVME storage device, including:

when the first indication information indicates that the state of the VMD is a closed state and the second indication information indicates that the plugging mode of the NVME storage device is violent hot plugging, the first logic device of the backboard obtains an in-place signal of the NVME storage device.

5. The method of claim 4, wherein the first logic device of the backplane is coupled with a second logic device of a motherboard, the second logic device being coupled with a baseboard management controller, BMC;

the first indication information and the second indication information are issued to a first logic device of the backboard by the BIOS through the BMC and the second logic device.

6. The backboard is characterized by comprising a first logic device and a hard disk interface, wherein the hard disk interface supports the insertion or extraction of NVME storage equipment; the first logic device comprises a register management unit, a first logic circuit and a second logic circuit;

one end of the first logic circuit is coupled with the hard disk interface, and the other end of the first logic circuit is coupled with the register management unit; one end of the second logic circuit is coupled with the hard disk interface, and the other end of the second logic circuit is coupled with the first logic circuit;

The first logic circuit is used for acquiring a bit signal of the NVME storage device;

the second logic circuit is configured to control the NVME storage device to be powered on if the bit signal indicates that the NVME storage device is inserted; or controlling the NVME storage device to be powered down under the condition that the bit signal indicates that the NVME storage device is pulled out;

the register management unit is used for sending a drive loading signal to a processor to enable the processor to load the drive of the NVME storage device under the condition that the bit signal indicates that the NVME storage device is inserted; or, if the bit signal indicates that the NVME storage device is unplugged, sending a drive offload signal to the processor to cause the processor to offload the drive of the NVME storage device.

7. The back plate of claim 6, wherein said back plate further comprises: a fault indicator light; the first logic device further includes: a third logic circuit; one end of the third logic circuit is coupled with the fault indicator lamp, and the other end of the third logic circuit is coupled with the register management unit;

the register management unit is also used for receiving the VPP information from the processor and analyzing the VPP information to obtain a lighting control signal;

The third logic circuit is used for controlling the fault indicator lamp on the backboard to be turned on or off in a preset mode based on the lighting control signal.

8. The back plate of claim 6 or 7, wherein the first logic device is a complex programmable logic device CPLD or a field programmable gate array FPGA.

9. A computing device comprising a back plane and a motherboard; the backboard comprises a first logic device and a hard disk interface; the hard disk interface supports the insertion or extraction of the NVME storage device; the main board comprises a processor, a BMC and a second logic device;

the BMC is coupled with the second logic device, and the second logic device is coupled with the first logic device;

one end of the first logic device is coupled with the processor, and the other end of the first logic device is coupled with the hard disk interface;

the first logic device is configured to perform the hot plug method of the NVME storage device of any one of claims 1-5.

10. A computing device comprising a back plane and a motherboard; the backboard comprises a first logic device and a hard disk interface; the hard disk interface supports the insertion or extraction of the NVME storage device; the main board comprises a processor, a BMC and a second logic device; the BMC is coupled with the second logic device, and the second logic device is coupled with the first logic device;

The first logic device includes: a register management unit, a first logic circuit and a second logic circuit;

the register management unit is coupled with the processor; one end of the first logic circuit is coupled with the hard disk interface, and the other end of the first logic circuit is coupled with the register management unit; one end of the second logic circuit is coupled with the hard disk interface, and the other end of the second logic circuit is coupled with the first logic circuit;

the register management unit, the first logic circuit, and the second logic circuit cooperate with each other such that the first logic device performs the hot plug method of the NVME storage device of any one of claims 1-5.