CN112768517A - 绝缘栅双极型晶体管 - Google Patents

绝缘栅双极型晶体管 Download PDF

Info

Publication number
CN112768517A
CN112768517A CN201911065246.6A CN201911065246A CN112768517A CN 112768517 A CN112768517 A CN 112768517A CN 201911065246 A CN201911065246 A CN 201911065246A CN 112768517 A CN112768517 A CN 112768517A
Authority
CN
China
Prior art keywords
region
type
doping concentration
conductivity type
anode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201911065246.6A
Other languages
English (en)
Other versions
CN112768517B (zh
Inventor
张龙
马杰
顾炎
张森
祝靖
龚金丽
孙伟锋
时龙兴
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Southeast University
CSMC Technologies Fab2 Co Ltd
Original Assignee
Southeast University
CSMC Technologies Fab2 Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Southeast University, CSMC Technologies Fab2 Co Ltd filed Critical Southeast University
Priority to CN201911065246.6A priority Critical patent/CN112768517B/zh
Priority to EP20884449.8A priority patent/EP3989292A4/en
Priority to US17/762,212 priority patent/US20220376094A1/en
Priority to PCT/CN2020/111385 priority patent/WO2021088478A1/zh
Publication of CN112768517A publication Critical patent/CN112768517A/zh
Application granted granted Critical
Publication of CN112768517B publication Critical patent/CN112768517B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7394—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET on an insulating layer or substrate, e.g. thin film device or device isolated from the bulk substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
    • H01L29/0834—Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/404—Multiple field plate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Thin Film Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

本发明涉及一种绝缘栅双极型晶体管，包括设于所述漂移区上的阳极第一导电类型区，所述阳极第一导电类型区包括第一区和第二区，所述阳极第二导电类型区包括第三区和第四区，所述第一区的掺杂浓度小于所述第二区，所述第三区的掺杂浓度小于所述第四区，所述第三区设于所述第四区和所述体区之间，所述第一区设于所述第四区下方，所述第二区设于所述第三区下方、且位于所述第一区和所述体区之间。本发明能够在线性电流区域提高注入效率，获得更低的导通压降；并且在饱和电流区域降低饱和电流，获得更大的安全工作区。

Description

绝缘栅双极型晶体管
技术领域
本发明涉及半导体制造领域，特别是涉及一种绝缘栅双极型晶体管。
背景技术
对于传统的绝缘栅双极型晶体管(Insulated Gate Bipolar Transistor，IGBT)，如果器件想获得较低的导通压降Von，则需要增强载流子的注入效率，但是这样会减小安全工作区(Safety Operating Area，SOA)，同时载流子浓度增大会导致器件开关切换时转换速度降低，且会产生拖尾电流，进而导致关断损耗增大。
发明内容
基于此，有必要提供一种具有低的导通压降和大的安全工作区的绝缘栅双极型晶体管。
一种绝缘栅双极型晶体管，包括第一导电类型的漂移区、所述漂移区上第二导电类型的体区，所述体区内的阴极第一导电类型区和阴极第二导电类型区，所述漂移区上的阳极第二导电类型区，第一导电类型和第二导电类型为相反的导电类型；还包括设于所述漂移区上的阳极第一导电类型区，所述阳极第一导电类型区包括第一区和第二区，所述阳极第二导电类型区包括第三区和第四区，所述第一区的掺杂浓度小于所述第二区，所述第三区的掺杂浓度小于所述第四区，所述第三区设于所述第四区和所述体区之间，所述第一区设于所述第四区下方，所述第二区设于所述第三区下方、且位于所述第一区和所述体区之间。
在其中一个实施例中，还包括第二导电类型的衬底和所述衬底上的埋氧层，所述漂移区设于所述埋氧层上。
在其中一个实施例中，还包括设于所述体区和阳极第二导电类型区之间的场氧层。
在其中一个实施例中，所述第三区距体区的距离小于所述第四区距体区的距离。
在其中一个实施例中，所述第二区距体区的距离小于所述第一区距体区的距离。
在其中一个实施例中，所述体区的掺杂浓度比所述阴极第二导电类型区的掺杂浓度低一个数量级。
在其中一个实施例中，所述第一导电类型是N型，所述第二导电类型是P型。
在其中一个实施例中，还包括第一导电类型的缓冲层，所述阳极第一导电类型区和阳极第二导电类型区设于所述缓冲层内。
在其中一个实施例中，所述缓冲层的掺杂浓度比所述第二区的掺杂浓度低一个数量级、比所述第一区的掺杂浓度高一个数量级。
在其中一个实施例中，所述绝缘栅双极型晶体管等效于具有第一三极管和第二三极管；所述第一三极管的集电极包括所述体区，基极包括所述漂移区、缓冲层及第一区，发射极包括所述第四区；所述第二三极管的集电极包括所述体区，基极包括所述漂移区、缓冲层及第二区，发射极包括所述第三区。
上述绝缘栅双极型晶体管，阳极第二导电类型区划分成轻掺杂的第三区和重掺杂的第四区，并在阳极第二导电类型区下方设置阳极第一导电类型区，包括第四区下方轻掺杂的第一区和第三区下方重掺杂的第二区。由于新增了额外的第一区，当阳极从第四区注入第二导电类型载流子时，为了达到电荷平衡，第四区的第二导电类型载流子注入效率会增加；由于新增了额外的第二区并且设置了第三区，因为第二区的掺杂浓度高于第一区，第三区的第二导电类型载流子注入效率将低于第四区。上述绝缘栅双极型晶体管等效于具有两个三极管：第四区、第一区/漂移区、体区形成第一三极管，第三区、第二区/漂移区、体区形成第二三极管。(1)在阳极电压较小时(器件工作在线性电流区域)，第一导电类型载流子电流作为两个三极管的基极驱动电流，促使第二导电类型载流子从阳极的第三、四区注入第一、二区，注入的第二导电类型载流子由此形成两个三极管的发射极电流，由于第一区为轻掺杂的第一导电类型，因此发射极区需要贡献更多的第一导电类型载流子。当第一导电类型载流子电流流向集电极时，集电极区吸引更多的第二导电类型载流子注入。由于第二三极管的第二导电类型载流子注入效率低于第一三极管，阳极电流主要流过第一三极管。由于第一区第二导电类型载流子浓度较低，第四区的第二导电类型载流子注入效率高于传统结构，因而本发明结构的导通电压较低。(2)随着阳极电流电压的增大(器件工作在饱和电流区域)，第一三极管的空穴注入效率下降，更多的电流流过第二三极管，而第二三极管第二导电类型载流子注入效率较低，故器件的饱和电流得到抑制。综上所述，上述绝缘栅双极型晶体管能够在线性电流区域提高第二导电类型载流子注入效率，获得更低的导通压降；并且在饱和电流区域降低饱和电流，获得更大的安全工作区。
附图说明
为了更好地描述和说明这里公开的那些发明的实施例和/或示例，可以参考一幅或多幅附图。用于描述附图的附加细节或示例不应当被认为是对所公开的发明、目前描述的实施例和/或示例以及目前理解的这些发明的最佳模式中的任何一者的范围的限制。
图1是一实施例中绝缘栅双极型晶体管的剖面结构示意图；
图2是图1所示IGBT的等效电路图；
图3是本发明结构与传统结构的ICE-VCE(集电极发射极电流-集电极发射极电压)对比图。
具体实施方式
为了便于理解本发明，下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的首选实施例。但是，本发明可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本发明的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本发明。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
应当明白，当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本发明教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下面”和“在...下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本发明的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
这里参考作为本发明的理想实施例(和中间结构)的示意图的横截面图来描述发明的实施例。这样，可以预期由于例如制造技术和/或容差导致的从所示形状的变化。因此，本发明的实施例不应当局限于在此所示的区的特定形状，而是包括由于例如制造导致的形状偏差。例如，显示为矩形的注入区在其边缘通常具有圆的或弯曲特征和/或注入浓度梯度，而不是从注入区到非注入区的二元改变。同样，通过注入形成的埋藏区可导致该埋藏区和注入进行时所经过的表面之间的区中的一些注入。因此，图中显示的区实质上是示意性的，它们的形状并不意图显示器件的区的实际形状且并不意图限定本发明的范围。
本文所使用的半导体领域词汇为本领域技术人员常用的技术词汇，例如对于P型和N型杂质，为区分掺杂浓度，简易的将P+型代表重掺杂浓度的P型，P型代表中掺杂浓度的P型，P-型代表轻掺杂浓度的P型，N+型代表重掺杂浓度的N型，N型代表中掺杂浓度的N型，N-型代表轻掺杂浓度的N型。
IGBT要想获得低的导通压降和大的安全工作区，需要少数载流子的阳极注入在通电状态下增强，在关断或短路切换时减弱或理想地消除。这已经在DB-IGBT(Dynamic N-Buffer Insulated Gate Bipolar Transistor，动态N缓冲绝缘栅双极型晶体管)和DT-IGBT(Double Trench Insulated Gate Bipolar Transistor，双沟槽绝缘栅双极晶体管)中实现。然而，这两种器件都需要两个栅极，在关断过程和短路切换过程中，需要对两个栅极的开关信号的时间相位进行精确控制，以获得理想的性能，这使得驱动电路变得复杂。
图1是一实施例中绝缘栅双极型晶体管的剖面结构示意图，包括漂移区3、体区4、阴极第一导电类型区6、阴极第二导电类型区5、阳极第一导电类型区(包括第一区17和第二区16)及阳极第二导电类型区(包括第三区15和第四区8)。
第二导电类型的体区4设于第一导电类型的漂移区3上，阴极第一导电类型区6和阴极第二导电类型区5设于体区4中，阳极第一导电类型区和阳极第二导电类型区设于漂移区3上。在图1所示的实施例中，第一导电类型是N型，第二导电类型是P型；在另一个实施例中，也可以第一导电类型是P型，第二导电类型是N型。
第一区17的掺杂浓度小于第二区16，第三区15的掺杂浓度小于第四区8，第三区15设于第四区8和体区4之间，第一区17设于第四区8下方，第二区16设于第三区15下方、且位于第一区17和体区4之间。在图1所示的实施例中，第三区15距体区4的距离小于第四区8距体区4的距离，第二区16距体区的距离小于第一区17距体区4的距离。
在图1所示的实施例中，IGBT还包括第一导电类型的缓冲层7，阳极第一导电类型区和阳极第二导电类型区设于缓冲层7内。在一个实施例中，缓冲层7的掺杂浓度小于第二区16的掺杂浓度、大于第一区17的掺杂浓度；进一步地，缓冲层7的掺杂浓度比第二区16的掺杂浓度低一个数量级，比第一区17的掺杂浓度高一个数量级。在图1所示的实施例中，缓冲层7是N型缓冲层。
在图1所示的实施例中，体区4的掺杂浓度低于阴极第二导电类型区5的掺杂浓度；进一步地，体区4的掺杂浓度比阴极第二导电类型区5的掺杂浓度低一个数量级。
在图1所示的实施例中，第一区17是N-区，第二区16是N+区，第三区15是P-区，第四区8是P+区，体区4是P型体区，阴极第一导电类型区6是N+区，阴极第二导电类型区5是P+区。
图2是图1所示IGBT的等效电路图。绝缘栅双极型晶体管等效于具有第一三极管PNP1和第二三极管PNP2。第一三极管PNP1的集电极包括体区4，基极包括漂移区3、缓冲层7及第一区17，发射极包括第四区8。第二三极管PNP2的集电极包括体区4，基极包括漂移区3、缓冲层7及第二区16，发射极包括第三区15。
上述绝缘栅双极型晶体管，阳极第二导电类型区划分成轻掺杂的第三区15和重掺杂的第四区8，并在阳极第二导电类型区下方设置阳极第一导电类型区，包括第四区8下方轻掺杂的第一区17和第三区15下方重掺杂的第二区16。由于新增了额外的第一区17，当阳极从第四区8注入空穴时，为了达到电荷平衡，第四区8的空穴注入效率会增加；由于新增了额外的第二区16并且设置了第三区15，再加上第二区16的掺杂浓度高于第一区17，因此第三区15的空穴注入效率将低于第四区8。上述绝缘栅双极型晶体管等效于具有两个三极管：第四区8、第一区17/缓冲层7/漂移区3、体区4形成第一三极管PNP1，第三区15、第二区16/缓冲层7/漂移区3、体区4形成第二三极管PNP2。(1)在阳极电压较小时(器件工作在线性电流区域)，电子电流作为两个三极管的基极驱动电流，促使空穴从阳极的第三区15和第四区8注入第一区17和第二区16，注入的空穴由此形成两个三极管的发射极电流。由于第一区17为N-区，因此发射极区需要贡献更多的电子。当电子电流流向集电极时，集电极区吸引更多的空穴注入。由于第二三极管PNP2的注入效率低于第一三极管PNP1，阳极电流主要流过第一三极管PNP1。由于第一区17空穴浓度较低，第四区8的空穴注入效率高于传统结构，因而本发明结构的导通电压较低。(2)随着阳极电流电压的增大(器件工作在饱和电流区域)，第一三极管PNP1的空穴注入效率下降，更多的电流流过第二三极管PNP2，而第二三极管PNP2空穴注入效率较低，故器件的饱和电流得到抑制。如图3所示，本发明结构的线性电流大于传统结构的线性电流，饱和电流小于传统结构的饱和电流。综上所述，上述绝缘栅双极型晶体管能够在线性电流区域提高空穴注入效率，获得更低的导通压降；并且在饱和电流区域降低饱和电流，获得更大的安全工作区。
在图1所示的实施例中，绝缘栅双极型晶体管还包括第二导电类型的衬底1和衬底1上的埋氧层BOX，漂移区3设于埋氧层BOX上。具体地，衬底1可以是P型衬底。
在图1所示的实施例中，绝缘栅双极型晶体管还包括设于体区4和阳极第二导电类型区之间的场氧层9。具体地，场氧层9的一侧可以延伸至第三区15边缘和第二区16边缘，并覆盖一部分缓冲层7。
在图1所示的实施例中，绝缘栅双极型晶体管还包括第一多晶硅10和第二多晶硅11。第二多晶硅11设于场氧层9上，第一多晶硅10从场氧层9上向阴极第一导电类型区6延伸。在图1所示的实施例中，第一多晶硅10位于场氧层9之外的部分还在下方设有介电层(图1未标示)，即场氧层9与阴极第一导电类型区6之间的区域在漂移区3和体区4上设有介电层，介电层上设有第一多晶硅10。
在图1所示的实施例中，绝缘栅双极型晶体管表面还设有介质层14。介质层14上设有第一电极12a和第二电极13a，第一电极12a通过第一接触孔12内填充的导电材料(例如金属或合金)电连接并引出阴极第一导电类型区6和阴极第二导电类型区5。第二电极13a通过一接触孔13电连接并引出第二多晶硅11，通过另一接触孔13电连接并引出第三区15和第四区8。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (10)

1.一种绝缘栅双极型晶体管，包括第一导电类型的漂移区、所述漂移区上第二导电类型的体区，所述体区内的阴极第一导电类型区和阴极第二导电类型区，所述漂移区上的阳极第二导电类型区，第一导电类型和第二导电类型为相反的导电类型；其特征在于，还包括设于所述漂移区上的阳极第一导电类型区，所述阳极第一导电类型区包括第一区和第二区，所述阳极第二导电类型区包括第三区和第四区，所述第一区的掺杂浓度小于所述第二区，所述第三区的掺杂浓度小于所述第四区，所述第三区设于所述第四区和所述体区之间，所述第一区设于所述第四区下方，所述第二区设于所述第三区下方、且位于所述第一区和所述体区之间。
2.根据权利要求1所述的绝缘栅双极型晶体管，其特征在于，还包括第二导电类型的衬底和所述衬底上的埋氧层，所述漂移区设于所述埋氧层上。
3.根据权利要求1所述的绝缘栅双极型晶体管，其特征在于，还包括设于所述体区和阳极第二导电类型区之间的场氧层。
4.根据权利要求1所述的绝缘栅双极型晶体管，其特征在于，所述第三区距体区的距离小于所述第四区距体区的距离。
5.根据权利要求1所述的绝缘栅双极型晶体管，其特征在于，所述第二区距体区的距离小于所述第一区距体区的距离。
6.根据权利要求1所述的绝缘栅双极型晶体管，其特征在于，所述体区的掺杂浓度比所述阴极第二导电类型区的掺杂浓度低一个数量级。
7.根据权利要求1-6中任一项所述的绝缘栅双极型晶体管，其特征在于，所述第一导电类型是N型，所述第二导电类型是P型。
8.根据权利要求7所述的绝缘栅双极型晶体管，其特征在于，还包括第一导电类型的缓冲层，所述阳极第一导电类型区和阳极第二导电类型区设于所述缓冲层内。
9.根据权利要求8所述的绝缘栅双极型晶体管，其特征在于，所述缓冲层的掺杂浓度比所述第二区的掺杂浓度低一个数量级、比所述第一区的掺杂浓度高一个数量级。
10.根据权利要求8或9所述的绝缘栅双极型晶体管，其特征在于，所述绝缘栅双极型晶体管等效于具有第一三极管和第二三极管；
所述第一三极管的集电极包括所述体区，基极包括所述漂移区、缓冲层及第一区，发射极包括所述第四区；
所述第二三极管的集电极包括所述体区，基极包括所述漂移区、缓冲层及第二区，发射极包括所述第三区。
CN201911065246.6A 2019-11-04 2019-11-04 绝缘栅双极型晶体管 Active CN112768517B (zh)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CN201911065246.6A CN112768517B (zh) 2019-11-04 2019-11-04 绝缘栅双极型晶体管
EP20884449.8A EP3989292A4 (en) 2019-11-04 2020-08-26 BIPOLAR TRANSISTOR WITH ISOLATED GATE
US17/762,212 US20220376094A1 (en) 2019-11-04 2020-08-26 Insulated gate bipolar transistor
PCT/CN2020/111385 WO2021088478A1 (zh) 2019-11-04 2020-08-26 绝缘栅双极型晶体管

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201911065246.6A CN112768517B (zh) 2019-11-04 2019-11-04 绝缘栅双极型晶体管

Publications (2)

Publication Number Publication Date
CN112768517A true CN112768517A (zh) 2021-05-07
CN112768517B CN112768517B (zh) 2022-06-21

Family

ID=75692268

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201911065246.6A Active CN112768517B (zh) 2019-11-04 2019-11-04 绝缘栅双极型晶体管

Country Status (4)

Country Link
US (1) US20220376094A1 (zh)
EP (1) EP3989292A4 (zh)
CN (1) CN112768517B (zh)
WO (1) WO2021088478A1 (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113690310A (zh) * 2021-07-14 2021-11-23 广东美的白色家电技术创新中心有限公司 Ligbt、制备方法、智能功率模块、驱动电路及电器
CN113690309A (zh) * 2021-07-14 2021-11-23 广东美的白色家电技术创新中心有限公司 Ligbt、制备方法、智能功率模块、驱动电路及电器

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120161201A1 (en) * 2010-12-23 2012-06-28 Force Mos Technology Co., Ltd. Fast switching lateral insulated gate bipolar transistor (ligbt) with trenched contacts
CN102760761A (zh) * 2012-06-30 2012-10-31 东南大学 一种抗闩锁n型绝缘体上硅横向绝缘栅双极型晶体管
US9397090B1 (en) * 2015-04-10 2016-07-19 Macronix International Co., Ltd. Semiconductor device
CN110190113A (zh) * 2019-05-16 2019-08-30 东南大学 一种消除负阻效应的阳极短路型横向绝缘栅双极型晶体管

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9627517B2 (en) * 2013-02-07 2017-04-18 Infineon Technologies Ag Bipolar semiconductor switch and a manufacturing method therefor
US9166005B2 (en) * 2013-03-01 2015-10-20 Infineon Technologies Austria Ag Semiconductor device with charge compensation structure
US9647065B2 (en) * 2013-10-17 2017-05-09 Taiwan Semiconductor Manufacturing Company, Ltd. Bipolar transistor structure having split collector region and method of making the same
CN103779404B (zh) * 2014-01-24 2016-03-30 东南大学 P沟道注入效率增强型绝缘栅双极型晶体管
CN108447904B (zh) * 2018-03-14 2020-09-29 电子科技大学 一种横向igbt的制造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120161201A1 (en) * 2010-12-23 2012-06-28 Force Mos Technology Co., Ltd. Fast switching lateral insulated gate bipolar transistor (ligbt) with trenched contacts
CN102760761A (zh) * 2012-06-30 2012-10-31 东南大学 一种抗闩锁n型绝缘体上硅横向绝缘栅双极型晶体管
US9397090B1 (en) * 2015-04-10 2016-07-19 Macronix International Co., Ltd. Semiconductor device
CN110190113A (zh) * 2019-05-16 2019-08-30 东南大学 一种消除负阻效应的阳极短路型横向绝缘栅双极型晶体管

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
HUAN HU ET AL: ""A Novel Low Turn-Off Loss and Snapback-Free Reverse-Conducting SOI-LIGBT With Integrated Polysilicon Diodes"", 《IEEE TRANSACTIONS ON ELECTRON DEVICES》 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113690310A (zh) * 2021-07-14 2021-11-23 广东美的白色家电技术创新中心有限公司 Ligbt、制备方法、智能功率模块、驱动电路及电器
CN113690309A (zh) * 2021-07-14 2021-11-23 广东美的白色家电技术创新中心有限公司 Ligbt、制备方法、智能功率模块、驱动电路及电器

Also Published As

Publication number Publication date
CN112768517B (zh) 2022-06-21
EP3989292A4 (en) 2023-07-19
WO2021088478A1 (zh) 2021-05-14
US20220376094A1 (en) 2022-11-24
EP3989292A1 (en) 2022-04-27

Similar Documents

Publication Publication Date Title
US9299695B2 (en) Semiconductor device
US20150187877A1 (en) Power semiconductor device
CN105789269A (zh) 沟槽绝缘栅双极型晶体管及其制备方法
WO2009088452A1 (en) Improved sawtooth electric field drift region structure for power semiconductor devices
US11081574B2 (en) IGBT power device
US9263560B2 (en) Power semiconductor device having reduced gate-collector capacitance
CN108365007B (zh) 绝缘栅双极型晶体管
US20170256614A1 (en) Vertical insulated gate turn-off thyristor with intermediate p+ layer in p-base
CN111834449B (zh) 一种具有背面双mos结构的快速关断rc-igbt器件
CN112768517B (zh) 绝缘栅双极型晶体管
CN112038401A (zh) 一种绝缘栅双极性晶体管结构及其制备方法
CN115832039A (zh) 一种逆导型igbt器件
JPH10125896A (ja) 絶縁ゲート型サイリスタ
Zhang et al. Optimization of ${V} _ {\text {CE}} $ Plateau for Deep-Oxide Trench SOI Lateral IGBT During Inductive Load Turn-OFF
CN117038718A (zh) 一种具有三栅结构的复合型rc-ligbt器件
US20150187922A1 (en) Power semiconductor device
CN108122962B (zh) 一种绝缘栅双极型晶体管
US20150171198A1 (en) Power semiconductor device
JP3163815B2 (ja) 半導体装置
CN111430454B (zh) 一种低饱和电流的绝缘体上硅横向绝缘栅双极型晶体管
US9209287B2 (en) Power semiconductor device
CN112018172A (zh) 绝缘栅双极型晶体管、智能功率器件及电子产品
US20150144993A1 (en) Power semiconductor device
US20150187869A1 (en) Power semiconductor device
CN110610986A (zh) 一种利用结终端集成横向续流二极管的rc-igbt器件

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant