CN112750911A - LDMOS with controllable three-dimensional electric field and preparation method thereof - Google Patents
LDMOS with controllable three-dimensional electric field and preparation method thereof Download PDFInfo
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- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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Abstract
The invention discloses a three-dimensional electric field controllable LDMOS (laterally diffused metal oxide semiconductor) which comprises a semiconductor substrate, a buried layer and an active region, wherein the active region comprises a semiconductor drain region, a strip-shaped semiconductor drift region and a semiconductor well region, the semiconductor drain region is positioned above a step at one side of the strip-shaped semiconductor drift region, and the semiconductor well region is positioned at the other side of the strip-shaped semiconductor drift region; the three-way control electrode is positioned on two sides and the surface of the strip-shaped semiconductor drift region, and a dielectric layer is arranged between the three-way control electrode and the strip-shaped semiconductor drift region; and the three gate electrodes are positioned at the two sides and the top of the channel region to form a three-gate structure. The invention also discloses a preparation method of the LDMOS with the controllable three-dimensional electric field. The three-way control electrode is arranged, so that higher breakdown voltage can be obtained, and the on-resistance of the LDMOS is effectively reduced; the three-gate electrode is arranged, so that good channel control capability is provided, the leakage current of the device during closing is reduced, the short channel effect is inhibited, and the hysteresis of the threshold voltage is greatly reduced.
Description
Technical Field
The invention relates to a semiconductor power device, in particular to a three-dimensional electric field controllable LDMOS and a preparation method thereof.
Background
The semiconductor power device is the core of electric energy conversion and circuit control in a power integrated circuit, and along with the development of the power integrated circuit, the performance of the semiconductor power device needs to be continuously improved to meet the requirements of high withstand voltage, low on resistance, low power consumption and the like. The lateral double-diffused metal oxide semiconductor (LDMOS) is widely applied to semiconductor power devices in the fields of 5G base stations and the like, needs to provide high breakdown voltage and low on-resistance to reduce power consumption, has a good sub-threshold characteristic and avoids a short channel effect.
In order to modulate the electric field distribution in the LDMOS drift region and reduce the junction electric field peak value, the field plate structure is widely researched and applied in the design of the LDMOS as a junction termination technology. Aharma et al proposed Integrated 85V Rated compatible LDMOS Devices Utilizing plated Field Plate Structures for Best-in-Class Performance in Network Communication Applications in a journal of IEEE ISPSD in 2013, relating to a surface patterning Field Plate technology, combining a common Field Plate and a floating Field Plate, wherein developed N-type and P-type LDMOS show good working characteristics; the field plates are mainly manufactured on the surface of the device, only the surface electric field distribution is modulated, and the drift region cannot be modulated in all directions to improve the breakdown voltage and reduce the on-resistance.
Disclosure of Invention
The purpose of the invention is as follows: in view of the above problems, the present invention aims to provide a three-directional electric field controllable LDMOS device, in which three-directional control electrodes are designed on two sides and a surface of a drift region, and three gate electrodes are formed on two sides and a surface of a channel region, thereby preparing an LDMOS device with an electric field controllable, high withstand voltage, and low on-resistance.
The technical scheme is as follows: the invention relates to a three-dimensional electric field controllable LDMOS, which comprises a semiconductor substrate positioned at the bottom, a buried layer positioned above the semiconductor substrate, and an active region positioned above the buried layer, wherein the active region comprises a semiconductor drain region, a strip-shaped semiconductor drift region and a semiconductor well region;
the three-way control electrode is positioned on two sides and the surface of the strip-shaped semiconductor drift region, and a dielectric layer is arranged between the three-way control electrode and the strip-shaped semiconductor drift region;
and the triple gate electrodes are positioned on two sides and the top of the channel region to form a triple gate structure, and a dielectric layer is arranged between the triple gate electrodes and the channel region.
The three-way control electrode comprises a plurality of metal control electrodes which are uniformly distributed above the strip-shaped semiconductor drift region.
The distance between the metal control electrodes is 0.5-5 mu m, the width of each metal control electrode is 0.5-2 mu m, and the depth of two sides of each three-way control electrode is the same as the thickness of the strip-shaped semiconductor drift region.
The semiconductor well region comprises a semiconductor source region, a semiconductor body contact region and a channel region, the semiconductor body contact region is located on the outer side, the semiconductor source region is located on the inner side and close to the strip-shaped semiconductor drift region, and the channel region is located between the strip-shaped semiconductor drift region and the semiconductor source region.
The three-way electric field controllable LDMOS further comprises drain metal and source metal, wherein the drain metal and the source metal are located above the active region, the drain metal is in contact with the semiconductor drain region, and the source metal is in contact with the semiconductor source region and the semiconductor body contact region.
The voltage on each control electrode of the three-way control electrode is controlled by an external control circuit.
The thickness of the dielectric layer is 20-200 nm, and the dielectric layer is made of a high-dielectric-constant dielectric material with a dielectric constant higher than that of silicon.
The invention relates to a preparation method of a three-dimensional electric field controllable LDMOS, which comprises the following steps:
(1) forming an active area structure on a substrate;
(2) injecting P-type impurities into the active region to form a semiconductor well region;
(3) injecting P-type impurities into the semiconductor well region to form a semiconductor body contact region;
(4) injecting N-type impurities into the semiconductor well region and the N-type top layer silicon to form an N-type semiconductor source region and a semiconductor drain region;
(5) filling a dielectric material into the grooves on two sides of the active region through deposition, and completely covering the surface of the whole device;
(6) adopting chemical mechanical polishing to enable the surface of the dielectric material to be flat and have a certain thickness;
(7) etching a contact hole, forming a plurality of grid contact holes and a plurality of three-way control electrode contact holes in the dielectric layer, and etching a dielectric material at a source end and a drain end by utilizing a mask to form a source drain contact hole;
(8) depositing metal in the contact hole, and etching the metal to form a multi-directional control electrode, a three-gate electrode, a source electrode and a drain electrode;
(9) and leading out wires on the surface and two sides of the control electrode for controlling the connection of the circuit.
The step (1) adopts photoetching and dry etching processes.
And (3) adopting an ion implantation process in the steps (2), (3) and (4).
And the step (7) adopts photoetching and etching processes.
And (7) the depth of the grid contact hole and the three-way control electrode contact hole is consistent with the thickness of the active region, and the depth of the source drain contact hole is consistent with the thickness of the surface dielectric material.
Has the advantages that: compared with the prior art, the invention has the following remarkable advantages:
1. three-way control electrodes are arranged on two sides and the surface of the drift region, and the three-way control electrodes are accurately controlled to form uniform electric field distribution so as to obtain higher breakdown voltage; the three-way control electrode forms a conducting layer with high carrier concentration on the surface and two sides of the drift region, so that the on-resistance of the LDMOS is effectively reduced;
2. three gate electrodes are formed on two side surfaces and the surface of the channel region, so that good channel control capability is provided, the leakage current of the device during closing is reduced, the short channel effect is inhibited, the hysteresis of threshold voltage is greatly reduced, and the transconductance is obviously improved;
3. dielectric materials with high dielectric constants are adopted as a field dielectric and a gate dielectric to further assist the depletion of the drift region, so that the withstand voltage is improved and the on-resistance is reduced;
4. the high-voltage high-frequency power supply has the advantages of controllable electric field, high voltage resistance and low on-resistance, and is suitable for the high-voltage high-frequency field.
Drawings
FIG. 1 is a schematic diagram of a three-dimensional electric field controllable LDMOS structure according to the present invention;
FIG. 2 is a schematic diagram of the device structure after fabrication of the active region;
FIG. 3 is a cross-sectional view of the LDMOS of the present invention taken along line A1;
FIG. 4 is a cross-sectional view of the LDMOS of the present invention taken along line A2, where line A2 is located directly above the middle of the active region;
FIG. 5 is a cross-sectional view of the LDMOS of the present invention taken along line B1, where line B1 is located directly above the semiconductor body contact regions;
FIG. 6 is a cross-sectional view of the LDMOS of the present invention taken along line B2, wherein line B2 is located directly above the semiconductor source region;
FIG. 7 is a cross-sectional view of the LDMOS of the present invention taken along line B3, where line B3 is directly above the tri-gate electrode;
FIG. 8 is a cross-sectional view of an LDMOS device of the present invention taken along line B4, wherein line B4 is located directly above a longitudinal junction of a semiconductor well region and a dielectric layer;
FIG. 9 is a cross-sectional view of the LDMOS of the present invention taken along line B5, where line B5 is located directly above the control electrode;
FIG. 10 is a cross-sectional view of the LDMOS of the present invention taken along line B6;
FIG. 11 is a cross-sectional view of the LDMOS of the present invention taken along line B7;
fig. 12 is a cross-sectional view of the LDMOS of the present invention taken along line a2 after forming a channel region and a conducting layer;
FIG. 13 is a cross-sectional view of the LDMOS device of the present invention after the formation of the channel region, taken along line B3;
fig. 14 is a cross-sectional view of the LDMOS of the present invention taken along line B5 after forming a conductive layer.
Detailed Description
Referring to fig. 1, the LDMOS with a three-dimensional electric field controllable in this embodiment includes a semiconductor substrate 1, a buried layer 2 and an active region 3, where the semiconductor substrate 1 is located at the bottom layer, the buried layer 2 is located above the semiconductor substrate 1, and the active region 3 is located above the buried layer 2. As shown in fig. 2, the active region 3 includes a semiconductor drain region 4, a strip-shaped semiconductor drift region 5, and a semiconductor well region 6, the semiconductor drain region 4 is located above a step on one side of the strip-shaped semiconductor drift region 5, and the semiconductor well region 6 is located on the other side of the strip-shaped semiconductor drift region 5. The semiconductor well region 6 comprises a semiconductor source region 8, a semiconductor body contact region 7 and a channel region 14, wherein the semiconductor body contact region 7 is located at the outer side, the semiconductor source region 8 is located at the inner side and is close to the strip-shaped semiconductor drift region 5, and the channel region 14 is located between the strip-shaped semiconductor drift region 5 and the semiconductor source region 8. FIGS. 3-14 are schematic cross-sectional views of the LDMOS along the various section lines of FIG. 1.
The LDMOS further includes three-way control electrodes 13 and three-way gate electrodes 10, wherein the three-way control electrodes 13 are located on two sides and on the surface of the strip-shaped semiconductor drift region 5. The three-way control electrode 13 comprises a plurality of metal control electrodes which are uniformly distributed above the strip-shaped semiconductor drift region 5. In this embodiment, 4 metal control electrodes are taken as an example. The number and width of the metal control electrodes are determined according to design requirements and the size of the device, the voltage on each metal control electrode is controlled by an external control circuit, and the external control circuit controls a plurality of electrodes to form a uniform electric field simultaneously. Conductive layers 15 are formed on three sides of the drift region by three-way control electrodes 13. The distance between the metal control electrodes is 0.5-5 micrometers, the width of a single metal control electrode is 0.5-2 micrometers, and the depth of two sides of the three-way control electrode 13 is the same as the thickness of the strip-shaped semiconductor drift region 5.
The triple-gate electrode 10 is positioned on two sides and above the channel region 14 to form a triple-gate structure, and a dielectric layer 9 is arranged between the triple-gate electrode 10 and the channel region 14. The depth of the gate electrode on both sides of the channel region 14 is the same as the thickness of the dielectric layer 9 of the active region 3. A dielectric layer 9 is arranged between the three-way control electrode 13 and the strip-shaped semiconductor drift region 5. The thickness of the dielectric layer 9 is 20 nm to 200 nm. The dielectric layer 9 is made of a dielectric material with a dielectric constant higher than that of silicon, and can effectively improve the leakage current of the grid electrode of the device when being used as a grid dielectric; the high-dielectric constant dielectric material can modulate the potential and electric field distribution of the drift region of the device from the surface and the side surface to obtain higher breakdown voltage as a field medium, and simultaneously the auxiliary depletion effect of the high-dielectric constant dielectric material on the drift region can improve the doping concentration of the drift region to reduce the on-resistance of the device.
A drain metal 11 and a source metal 12 are disposed above the active region 3, the drain metal 11 contacting the semiconductor drain region 4, and the source metal 12 contacting the semiconductor source region 8 and the semiconductor body contact region 7.
In the LDMOS field effect transistor of this embodiment, the N-type drift region is taken as an example, and the high-dielectric-constant medium covers both sides and the surface of the active region 3, so as to modulate the active region 3 from three directions. Meanwhile, the three-way control electrode 13 is arranged in the drift region, a uniform control electric field is generated in the strip-shaped semiconductor drift region 5, and the three-grid is used for replacing an original surface grid, so that the channel control capability is better, and the leakage current of the device during closing is reduced. In addition, changing the commonly used silicon oxide gate dielectric into a high-k gate dielectric can have a thicker physical oxide layer and improve the problem of gate leakage current. The strip-shaped semiconductor drift region 5 of the transverse double-diffusion power device is an N-type drift region. The LDMOS device is formed on a silicon-on-insulator (SOI) substrate, the thickness of top silicon of the SOI substrate is 1-5 microns, and the concentration range of the top silicon on the SOI substrate is 1014Atom/cm3-1018Atom/cm3。
When high voltage is applied to the triple-gate electrode 10 for conduction, an external control circuit is operated by an electric field, a conducting layer with high carrier concentration is formed in the drift region, and the drift region is formed by drift regions in three directions together, so that the area of the drift region is increased, and the on-resistance of the LDMOS is effectively reduced. And with the reduction of the design line width, the control electric field formed by the control electrode is more and more uniform, the on-resistance is also greatly reduced, and the power density is higher.
The preparation method of the three-dimensional electric field controllable LDMOS, provided by the embodiment, comprises the following steps:
(1) and forming an active region 3 structure on the top silicon of the SOI substrate by utilizing photoetching and dry etching processes. The width range of the strip-shaped semiconductor drift region 5 of the active region 3 is 0.5-2 microns, and the width range of the grooves on two sides of the semiconductor drift region is 0.5-1 micron.
(2) P-type impurities are implanted on the active region 3 by an ion implantation process to form a semiconductor well region 6.
(3) Injecting P-type impurities into the semiconductor well region 6 by adopting an ion injection process to form a semiconductor body contact region 7;
(4) and injecting N-type impurities into the semiconductor well region 6 and the N-type top layer silicon by adopting an ion injection process to form an N-type semiconductor source region 8 and a semiconductor drain region 4, and forming a channel region by an annealing process.
(5) Depositing and filling a dielectric material into two sides of the strip-shaped active region 3 by adopting vacuum evaporation or magnetron sputtering, and completely covering the surface of the whole device;
(6) and then, grinding and polishing to enable the dielectric material on the surface to have a certain thickness in the range of 0.1-1 micron.
(7) A plurality of gate contact holes and a plurality of three-way control electrode contact holes are formed in the dielectric layer 9 through photoetching and etching processes, and the depth of the holes is consistent with the thickness of the active region 3. And etching the dielectric material at the source end and the drain end by using the mask to form a source drain contact hole, wherein the depth of the hole is consistent with the thickness of the surface dielectric material.
(8) And depositing metal into the contact hole, and etching the metal to form a three-dimensional control metal electrode, a metal gate electrode, a metal source electrode and a metal drain electrode. Wherein the metal gate electrode surrounds the channel region 14 from three directions of the surface and two sides to form a tri-gate structure. The source metal 12 forms a metal source electrode in contact with the semiconductor source region 8 and the body contact region 7; the drain metal 11 forms a metal drain electrode across and in contact with the semiconductor drain region 4. A plurality of control electrodes are uniformly arranged above the drift region 5.
The channel region 14 is formed by inverting the p-well region into n-type after increasing the gate voltage, as shown in fig. 12 and 13, and its position and size are not fixed; the surface and both sides of the drift region are affected by a plurality of three-way control electrodes 13 uniformly arranged, and a conductive layer 15 is formed on the surface and both sides, as shown in fig. 12 and 14.
(9) After the control electrode metal is formed, processing is continued to lead out a lead wire to an external control IC circuit for controlling the operation of the electrode.
The embodiments shown above are only examples of the LDMOS of the N-type drift region, and can also be applied to the LDMOS of the P-type drift region, and can also be applied to the lateral IGBT device.
Claims (10)
1. The LDMOS with the controllable three-dimensional electric field is characterized by comprising a semiconductor substrate (1) positioned at the bottom, a buried layer (2) positioned above the semiconductor substrate (1), and an active region (3) positioned above the buried layer (2), wherein the active region (3) comprises a semiconductor drain region (4), a strip-shaped semiconductor drift region (5) and a semiconductor well region (6), the semiconductor drain region (4) is positioned above a step on one side of the strip-shaped semiconductor drift region (5), and the semiconductor well region (6) is positioned on the other side of the strip-shaped semiconductor drift region (5);
the three-way control electrode (13) is positioned on two sides and the surface of the strip-shaped semiconductor drift region (5), and a dielectric layer (9) is arranged between the three-way control electrode (13) and the strip-shaped semiconductor drift region (5);
and the triple gate electrode (10) is positioned on two sides and the top of the channel region (14) to form a triple gate structure, and a dielectric layer (9) is arranged between the triple gate electrode (10) and the channel region (14).
2. The three-way electric field controllable LDMOS of claim 1, wherein said three-way control electrode (13) comprises a plurality of metal control electrodes evenly distributed over a strip shaped semiconductor drift region (5).
3. The LDMOS of claim 2, wherein the spacing between the metal control electrodes is 0.5-5 μm, the width of a single metal control electrode is 0.5-2 μm, and the depth of the two sides of the three-way control electrode (13) is the same as the thickness of the strip-shaped semiconductor drift region (5).
4. The three-dimensional electric field controllable LDMOS as claimed in claim 1, wherein said semiconductor well region (6) comprises a semiconductor source region (8), a semiconductor body contact region (7) and a channel region (14), said semiconductor body contact region (7) being located at an outer side, said semiconductor source region (8) being located at an inner side, close to the strip-shaped semiconductor drift region (5), said channel region (14) being located between the strip-shaped semiconductor drift region (5) and the semiconductor source region (8).
5. The three-dimensional electric field controllable LDMOS of claim 1, further comprising a drain metal (11) and a source metal (12) located above the active region (3), the drain metal (11) being in contact with the semiconductor drain region (4), the source metal (12) being in contact with the semiconductor source region (8) and the semiconductor body contact region (7).
6. A three-way electric field controllable LDMOS as claimed in any one of claims 1 to 3, wherein the voltage on each metal control electrode of said three-way control electrode (13) is controlled by an external control circuit.
7. The LDMOS of claim 1, wherein the dielectric layer (9) is 20-200 nm thick, and the dielectric layer (9) is made of a high-k dielectric material with a dielectric constant higher than that of silicon.
8. A method for preparing an LDMOS with a controllable three-dimensional electric field is characterized by comprising the following steps:
(1) forming an active region (3) structure on a semiconductor substrate (1);
(2) injecting P-type impurities on the active region (3) to form a semiconductor well region (6);
(3) injecting P-type impurities into the semiconductor well region (6) to form a semiconductor body contact region (7);
(4) injecting N-type impurities into the semiconductor well region (6) and the N-type top layer silicon to form an N-type semiconductor source region (8) and a semiconductor drain region (4);
(5) filling a dielectric material into the grooves on the two sides of the active region (3) through deposition, and completely covering the surface of the active region (3);
(6) the surface of the dielectric layer (9) is flattened by adopting chemical mechanical polishing and has a certain thickness;
(7) etching contact holes, forming a plurality of grid contact holes and a plurality of three-way control electrode contact holes in the dielectric layer (9), and etching a dielectric material at a source end and a drain end by utilizing a mask to form source and drain contact holes;
(8) depositing metal in the contact hole, and etching the metal to form a multi-directional control electrode (13), a three-gate electrode (10), a source electrode and a drain electrode;
(9) and leading out wires on the surface and two sides of the control electrode for controlling the connection of the circuit.
9. The method for preparing the LDMOS in accordance with claim 8, wherein the step (1) adopts a photolithography and dry etching process, the steps (2), (3) and (4) adopt an ion implantation process, and the step (7) adopts a photolithography and etching process.
10. The method for preparing the LDMOS with the controllable three-way electric field according to claim 8, wherein in the step (7), the depth of the gate contact hole and the three-way control electrode contact hole is consistent with the thickness of the active region (3), and the depth of the source and drain contact holes is consistent with the thickness of the surface dielectric material.
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