CN112701056A - 半导体结构的制造方法 - Google Patents

半导体结构的制造方法 Download PDF

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CN112701056A
CN112701056A CN201911257594.3A CN201911257594A CN112701056A CN 112701056 A CN112701056 A CN 112701056A CN 201911257594 A CN201911257594 A CN 201911257594A CN 112701056 A CN112701056 A CN 112701056A
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conductive
layer
mask structures
mask
conductive pads
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CN112701056B (zh
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丘世仰
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Nanya Technology Corp
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Abstract

本发明公开了一种半导体结构的制造方法，包含形成前驱结构，前驱结构包含多个导电垫位于基板上，蚀刻停止层位于导电垫之间，以及凸块下金属层，位于导电垫及蚀刻停止层之上。形成多个掩模结构位于凸块下金属层之上，以及多个开口位于掩模结构之间。每个掩模结构位于导电垫的其中一个之上，且开口暴露出凸块下金属层的第一部分。形成支撑层于开口中。去除掩模结构，以形成多个空腔暴露出凸块下金属层的第二部分。形成导电材料于空腔中。去除支撑层。去除凸块下金属层的第一部分，以形成多个彼此分离的导电凸块。本发明的半导体结构可以减小导电凸块和其他半导体结构之间的接合面积，可以在低温和低负载力(load force)下进行凸块接合。

Description

半导体结构的制造方法
技术领域
本发明是有关于一种半导体结构的制造方法。
背景技术
在三维大型集成电路(3D LSI)芯片堆叠技术中，可以垂直堆叠两个或更多芯片，并通过铜柱和金属凸块将其接合在一起。但是，铜柱和金属凸块之间的接合面积大，因此，在热压凸块接合工艺需要较大的下压力和较高温度，并且容易导致芯片的损坏和破裂。
发明内容
本发明的目的在于提供一种半导体结构的制造方法，其可以减小导电凸块和其他半导体结构之间的接合面积，可以在低温和低负载力下进行凸块接合。
根据本发明的一个目的提供的一种半导体结构的制造方法。此方法包含以下操作。形成前驱结构。前驱结构包含基板、多个导电垫、蚀刻停止层、以及凸块下金属层。多个导电垫位于基板上。蚀刻停止层位于导电垫之间。凸块下金属层位于导电垫及蚀刻停止层之上。之后形成多个掩模结构位于凸块下金属层之上，以及形成多个开口位于掩模结构之间，其中每个掩模结构位于导电垫的其中一个之上，且开口暴露出凸块下金属层的第一部分。之后形成支撑层于开口中。之后去除掩模结构，以形成多个空腔暴露出凸块下金属层的第二部分。之后形成导电材料于空腔中。之后去除支撑层。之后去除凸块下金属层的第一部分，以形成多个彼此分离的导电凸块。
根据本发明的一些实施方式，掩模结构包含氧化物材料。
根据本发明的一些实施方式，形成掩模结构包含执行高密度等离子体工艺。
根据本发明的一些实施方式，每个掩模结构具有顶部宽度及大于顶部宽度的底部宽度。
根据本发明的一些实施方式，每个掩模结构具有尖端。
根据本发明的一些实施方式，方法还包含去除每个掩模结构的顶部部分。
根据本发明的一些实施方式，支撑层包含高分子材料。
根据本发明的一些实施方式，去除掩模结构包含湿蚀刻工艺。
根据本发明的一些实施方式，每个导电凸块覆盖导电垫的其中之一。
根据本发明的一些实施方式，每个导电凸块具有圆锥形结构或金字塔形结构。
与现有技术相比，本发明的半导体结构的制造方法，可以减小导电凸块和其他半导体结构的导电垫之间的接合面积。此外，还可以在低温和低负载力下执行凸块接合工艺。因此，该制造方法可以防止芯片在凸块接合过程中损坏和破裂。
附图说明
当读到随附的附图时，从以下详细的叙述可充分了解本发明的各方面。值得注意的是，根据工业上的标准实务，各种特征不是按比例绘制。事实上，为了清楚的讨论，各种特征的尺寸可任意增加或减少。
图1为根据本发明的一些实施方式绘示的半导体结构的制造方法流程图。
图2-图3为根据本发明的一些实施方式绘示的半导体结构的工艺各步骤的截面示意图。
图4为根据本发明的一些实施方式绘示的图3的俯视图。
图5-图10为根据本发明的一些实施方式绘示的半导体结构的工艺各步骤的截面示意图。
主要附图标记说明：
10-方法，12、14、16、18、20、22、24-操作，101-前驱结构，110-基板，120-导电垫，122、124-蚀刻停止层，130-凸块下金属层，130a-第一部分，130b-第二部分，132-凸块下金属层，140、142-掩模结构，150-支撑层，152-空腔，160-导电材料层，162-导电凸块，OP1、OP2-开口，W1、W1’、W1”、W2、W2’-顶部宽度和底部宽度。
具体实施方式
为了使本发明的叙述更加详尽与完备，下文针对了本发明的实施目的与具体实施例提出了说明性的描述，但这并非实施或运用本发明具体实施例的唯一形式。以下所公开的各实施例，在有益的情形下可相互组合或取代，也可在一实施例中附加其他的实施例，而无须进一步的记载或说明。在以下描述中，将详细叙述许多特定细节以使读者能够充分理解以下的实施例。然而，可在无此等特定细节的情况下实践本发明的实施例。
尽管下文使用所揭示的此方法中描述的一系列动作或步骤，但所示此等动作或步骤的次序不应视为限制本发明。例如，可以不同次序及/或与其他步骤同时执行某些动作或步骤。此外，并非必须执行全部步骤以便实现本发明描绘的实施例。此外，本文描述的每个操作或程序可包含若干子步骤或动作。
图1为根据本发明的一些实施方式绘示的半导体结构的制造方法流程图。如图1所示，方法10包括操作14、操作14、操作16、操作18、操作20、操作22、及操作24。图2-图10分别为根据本发明的一些实施方式绘示的半导体结构的工艺各步骤的截面示意图及俯视图。
请参考图1及图2，在方法10的操作12中，形成前驱结构101。如图2所示，前驱结构101包括基板110、多个导电垫120、蚀刻停止层122、及和凸块下金属层130。在一些实施方式中，基板110可以为半导体基板，例如硅基板，锗化硅基板、碳化硅基板，III-V族化合物半导体基板等。在一些实施方式中，基板110可以包括一个或多个主动元件(未示出)，例如晶体管。
导电垫120设置在基板110上。在一些实施方式中，导电垫120包括金属材料。导电垫120可通过适当的沉积和图案化工艺形成。蚀刻停止层122在导电垫120之间。在一些实施方式中，蚀刻停止层122包括氮化硅，但不限于此。具体地，蚀刻停止层122覆盖被导电垫120暴露的基板110，并且使导电垫120彼此分离。凸块下金属层130设置在导电垫120和蚀刻停止层122之上。具体地，凸块下金属层130共形地形成在导电垫120和蚀刻停止层122上。凸块下金属层130可以是单层或可以包括多层。在一些实施方式中，凸块下金属层130包括钛(Ti)/铜(Cu)，但不限于此。凸块下金属层130可以做为用于电化学沉积的粘着层(gluelayer)。
接下来，请参考图1和图3，在方法10的操作14中，形成多个掩模结构140在凸块下金属层130上，并且形成多个开口OP1在其之间。图4为图3的俯视图。为了简化附图，凸块下金属层130未于图4中示出。如图3和图4所示，每个掩模结构140位于一个导电垫120上，并且开口OP1暴露凸块下金属层130的第一部分130a。具体地，每个掩模结构140是单独的结构，并且每个掩模结构140的底部(即，图4中所示的虚线区域)覆盖对应的导电垫120。因此，凸块下金属层130的第一部分130a被掩模结构140之间的开口OP1暴露。在一些实施方式中，通过执行高密度等离子体(High Density Plasma,HDP)工艺在凸块下金属层130上形成掩模结构140。高密度等离子体工艺包括一个或多个沉积/蚀刻/沉积工艺，使得每个掩模结构140具有图3所示的尖端。在一些实施方式中，每个掩模结构140具有圆锥形结构或金字塔形结构。在一些实施方式中，掩模结构140包括氧化物材料，例如氧化硅。
请参考图5，在一些实施方式中，方法10还包括去除每个掩模结构140的顶部部分以形成掩模结构142。在一些实施方式中，通过化学机械研磨(CMP)工艺去除每个掩模结构140的顶部部分。掩模结构142的顶表面面积大于掩模结构140的顶表面，因此在随后的操作中去除掩模结构142更容易。如图5所示，每个掩模结构142具有顶部宽度W1和底部宽度W2，并且底部宽度W2大于顶部宽度W1。即，掩模结构142可以具有倾斜的侧壁
接下来，参考图1和图6，在方法10的操作16中，形成支撑层150在开口OP1中。在一些实施方式中，支撑层150包括高分子材料。在一些实例中，支撑层150可以为聚酰亚胺异丁唑啉(polyimide isoindro quindzoline,PIQ)。支撑层150可以通过涂覆工艺来形成，以填充开口OP1。如图6所示，支撑层150填充掩模结构142之间的开口OP1，并覆盖凸块下金属层130的第一部分130a。
接下来，参考图1和图7，在方法10的操作18中，去除掩模结构142，以形成多个空腔152暴露出凸块下金属层130的第二部分130b。在一些实施方式中，去除掩模结构142包括湿蚀刻工艺。例如，通过使用氢氟酸(HF)从掩模结构142的顶表面蚀刻来去除掩模结构142。如图7所示，空腔152具有与掩模结构142(图6所示)基本一致的形状。也就是说，每个空腔152具有宽度W1'的入口，宽度W1'基本上等于掩模结构142的顶部宽度W1。类似地，每个空腔152的底部宽度W2′基本上等于掩模结构142的底部宽度W2。
接下来，参考图1和图8，在方法10的操作20中，形成导电材料层160在空腔152中。具体地，导电材料层160形成在凸块下金属层130暴露的第二部分130b(图7所示)上。在一些实施方式中，通过执行电化学沉积工艺在空腔152中形成导电材料层160。在一些实施例中，导电材料层160包括铜(Cu)，但不限于此。
接下来，参考图1和图9，在方法10的操作22中，去除支撑层150。具体地，去除支撑层150以暴露凸块下金属层130的第一部分130a。如图9所示，导电材料层160保留在凸块下金属层130上，并且通过开口OP1彼此分离。导电材料层160的形状是从掩模结构142和空腔152而形成。因此，导电材料层160的形状基本上与掩模结构142和空腔152相同。具体地，导电材料层160具有顶部宽度W1'和底部宽度W2'。
接下来，参照图1和图10，在方法10的操作24中，去除凸块下金属层130的第一部分130a，以形成彼此分离的多个导电凸块162。可以通过适当的蚀刻工艺来去除凸块下金属层130的第一部分130a，并且蚀刻工艺可以停止在蚀刻停止层122上。具体地，去除凸块下金属层130的第一部分130a以形成凸块下金属层132。因此，形成具有多个单独的导电凸块162的半导体结构100。在一些实施方式中，每个导电凸块162覆盖导电垫120的其中之一。如图10所示，每个导电凸块162与导电垫120对准。导电垫120通过开口OP2彼此电性绝缘。导电凸块162通过凸块下金属层132电连接到对应的导电垫120，且凸块下金属层132位于导电凸块162与导电垫120之间。导电凸块162的形状类似于导电材料层160、掩模结构142和空腔152。也就是说，导电凸块162的顶部宽度W1”基本上等于顶部宽度W1和W1'。在一些实施方式中，每个导电凸块162具有圆锥形结构或金字塔形结构，但不限于此。在一些实施方式中，当去除凸块下金属层130的第一部分130a时，进一步去除位于凸块下金属层130的第一部分130a下方的蚀刻停止层122。在一些实施方式中，当去除凸块下金属层130的第一部分130a时，进一步去除凸块下金属层130的第一部分130a上的导电材料层160。导电凸块162可以与其他半导体结构上的导电垫和/或导电凸块接合。
值得注意的是，上述工艺操作仅为例示性的示出，各操作可以依照需求任意的调换顺序。在某些实施例中，在上述工艺之前、期间或之后可以执行额外的操作。
如上所述，根据本发明的实施方式，提供一种半导体结构的制造方法。本发明的方法在基板上形成具有圆锥形结构的多个导电凸块。通过高密度等离子体(HDP)工艺形成多个圆锥形掩模结构，可以容易地形成圆锥形导电凸块。具体地，在圆锥形掩模结构之间的开口中填充支撑层。然后去除圆锥形掩模结构以在支撑层中形成多个空腔，此空腔作为形成圆锥形导电凸块的模具。然后通过电化学沉积工艺形成圆锥形导电凸块。圆锥形导电凸块具有较小的顶表面面积，可以减小导电凸块和其他半导体结构(例如，芯片)的导电垫之间的接合面积。此外，可以在低温和低负载力(load force)下执行凸块接合工艺。因此，可以防止芯片在凸块接合过程中损坏和破裂。
虽然本发明已以实施方式公开如上，然其并非用以限定本发明，任何所属领域的技术人员，在不脱离本发明的精神和范围内，当可作各种的更动与润饰，因此本发明的保护范围当视权利要求所界定的为准。

Claims (10)

1.一种半导体结构的制造方法，其特征在于，包含：
形成前驱结构，所述前驱结构包含：
基板；
多个导电垫，位于所述基板上；
蚀刻停止层，位于所述多个导电垫之间；以及
凸块下金属层，位于所述多个导电垫及所述蚀刻停止层之上；
形成多个掩模结构位于所述凸块下金属层之上，以及形成多个开口位于所述多个掩模结构之间，其中各所述掩模结构位于所述多个导电垫的其中一个之上，且所述多个开口暴露出所述凸块下金属层的第一部分；
形成支撑层于所述多个开口中；
去除所述多个掩模结构，以形成多个空腔暴露出所述凸块下金属层的第二部分；
形成导电材料于所述多个空腔中；
去除所述支撑层；以及
去除所述凸块下金属层的所述第一部分，以形成多个彼此分离的导电凸块。
2.如权利要求1所述的方法，其特征在于，所述多个掩模结构包含氧化物材料。
3.如权利要求1所述的方法，其特征在于，形成所述多个掩模结构包含执行高密度等离子体工艺。
4.如权利要求1所述的方法，其特征在于，各所述掩模结构具有顶部宽度及大于所述顶部宽度的底部宽度。
5.如权利要求1所述的方法，其特征在于，各所述掩模结构具有尖端。
6.如权利要求1所述的方法，其特征在于，还包含去除各所述掩模结构的顶部部分。
7.如权利要求1所述的方法，其特征在于，所述支撑层包含高分子材料。
8.如权利要求1所述的方法，其特征在于，去除所述多个掩模结构包含湿蚀刻工艺。
9.如权利要求1所述的方法，其特征在于，各所述导电凸块覆盖所述多个导电垫的其中之一。
10.如权利要求1所述的方法，其特征在于，各所述导电凸块具有圆锥形结构或金字塔形结构。
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