US20100327442A1 - Package and the Method for Making the Same, and a Stacked Package - Google Patents
Package and the Method for Making the Same, and a Stacked Package Download PDFInfo
- Publication number
- US20100327442A1 US20100327442A1 US12/876,907 US87690710A US2010327442A1 US 20100327442 A1 US20100327442 A1 US 20100327442A1 US 87690710 A US87690710 A US 87690710A US 2010327442 A1 US2010327442 A1 US 2010327442A1
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- Prior art keywords
- circuit layer
- molding compound
- package
- disposed
- dice
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- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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Definitions
- the present invention relates to a package and the method for making the same, and more particularly to a package and the method for making the same, and a stacked package.
- a conventional method for making a stacked package a plurality of die elements are formed on a wafer first, then two or more than two wafers are stacked, and a cutting process is performed so as to form a plurality of stacked package.
- the conventional method has a disadvantage, which is that the die elements on the wafer are not tested. Therefore, the stacked packages formed as described above have the problem of high defective fraction. Especially, if more wafers are stacked, more defective fraction will occur.
- Another conventional method is provided. First, the die elements on the wafer are cut off, and then stacked after being tested.
- the method's disadvantage is that it is hard to align the die elements during the stacking process, which results in a shift between the corresponding upper and lower die elements.
- the present invention is directed to a method for making a package.
- the method comprises the following steps: (a) providing a carrier having a plurality of platforms; (b) providing a plurality of dice, and disposing the dice on the platforms; (c) performing a reflow process so that the dice are self-aligned on the platforms; (d) forming a molding compound in the gaps between the dice; and (e) performing a cutting process so as to form a plurality of packages. Since the dice are self-aligned during the reflow process, a die attach machine with high accuracy is unnecessary. That is, a die attach machine with low accuracy can achieve highly accurate placement, so the cost of the die attach machine is reduced.
- FIGS. 1 to 10 are schematic views of a method for making a package according to the present invention.
- FIGS. 11 to 23 are schematic views of a method for making a stacked package according to the present invention.
- FIGS. 1 to 10 show the schematic views of the method for making the package according to the present invention.
- a carrier 1 is provided.
- the carrier 1 has a plurality of platforms 10 .
- the carrier 1 is a silicon wafer, and each of the platforms 10 comprises a solder layer 11 and a pad 12 .
- the pad 12 is disposed between the solder layer 11 and the carrier 1 , and the material of the pad 12 is preferably metal.
- a flux 13 is formed on the platforms 10 and the carrier 1 .
- a plurality of dice 2 are provided, and disposed on the platforms 10 , that is, on the flux 13 .
- the dice 2 are tested and are known good dice.
- Each of the dice 2 comprises a first surface 21 and a second surface 22 .
- the second surface 22 faces the platforms 10 , and the second surface 22 further comprises a wettable layer 23 .
- the first surface 21 further comprises a plurality of ball pads 24 .
- a reflow process is performed so that the dice 2 are self-aligned on the platforms 10 . This is because that the solder layer 11 has surface tension during the reflow process, which makes the dice 2 on the solder layer 11 able to self-align.
- the carrier 1 further has a plurality of grooves 15 disposed between the platforms 10 .
- the grooves 15 are filled with the molding compound 14 so as to increase the combination between the molding compound 14 and the carrier 1 , as shown in FIG. 7 .
- a circuit layer 16 is formed on the molding compound 14 , and the circuit layer 16 electrically connects the dice 2 .
- the circuit layer 16 comprises a redistribution layer 161 , and the redistribution layer 161 connects the ball pads 24 .
- a plurality of solder balls 17 are further formed on the circuit layer 16 . The solder balls 17 connect the redistribution layer 161 , and further electrically connect the ball pads 24 .
- FIG. 9 the carrier 1 is removed.
- FIG. 10 a cutting process is performed so as to form a plurality of package 3 . It should be noted that the cutting process may be performed without removing the carrier 1 , so the packages 3 may include the carrier 1 .
- the pads 12 are formed on the carrier 1 by a photo-lithography process, and the solder layer 11 is formed on the pads 12 by electroplating, so that highly accurate placement can be achieved.
- the dice 4 can be self-aligned during the reflow process, so a die attach machine with high accuracy is unnecessary. That is, in the embodiment, a die attach machine with low accuracy can achieve highly accurate placement, so the cost of the die attach machine is reduced.
- FIG. 10 shows the schematic view of a package of the present invention.
- the package 3 comprises a molding compound 14 , a platform 10 , a die 2 , a wettable layer 23 and a circuit layer 16 .
- the molding compound 14 has a first surface 141 , a second surface 142 and an accommodating groove 143 .
- the accommodating groove 143 penetrates the molding compound 14 .
- the platform 10 is disposed in the accommodating groove 143 and exposed to the second surface 142 of the molding compound 14 .
- the platform 10 comprises a solder layer 11 and a pad 12 .
- the solder layer 11 is disposed between the pad 12 and the wettable layer 23 .
- the material of the pad 12 is metal.
- the die 2 is disposed in the accommodating groove 143 , and has a first surface 21 and a second surface 22 .
- the first surface 21 of the die 2 is exposed to the first surface 141 of the molding compound 14 .
- the first surface 21 of the die 2 further comprises a plurality of ball pads 24 .
- the wettable layer 23 is disposed on the second surface 22 of the die 2 , and connects the solder layer 11 of the platform 10 .
- the circuit layer 16 is disposed on the first surface 141 of the molding compound 14 , and the circuit layer 16 electrically connects the first surface 21 of the die 2 .
- the circuit layer 16 comprises a redistribution layer 161 , and the redistribution layer 161 connects the ball pads 24 .
- the circuit layer 16 further comprises a plurality of solder balls 17 .
- the solder balls 17 connect the redistribution layer 161 , and further electrically connect the ball pads 24 .
- the package 3 further comprises a carrier (not shown) disposed on the second surface 142 of the molding compound 14 .
- FIGS. 11 to 23 show the schematic views of the method for making the stacked package according to the present invention.
- a first carrier 4 is provided.
- the first carrier 4 has a plurality of first platforms 40 .
- the first carrier 4 is a silicon wafer, and each of the first platforms 40 comprises a first solder layer 41 and a first pad 42 .
- the first pads 42 is disposed between the first solder layer 41 and the first carrier 4 .
- a first flux 43 is formed on the first platforms 40 and the first carrier 4 .
- a plurality of first dice 5 are provided.
- the first dice 5 are disposed on the first platform 40 , that is, on the first flux 43 .
- the first dice 5 are tested and are known good dice.
- Each of the first dice 5 comprises a first surface 51 , a second surface 52 and at least one first via 55 .
- the second surface 52 faces the first platform 40 , and the second surface 52 further comprises a first wettable layer 53 .
- the first surface 51 further comprises a plurality of first ball pads 54 .
- the first vias 55 comprises a conductive metal therein, and the material of the conductive metal may be the same as or different from that of the first wettable layer 53 .
- a reflow process is performed so that the first dice 5 are self-aligned on the first platforms 40 . Afterward, the first flux 43 is removed.
- a first molding compound 44 is formed in the gaps between the first dice 5 , and the first ball pads 54 are exposed.
- the first carrier 4 , part of the first molding compound 44 , the first solder layer 41 , the first pad 42 and the first wettable layer 53 are removed so as to expose the first via 55 , and the first molding compound 44 has a first surface 441 and a second surface 442 .
- a first upper circuit layer 46 and a first lower circuit layer 47 are formed on the second surface 442 and the first surface 441 of the first molding compound 44 respectively, so as to form a first package 9 A.
- the first upper circuit layer 46 is electrically connected to the first lower circuit layer 47 by the first vias 55 and the first ball pads 54 , so as to form a plurality of first package elements 6 A.
- the first upper circuit layer 46 comprises a first upper redistribution layer 461
- the first lower circuit layer 47 comprises a first lower redistribution layer 471 .
- the first package 9 A comprises a first molding compound 44 , a plurality of first dice 5 , a first upper circuit layer 46 and a first lower circuit layer 47 .
- the first molding compound 44 has a first surface 441 , a second surface 442 and a plurality of first accommodating grooves 443 .
- the first accommodating grooves 443 penetrate the first molding compound 44 .
- the first dice 5 are disposed in the first accommodating grooves 443 , and each of the first dice 5 has a first surface 51 , a second surface 52 and at least one first via 55 .
- the first surfaces 51 of the first dice 5 are exposed to the first surface 441 of the first molding compound 44
- the second surfaces 52 of the first dice 5 are exposed to the second surface 442 of the first molding compound 44 .
- the first upper circuit layer 46 is disposed on the second surface 442 of the first molding compound 44 .
- the first lower circuit layer 47 is disposed on the first surface 441 of the first molding compound 44 .
- the first upper circuit layer 46 is electrically connected to the first lower circuit layer 47 by the first via 55 .
- the first package 9 A further comprises a plurality of first ball pads 54 disposed on the first surfaces 51 of the first dice 5 .
- a plurality of first solder balls 48 are further formed on the first lower circuit layer 47 , and connect the first lower redistribution layer 471 .
- the first package elements 6 A will become a singulated package, and comprises a first molding compound 44 , a first die 5 , a first upper circuit layer 46 and a first lower circuit layer 47 .
- the first molding compound 44 has a first surface 441 , a second surface 442 and a first accommodating groove 443 .
- the first accommodating groove 443 penetrates the first molding compound 44 .
- the first die 5 is disposed in the first accommodating groove 443 , and has a first surface 51 , a second surface 52 and at least one first via 55 .
- the first surface 51 of the first die 5 is exposed to the first surface 441 of the first molding compound 44
- the second surface 52 of the first die 5 is exposed to the second surface 442 of the first molding compound 44 .
- the first upper circuit layer 46 is disposed on the second surface 442 of the first molding compound 44 .
- the first lower circuit layer 47 is disposed on the first surface 441 of the first molding compound 44 .
- the first upper circuit layer 46 is electrically connected to the first lower circuit layer 47 by the first via 55 .
- the package further comprises a plurality of first ball pads 54 disposed on the first surface 51 of the first die 5 .
- a plurality of first solder balls 48 are further formed on the first lower circuit layer 47 , and connect the first lower redistribution layer 471 .
- the second package element may be a package of any type.
- the second package element is substantially the same as the first package element 6 A, and the method for making the second package is described as below.
- a second carrier 7 is provided.
- the second carrier 7 has a plurality of second platforms 70 .
- the second carrier 7 is a silicon wafer, and each of the second platforms 70 comprises a second solder layer 71 and a second pad 72 .
- the second pad 72 is disposed between the second solder layer 71 and the second carrier 7 .
- a second flux (not shown) is formed on the second platforms 70 and the second carrier 7 .
- a plurality of second dice 8 are provided, and disposed on the second platforms 70 , that is, on the second flux.
- the function or size of the second dice 8 may be the same as or different from that of the first dice 5 .
- the second dice 8 are tested and are known good dice.
- Each of the second dice 8 comprises a first surface 81 , a second surface 82 and at least one second via 85 .
- the second surface 82 faces the second platforms 70 , and the second surface 82 further comprises a second wettable layer 83 .
- the first surface 81 further comprises a plurality of second ball pads 84 .
- the second via 85 comprises a conductive metal, and the material of the conductive metal may be the same as or different from that of the second wettable layer 83 . Afterward, a reflow process is performed so that the second dice 8 are self-aligned on the second platforms 70 . Afterward, the second flux is removed.
- a second molding compound 74 is formed in the gaps between the second dice 8 , and the second ball pads 84 are exposed. Afterward, the second carrier 7 , part of the second molding compound 74 , the second solder layer 71 , the second pad 72 and the second wettable 83 are removed so as to expose the second via 85 , and the second molding compound 74 has a first surface 741 and a second surface 742 .
- a second upper circuit layer 76 and a second lower circuit layer 77 are formed on the second surface 742 and the first surface 741 of the second molding compound 74 respectively, so as to form a second package 9 B.
- the second upper circuit layer 76 is electrically connected to the second lower circuit layer 77 by the second vias 85 and the second ball pads 84 so as to form a plurality of second package elements 6 B.
- the second upper circuit layer 76 comprises a second upper redistribution layer 761
- the second lower circuit layer 77 comprises a second lower redistribution 771 .
- the second package 9 B comprises a second molding compound 74 , a plurality of second dice 8 , a second upper circuit layer 76 and a second lower circuit layer 77 .
- the second molding compound 74 has a first surface 741 , a second surface 742 and a plurality of second accommodating grooves 743 .
- the second accommodating grooves 743 penetrate the second molding compound 74 .
- the second dice 8 are disposed in the second accommodating grooves 743 , and each of the second dice 8 has a first surface 81 , a second surface 82 and at least one second via 85 .
- the first surfaces 81 of the second dice 8 are exposed to the first surface 741 of the second molding compound 74
- the second surfaces 82 of the second dice 8 are exposed to the second surface 742 of the second molding compound 74 .
- the second upper circuit layer 76 is disposed on the second surface 742 of the second molding compound 74 .
- the second lower circuit layer 77 is disposed on the first surface 441 of the second molding compound 74 .
- the second upper circuit layer 76 is electrically connected to the second lower circuit layer 77 by the second via 85 .
- the first package 9 B further comprises a plurality of second ball pads 84 disposed on the first surfaces 81 of the second dice 8 .
- a plurality of second solder balls 78 are further formed on the second lower circuit layer 77 , and connect the second lower redistribution 771 .
- the first package 9 A and the second package 9 B are stacked, and the first package element 6 A and the second package element 6 B are stacked, so as to form a stacked package 9 C. It is understood that other package element may be further stacked on the second package 9 B or the second package element 6 B.
- the second lower circuit layer 77 of the second package 9 B is electrically connected to the first upper circuit layer 46 of the first package 9 A, preferably, by the second solder balls 78 .
- a cutting process is performed so as to form a plurality of stacked package 9 .
- FIG. 23 shows the schematic view of the stacked package after cutting process of the present invention.
- the stacked package 9 comprises a first package element 6 A and a second package element 6 B.
- the first package element 6 A comprises a first molding compound 44 , a first die 5 , a first upper circuit layer 46 and a first lower circuit layer 47 .
- the first molding compound 44 has a first surface 441 , a second surface 442 and a first accommodating groove 443 .
- the first accommodating groove 443 penetrates the first molding compound 44 .
- the first die 5 is disposed in the first accommodating groove 443 , and has a first surface 51 , a second surface 52 and at least one first via 55 .
- the first surface 51 of the first die 5 is exposed to the first surface 441 of the first molding compound 44
- the second surface 52 of the first die 5 is exposed to the second surface 442 of the first molding compound 44 .
- the first surface 51 of the first die 5 further comprises a plurality of first ball pads 54 .
- the first upper circuit layer 46 is disposed on the second surface 442 of the first molding compound 44 .
- the first lower circuit layer 47 is disposed on the first surface 441 of the first molding compound 44 .
- the first upper circuit layer 46 is electrically connected to the first lower circuit layer 47 by the first via 55 .
- the first lower circuit layer 47 further comprises a plurality of first solder balls 48 .
- the second package element 6 B is stacked on the first package element 6 A, and electrically connected to the first upper circuit layer 46 .
- the second package element 6 B comprises a second molding compound 74 , a second die 8 , a second upper circuit layer 76 and a second lower circuit layer 77 .
- the second molding compound 74 has a first surface 741 , a second surface 742 and a second accommodating groove 743 .
- the second accommodating groove 743 penetrates the second molding compound 74 .
- the function or size of the second die 8 may be the same as or different from that of the first die 5 .
- the second die 8 is disposed in the second accommodating 743 , and has a first surface 81 , a second surface 82 and at least one second via 85 .
- the first surface 81 of the second die 8 is exposed to the first surface 841 of the second molding compound 84
- the second surface 82 of the second die 8 is exposed to the second surface 842 of the second molding compound 84 .
- the first surface 81 of the second die 8 further comprises a plurality of second ball pads 84 .
- the first upper circuit layer 46 is disposed on the second surface 442 of the first molding compound 44 .
- the first lower circuit layer 47 is disposed on the first surface 441 of the first molding compound 44 .
- the first upper circuit layer 46 is electrically connected to the first lower circuit layer 47 by the first via 55 .
- the second lower circuit layer 77 further comprises a plurality of second solder balls 78 .
- the second lower circuit layer 77 is electrically connected to the first upper circuit layer 46 by the second solder balls 78 .
- the dice are tested and are known good dice, and stacked with highly accurate placement, so the yield rate is raised. Moreover, dice with different sizes can be stacked in the embodiment, so the flexibility of layout is increased.
Abstract
The present invention relates to a package and the method for making the same, and a stacked package. The method for making the package includes the following steps: (a) providing a carrier having a plurality of platforms; (b) providing a plurality of dice, and disposing the dice on the platforms; (c) performing a reflow process so that the dice are self-aligned on the platforms; (d) forming a molding compound in the gaps between the dice, and (e) performing a cutting process so as to form a plurality of packages. Since the dice are self-aligned on the platforms during the reflow process, a die attach machine with low accuracy can achieve highly accurate placement.
Description
- This is a divisional of U.S. application Ser. No. 12/185,879, filed Aug. 5, 2008, and claims priority to Taiwanese Patent No. 096129098, filed Aug. 7, 2007, each of which is incorporated by reference herein.
- 1. Field of the Invention
- The present invention relates to a package and the method for making the same, and more particularly to a package and the method for making the same, and a stacked package.
- 2. Description of the Related Art
- In a conventional method for making a stacked package, a plurality of die elements are formed on a wafer first, then two or more than two wafers are stacked, and a cutting process is performed so as to form a plurality of stacked package. The conventional method has a disadvantage, which is that the die elements on the wafer are not tested. Therefore, the stacked packages formed as described above have the problem of high defective fraction. Especially, if more wafers are stacked, more defective fraction will occur.
- In order to eliminate the above-mentioned disadvantage, another conventional method is provided. First, the die elements on the wafer are cut off, and then stacked after being tested. The method's disadvantage is that it is hard to align the die elements during the stacking process, which results in a shift between the corresponding upper and lower die elements.
- Therefore, it is necessary to provide a package and the method for making the same, and a stacked package to solve the above problems.
- The present invention is directed to a method for making a package. The method comprises the following steps: (a) providing a carrier having a plurality of platforms; (b) providing a plurality of dice, and disposing the dice on the platforms; (c) performing a reflow process so that the dice are self-aligned on the platforms; (d) forming a molding compound in the gaps between the dice; and (e) performing a cutting process so as to form a plurality of packages. Since the dice are self-aligned during the reflow process, a die attach machine with high accuracy is unnecessary. That is, a die attach machine with low accuracy can achieve highly accurate placement, so the cost of the die attach machine is reduced.
-
FIGS. 1 to 10 are schematic views of a method for making a package according to the present invention; and -
FIGS. 11 to 23 are schematic views of a method for making a stacked package according to the present invention. -
FIGS. 1 to 10 show the schematic views of the method for making the package according to the present invention. First, as shown inFIG. 1 , acarrier 1 is provided. Thecarrier 1 has a plurality ofplatforms 10. In the embodiment, thecarrier 1 is a silicon wafer, and each of theplatforms 10 comprises asolder layer 11 and apad 12. Thepad 12 is disposed between thesolder layer 11 and thecarrier 1, and the material of thepad 12 is preferably metal. - As shown in
FIG. 2 , aflux 13 is formed on theplatforms 10 and thecarrier 1. - As shown in
FIG. 3 , a plurality ofdice 2 are provided, and disposed on theplatforms 10, that is, on theflux 13. In the embodiment, thedice 2 are tested and are known good dice. Each of thedice 2 comprises afirst surface 21 and asecond surface 22. Thesecond surface 22 faces theplatforms 10, and thesecond surface 22 further comprises awettable layer 23. Thefirst surface 21 further comprises a plurality ofball pads 24. - As shown in
FIG. 4 , a reflow process is performed so that thedice 2 are self-aligned on theplatforms 10. This is because that thesolder layer 11 has surface tension during the reflow process, which makes thedice 2 on thesolder layer 11 able to self-align. - As shown in
FIG. 5 , theflux 13 is removed. Afterward, as shown inFIG. 6 , amolding compound 14 is formed in the gaps between thedice 2, and theball pads 24 are exposed. Preferably, in another embodiment, thecarrier 1 further has a plurality ofgrooves 15 disposed between theplatforms 10. Thegrooves 15 are filled with themolding compound 14 so as to increase the combination between themolding compound 14 and thecarrier 1, as shown inFIG. 7 . - As shown in
FIG. 8 , acircuit layer 16 is formed on themolding compound 14, and thecircuit layer 16 electrically connects thedice 2. In the embodiment, thecircuit layer 16 comprises aredistribution layer 161, and theredistribution layer 161 connects theball pads 24. Preferably, a plurality ofsolder balls 17 are further formed on thecircuit layer 16. Thesolder balls 17 connect theredistribution layer 161, and further electrically connect theball pads 24. - In
FIG. 9 , thecarrier 1 is removed. Finally, inFIG. 10 , a cutting process is performed so as to form a plurality of package 3. It should be noted that the cutting process may be performed without removing thecarrier 1, so the packages 3 may include thecarrier 1. - In the embodiment, the
pads 12 are formed on thecarrier 1 by a photo-lithography process, and thesolder layer 11 is formed on thepads 12 by electroplating, so that highly accurate placement can be achieved. Moreover, thedice 4 can be self-aligned during the reflow process, so a die attach machine with high accuracy is unnecessary. That is, in the embodiment, a die attach machine with low accuracy can achieve highly accurate placement, so the cost of the die attach machine is reduced. -
FIG. 10 shows the schematic view of a package of the present invention. The package 3 comprises amolding compound 14, aplatform 10, adie 2, awettable layer 23 and acircuit layer 16. - The
molding compound 14 has afirst surface 141, asecond surface 142 and anaccommodating groove 143. Theaccommodating groove 143 penetrates themolding compound 14. Theplatform 10 is disposed in theaccommodating groove 143 and exposed to thesecond surface 142 of themolding compound 14. In the embodiment, theplatform 10 comprises asolder layer 11 and apad 12. Thesolder layer 11 is disposed between thepad 12 and thewettable layer 23. The material of thepad 12 is metal. - The die 2 is disposed in the
accommodating groove 143, and has afirst surface 21 and asecond surface 22. Thefirst surface 21 of thedie 2 is exposed to thefirst surface 141 of themolding compound 14. Preferably, thefirst surface 21 of the die 2 further comprises a plurality ofball pads 24. - The
wettable layer 23 is disposed on thesecond surface 22 of thedie 2, and connects thesolder layer 11 of theplatform 10. Thecircuit layer 16 is disposed on thefirst surface 141 of themolding compound 14, and thecircuit layer 16 electrically connects thefirst surface 21 of thedie 2. In the embodiment, thecircuit layer 16 comprises aredistribution layer 161, and theredistribution layer 161 connects theball pads 24. Preferably, thecircuit layer 16 further comprises a plurality ofsolder balls 17. Thesolder balls 17 connect theredistribution layer 161, and further electrically connect theball pads 24. In another embodiment, the package 3 further comprises a carrier (not shown) disposed on thesecond surface 142 of themolding compound 14. -
FIGS. 11 to 23 show the schematic views of the method for making the stacked package according to the present invention. First, as shown inFIG. 11 , afirst carrier 4 is provided. Thefirst carrier 4 has a plurality offirst platforms 40. In the embodiment, thefirst carrier 4 is a silicon wafer, and each of thefirst platforms 40 comprises afirst solder layer 41 and afirst pad 42. Thefirst pads 42 is disposed between thefirst solder layer 41 and thefirst carrier 4. - As shown in
FIG. 12 , afirst flux 43 is formed on thefirst platforms 40 and thefirst carrier 4. - As shown in
FIG. 13 , a plurality offirst dice 5 are provided. Thefirst dice 5 are disposed on thefirst platform 40, that is, on thefirst flux 43. In the embodiment, thefirst dice 5 are tested and are known good dice. Each of thefirst dice 5 comprises afirst surface 51, asecond surface 52 and at least one first via 55. Thesecond surface 52 faces thefirst platform 40, and thesecond surface 52 further comprises a firstwettable layer 53. Thefirst surface 51 further comprises a plurality offirst ball pads 54. Thefirst vias 55 comprises a conductive metal therein, and the material of the conductive metal may be the same as or different from that of the firstwettable layer 53. - As shown in
FIG. 14 , a reflow process is performed so that thefirst dice 5 are self-aligned on thefirst platforms 40. Afterward, thefirst flux 43 is removed. - As shown in
FIG. 15 , afirst molding compound 44 is formed in the gaps between thefirst dice 5, and thefirst ball pads 54 are exposed. - As shown in
FIG. 16 , thefirst carrier 4, part of thefirst molding compound 44, thefirst solder layer 41, thefirst pad 42 and the firstwettable layer 53 are removed so as to expose the first via 55, and thefirst molding compound 44 has afirst surface 441 and asecond surface 442. - As shown in
FIG. 17 , a firstupper circuit layer 46 and a firstlower circuit layer 47 are formed on thesecond surface 442 and thefirst surface 441 of thefirst molding compound 44 respectively, so as to form afirst package 9A. In thefirst package 9A, the firstupper circuit layer 46 is electrically connected to the firstlower circuit layer 47 by thefirst vias 55 and thefirst ball pads 54, so as to form a plurality offirst package elements 6A. In the embodiment, the firstupper circuit layer 46 comprises a firstupper redistribution layer 461, and the firstlower circuit layer 47 comprises a firstlower redistribution layer 471. - The
first package 9A comprises afirst molding compound 44, a plurality offirst dice 5, a firstupper circuit layer 46 and a firstlower circuit layer 47. Thefirst molding compound 44 has afirst surface 441, asecond surface 442 and a plurality of firstaccommodating grooves 443. The firstaccommodating grooves 443 penetrate thefirst molding compound 44. Thefirst dice 5 are disposed in the firstaccommodating grooves 443, and each of thefirst dice 5 has afirst surface 51, asecond surface 52 and at least one first via 55. The first surfaces 51 of thefirst dice 5 are exposed to thefirst surface 441 of thefirst molding compound 44, and thesecond surfaces 52 of thefirst dice 5 are exposed to thesecond surface 442 of thefirst molding compound 44. - The first
upper circuit layer 46 is disposed on thesecond surface 442 of thefirst molding compound 44. The firstlower circuit layer 47 is disposed on thefirst surface 441 of thefirst molding compound 44. The firstupper circuit layer 46 is electrically connected to the firstlower circuit layer 47 by the first via 55. Preferably, thefirst package 9A further comprises a plurality offirst ball pads 54 disposed on thefirst surfaces 51 of thefirst dice 5. Preferably, a plurality offirst solder balls 48 are further formed on the firstlower circuit layer 47, and connect the firstlower redistribution layer 471. - In other embodiment, if the
first package 9A undergoes a cutting process, thefirst package elements 6A will become a singulated package, and comprises afirst molding compound 44, afirst die 5, a firstupper circuit layer 46 and a firstlower circuit layer 47. Thefirst molding compound 44 has afirst surface 441, asecond surface 442 and a firstaccommodating groove 443. The firstaccommodating groove 443 penetrates thefirst molding compound 44. Thefirst die 5 is disposed in the firstaccommodating groove 443, and has afirst surface 51, asecond surface 52 and at least one first via 55. Thefirst surface 51 of thefirst die 5 is exposed to thefirst surface 441 of thefirst molding compound 44, and thesecond surface 52 of thefirst die 5 is exposed to thesecond surface 442 of thefirst molding compound 44. - The first
upper circuit layer 46 is disposed on thesecond surface 442 of thefirst molding compound 44. The firstlower circuit layer 47 is disposed on thefirst surface 441 of thefirst molding compound 44. The firstupper circuit layer 46 is electrically connected to the firstlower circuit layer 47 by the first via 55. Preferably, the package further comprises a plurality offirst ball pads 54 disposed on thefirst surface 51 of thefirst die 5. Preferably, a plurality offirst solder balls 48 are further formed on the firstlower circuit layer 47, and connect the firstlower redistribution layer 471. - Afterward, a second package element is provided. The second package element may be a package of any type. In the embodiment, the second package element is substantially the same as the
first package element 6A, and the method for making the second package is described as below. - First, as shown in
FIG. 18 , asecond carrier 7 is provided. Thesecond carrier 7 has a plurality ofsecond platforms 70. In the embodiment, thesecond carrier 7 is a silicon wafer, and each of thesecond platforms 70 comprises asecond solder layer 71 and asecond pad 72. Thesecond pad 72 is disposed between thesecond solder layer 71 and thesecond carrier 7. - Afterward, a second flux (not shown) is formed on the
second platforms 70 and thesecond carrier 7. - As shown in
FIG. 19 , a plurality ofsecond dice 8 are provided, and disposed on thesecond platforms 70, that is, on the second flux. The function or size of thesecond dice 8 may be the same as or different from that of thefirst dice 5. In the embodiment, thesecond dice 8 are tested and are known good dice. Each of thesecond dice 8 comprises afirst surface 81, asecond surface 82 and at least one second via 85. Thesecond surface 82 faces thesecond platforms 70, and thesecond surface 82 further comprises a secondwettable layer 83. Thefirst surface 81 further comprises a plurality ofsecond ball pads 84. The second via 85 comprises a conductive metal, and the material of the conductive metal may be the same as or different from that of the secondwettable layer 83. Afterward, a reflow process is performed so that thesecond dice 8 are self-aligned on thesecond platforms 70. Afterward, the second flux is removed. - As shown in
FIG. 20 , asecond molding compound 74 is formed in the gaps between thesecond dice 8, and thesecond ball pads 84 are exposed. Afterward, thesecond carrier 7, part of thesecond molding compound 74, thesecond solder layer 71, thesecond pad 72 and the second wettable 83 are removed so as to expose the second via 85, and thesecond molding compound 74 has afirst surface 741 and asecond surface 742. - As shown in
FIG. 21 , a secondupper circuit layer 76 and a secondlower circuit layer 77 are formed on thesecond surface 742 and thefirst surface 741 of thesecond molding compound 74 respectively, so as to form asecond package 9B. In thesecond package 9B, the secondupper circuit layer 76 is electrically connected to the secondlower circuit layer 77 by thesecond vias 85 and thesecond ball pads 84 so as to form a plurality ofsecond package elements 6B. In the embodiment, the secondupper circuit layer 76 comprises a secondupper redistribution layer 761, the secondlower circuit layer 77 comprises a secondlower redistribution 771. - The
second package 9B comprises asecond molding compound 74, a plurality ofsecond dice 8, a secondupper circuit layer 76 and a secondlower circuit layer 77. Thesecond molding compound 74 has afirst surface 741, asecond surface 742 and a plurality of secondaccommodating grooves 743. The secondaccommodating grooves 743 penetrate thesecond molding compound 74. Thesecond dice 8 are disposed in the secondaccommodating grooves 743, and each of thesecond dice 8 has afirst surface 81, asecond surface 82 and at least one second via 85. The first surfaces 81 of thesecond dice 8 are exposed to thefirst surface 741 of thesecond molding compound 74, and thesecond surfaces 82 of thesecond dice 8 are exposed to thesecond surface 742 of thesecond molding compound 74. - The second
upper circuit layer 76 is disposed on thesecond surface 742 of thesecond molding compound 74. The secondlower circuit layer 77 is disposed on thefirst surface 441 of thesecond molding compound 74. The secondupper circuit layer 76 is electrically connected to the secondlower circuit layer 77 by the second via 85. Preferably, thefirst package 9B further comprises a plurality ofsecond ball pads 84 disposed on thefirst surfaces 81 of thesecond dice 8. Preferably, a plurality ofsecond solder balls 78 are further formed on the secondlower circuit layer 77, and connect the secondlower redistribution 771. - As shown in
FIG. 22 , thefirst package 9A and thesecond package 9B are stacked, and thefirst package element 6A and thesecond package element 6B are stacked, so as to form astacked package 9C. It is understood that other package element may be further stacked on thesecond package 9B or thesecond package element 6B. In thestacked package 9C, the secondlower circuit layer 77 of thesecond package 9B is electrically connected to the firstupper circuit layer 46 of thefirst package 9A, preferably, by thesecond solder balls 78. Afterward, as shown inFIG. 23 , a cutting process is performed so as to form a plurality of stackedpackage 9. -
FIG. 23 shows the schematic view of the stacked package after cutting process of the present invention. Thestacked package 9 comprises afirst package element 6A and asecond package element 6B. - The
first package element 6A comprises afirst molding compound 44, afirst die 5, a firstupper circuit layer 46 and a firstlower circuit layer 47. - The
first molding compound 44 has afirst surface 441, asecond surface 442 and a firstaccommodating groove 443. The firstaccommodating groove 443 penetrates thefirst molding compound 44. Thefirst die 5 is disposed in the firstaccommodating groove 443, and has afirst surface 51, asecond surface 52 and at least one first via 55. Thefirst surface 51 of thefirst die 5 is exposed to thefirst surface 441 of thefirst molding compound 44, and thesecond surface 52 of thefirst die 5 is exposed to thesecond surface 442 of thefirst molding compound 44. Preferably, thefirst surface 51 of thefirst die 5 further comprises a plurality offirst ball pads 54. - The first
upper circuit layer 46 is disposed on thesecond surface 442 of thefirst molding compound 44. The firstlower circuit layer 47 is disposed on thefirst surface 441 of thefirst molding compound 44. The firstupper circuit layer 46 is electrically connected to the firstlower circuit layer 47 by the first via 55. Preferably, the firstlower circuit layer 47 further comprises a plurality offirst solder balls 48. - The
second package element 6B is stacked on thefirst package element 6A, and electrically connected to the firstupper circuit layer 46. - The
second package element 6B comprises asecond molding compound 74, asecond die 8, a secondupper circuit layer 76 and a secondlower circuit layer 77. - The
second molding compound 74 has afirst surface 741, asecond surface 742 and a secondaccommodating groove 743. The secondaccommodating groove 743 penetrates thesecond molding compound 74. The function or size of thesecond die 8 may be the same as or different from that of thefirst die 5. Thesecond die 8 is disposed in the second accommodating 743, and has afirst surface 81, asecond surface 82 and at least one second via 85. Thefirst surface 81 of thesecond die 8 is exposed to the first surface 841 of thesecond molding compound 84, and thesecond surface 82 of thesecond die 8 is exposed to the second surface 842 of thesecond molding compound 84. Preferably, thefirst surface 81 of thesecond die 8 further comprises a plurality ofsecond ball pads 84. - The first
upper circuit layer 46 is disposed on thesecond surface 442 of thefirst molding compound 44. The firstlower circuit layer 47 is disposed on thefirst surface 441 of thefirst molding compound 44. The firstupper circuit layer 46 is electrically connected to the firstlower circuit layer 47 by the first via 55. Preferably, the secondlower circuit layer 77 further comprises a plurality ofsecond solder balls 78. The secondlower circuit layer 77 is electrically connected to the firstupper circuit layer 46 by thesecond solder balls 78. - In the embodiment, the dice are tested and are known good dice, and stacked with highly accurate placement, so the yield rate is raised. Moreover, dice with different sizes can be stacked in the embodiment, so the flexibility of layout is increased.
- While several embodiments of the present invention have been illustrated and described, various modifications and improvements can be made by those skilled in the art. The embodiments of the present invention are therefore described in an illustrative but not restrictive sense. It is intended that the present invention should not be limited to the particular forms as illustrated, and that all modifications which maintain the spirit and scope of the present invention are within the scope defined in the appended claims.
Claims (16)
1. A stacked package, comprising:
a first package element, comprising:
a first molding compound, having a first surface, a second surface and a first accommodating groove, wherein the first accommodating groove penetrates the first molding compound;
a first die, disposed in the first accommodating groove and having a first surface, a second surface and at least one first via, wherein the first surface of the first die is exposed to the first surface of the first molding compound, the second surface of the first die is exposed to the second surface of the first molding compound;
a first upper circuit layer, disposed on the second surface of the first molding compound; and
a first lower circuit layer, disposed on the first surface of the first molding compound, and the first upper circuit layer electrically connected to the first lower circuit layer by the first via; and
a second package element, stacked on the first package element, and electrically connected to the first upper circuit layer.
2. The stacked package as claimed in claim 1 , wherein the first die further comprises a plurality of first ball pads disposed on the first surface of the first die.
3. The stacked package as claimed in claim 1 , further comprising a plurality of first solder balls disposed on the first lower circuit layer.
4. The stacked package as claimed in claim 1 , wherein the second package element comprises:
a second molding compound, having a first surface, a second surface and a second accommodating groove, wherein the second accommodating groove penetrates the second molding compound;
a second die, disposed in the second accommodating groove and having a first surface, a second surface and at least one second via, wherein the first surface of the second die is exposed to the first surface of the second molding compound, and the second surface of the second die is exposed to the second surface of the second molding compound;
a second upper circuit layer, disposed on the second surface of the second molding compound; and
a second lower circuit layer, disposed on the first surface of the second molding compound, and the second upper circuit layer electrically connected to the second lower circuit layer by the second via, and the second lower circuit layer electrically connected to the first upper circuit layer.
5. The stacked package as claimed in claim 4 , wherein the second die further comprises a plurality of second ball pads disposed on the first surface of the second die.
6. The stacked package as claimed in claim 4 , further comprising a plurality of second solder balls disposed on the second lower circuit layer and connecting the first upper circuit layer.
7. The stacked package as claimed in claim 1 , wherein the first upper circuit layer comprises a first upper redistribution layer and the first lower circuit layer comprises a first lower redistribution layer.
8. The stacked package as claimed in claim 4 , wherein the second upper circuit layer comprises a second upper redistribution layer and the second lower circuit layer comprises a second lower redistribution layer.
9. A package, comprising:
a first molding compound, having a first surface, a second surface and a plurality of first accommodating grooves, wherein the first accommodating grooves penetrate the first molding compound;
a plurality of first dice, disposed in the first accommodating grooves, each of the first dice having a first surface, a second surface and at least one first via, wherein the first surfaces of the first dice are exposed to the first surface of the first molding compound, the second surfaces of the first dice are exposed to the second surface of the first molding compound;
a first upper circuit layer, disposed on the second surface of the first molding compound; and
a first lower circuit layer, disposed on the first surface of the first molding compound, and the first upper circuit layer electrically connected to the first lower circuit layer by the first via.
10. The package as claimed in claim 9 , further comprising a plurality of first ball pads disposed on the first surfaces of the first dice.
11. The package as claimed in claim 9 , further comprising a plurality of first solder balls disposed on the first lower circuit layer.
12. The stacked package as claimed in claim 9 , wherein the first upper circuit layer comprises a first upper redistribution layer and the first lower circuit layer comprises a first lower redistribution layer.
13. A package, comprising:
a molding compound, having a first surface, a second surface and a accommodating groove, wherein the accommodating groove penetrates the molding compound;
a die, disposed in the accommodating groove, having a first surface, a second surface and at least one via, wherein the first surface of the die is exposed to the first surface of the molding compound, and the second surface of the die is exposed to the second surface of the molding compound;
an upper circuit layer, disposed on the second surface of the molding compound; and
a lower circuit layer, disposed on the first surface of the molding compound, and the upper circuit layer electrically connected to the lower circuit layer by the via.
14. The package as claimed in claim 13 , further comprising a plurality of ball pads disposed on the first surface of the die.
15. The package as claimed in claim 13 , further comprising a plurality of solder balls disposed on the lower circuit layer.
16. The package as claimed in claim 13 , wherein the upper circuit layer comprises an upper redistribution layer and the lower circuit layer comprises a lower redistribution layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/876,907 US20100327442A1 (en) | 2007-08-07 | 2010-09-07 | Package and the Method for Making the Same, and a Stacked Package |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW096129098 | 2007-08-07 | ||
TW096129098A TWI345296B (en) | 2007-08-07 | 2007-08-07 | Package having a self-aligned die and the method for making the same, and a stacked package and the method for making the same |
US12/185,879 US7811858B2 (en) | 2007-08-07 | 2008-08-05 | Package and the method for making the same, and a stacked package |
US12/876,907 US20100327442A1 (en) | 2007-08-07 | 2010-09-07 | Package and the Method for Making the Same, and a Stacked Package |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US12/185,879 Division US7811858B2 (en) | 2007-08-07 | 2008-08-05 | Package and the method for making the same, and a stacked package |
Publications (1)
Publication Number | Publication Date |
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US20100327442A1 true US20100327442A1 (en) | 2010-12-30 |
Family
ID=40345711
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
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US12/185,879 Active 2028-09-16 US7811858B2 (en) | 2007-08-07 | 2008-08-05 | Package and the method for making the same, and a stacked package |
US12/876,907 Abandoned US20100327442A1 (en) | 2007-08-07 | 2010-09-07 | Package and the Method for Making the Same, and a Stacked Package |
Family Applications Before (1)
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US12/185,879 Active 2028-09-16 US7811858B2 (en) | 2007-08-07 | 2008-08-05 | Package and the method for making the same, and a stacked package |
Country Status (2)
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US (2) | US7811858B2 (en) |
TW (1) | TWI345296B (en) |
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US20150179618A1 (en) * | 2013-12-19 | 2015-06-25 | SK Hynix Inc. | Package-on-package modules, electronic systems including the same, and memory cards including the same |
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Also Published As
Publication number | Publication date |
---|---|
TWI345296B (en) | 2011-07-11 |
US20090039526A1 (en) | 2009-02-12 |
US7811858B2 (en) | 2010-10-12 |
TW200908279A (en) | 2009-02-16 |
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