CN112669772B

CN112669772B - Display panel, driving method thereof and display device

Info

Publication number: CN112669772B
Application number: CN202011587593.8A
Authority: CN
Inventors: 张蒙蒙; 周星耀
Original assignee: Xiamen Tianma Microelectronics Co Ltd
Current assignee: Xiamen Tianma Microelectronics Co Ltd
Priority date: 2020-12-28
Filing date: 2020-12-28
Publication date: 2022-12-09
Anticipated expiration: 2040-12-28
Also published as: CN112669772A

Abstract

The application discloses a display panel, a driving method thereof and a display device, wherein a light-emitting element of the display panel is driven by a pixel circuit comprising a driving transistor, a first initialization module, a data writing module and a light-emitting control module, the first initialization module responds to a first driving signal in a reset stage of a pixel circuit driving period, a reference signal is used for carrying out preset reset processing on a first node of the pixel circuit, the reference signal comprises a period state signal, each period of the signal comprises a first state signal and a second state signal which are alternated, the preset reset processing comprises the step of utilizing the first state signal and the second state signal to carry out the alternative reset, so that the hysteresis effect of the driving transistor caused by the signals applied to the first node in the previous frame image display process is eliminated, the problem that the pixel circuit is influenced by the previous frame image in the process of driving the light-emitting element to emit light is avoided, and the image afterimage problem which may appear on the display panel is effectively solved.

Description

Display panel, driving method thereof and display device

Technical Field

The present application relates to the field of display technologies, and in particular, to a display panel, a driving method thereof, and a display device.

Background

For a novel display panel such as an OLED (Organic Light-Emitting Diode) display panel, a Micro-LED (Micro-Diode) display panel, and a QLED (Quantum Dot Light Emitting Diode) display panel, driving of a Light-Emitting unit usually needs to be completed by a pixel circuit including a plurality of TFTs (Thin Film transistors).

In the practical application process, the problem of picture ghost can occur under certain conditions, and negative effects are brought to the practical use experience of a user.

Disclosure of Invention

In order to solve the above technical problems, the present application provides a display panel, a driving method thereof, and a display device, so as to solve a problem that a display panel may have a picture ghost.

In order to achieve the technical purpose, the embodiment of the application provides the following technical scheme:

a display panel, comprising:

the light emitting device includes a substrate, and a plurality of light emitting elements located on one side of the substrate.

The pixel circuit is electrically connected with the light-emitting element and comprises a driving transistor, a first initialization module, a data writing module and a light-emitting control module; wherein,

the driving period of the pixel circuit includes a reset phase, a data writing phase, and a light emitting phase.

The first initialization module is used for responding to a first driving signal in a reset stage, performing preset reset processing on a first node of the pixel circuit by using a reference signal, and electrically connecting a control end of the driving transistor with the first node.

The reference signal comprises a periodic state signal, each period of the reference signal comprises a first state signal and a second state signal which are alternated, the preset reset processing comprises the steps of utilizing the first state signal and the second state signal to carry out alternation reset, enabling the electric potential of a first node after alternation reset to be equal to the first state signal, and enabling the phases of the first state signal and the second state signal to be different.

And the data writing module is used for writing the data signal into the first node subjected to the preset reset processing in the data writing stage.

And the light-emitting control module is used for receiving the first power supply signal and driving the light-emitting element to emit light by utilizing the written data signal in the light-emitting stage.

A driving method of the display panel as described above, the driving method comprising:

and in the resetting stage, performing preset resetting processing on the first node by using the reference signal.

And in the data writing stage, writing the data signal into the first node subjected to the preset reset processing.

In the light-emitting stage, the light-emitting element is driven to emit light by the written data signal.

A display device comprising a display panel as in the previous item.

It can be seen from the foregoing technical solutions that, an embodiment of the present application provides a display panel, a driving method thereof, and a display device, where a light emitting element of the display panel is driven by a pixel circuit including a driving transistor, a first initialization module, a data writing module, and a light emitting control module, in a reset stage of a driving period of the pixel circuit, the first initialization module performs preset reset processing on a first node of the pixel circuit by using a reference signal in response to a first driving signal, the reference signal includes a period state signal, each period of the signal includes first and second state signals that are alternated, and the preset reset processing includes alternating reset by using the first and second state signals, so as to eliminate a hysteresis effect of the driving transistor caused by a signal applied to the first node in a previous frame of image display process, thereby avoiding a problem that the pixel circuit is affected by the previous frame of image when driving the light emitting element to emit light, and effectively solving a possible image sticking problem of the display panel.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

Fig. 1 is a schematic top view of a display panel according to an embodiment of the present disclosure;

fig. 2 is a schematic structural diagram of a pixel circuit according to an embodiment of the present disclosure;

FIG. 3 is a schematic diagram illustrating a relationship between waveforms of a first driving signal and a reference signal according to an embodiment of the present disclosure;

fig. 4 is a schematic top view of another display panel according to an embodiment of the present disclosure;

fig. 5 is a schematic diagram illustrating a relationship between waveforms of a first driving signal, a second driving signal, a third driving signal and a reference signal according to an embodiment of the present disclosure;

fig. 6 is a schematic structural diagram of another pixel circuit according to an embodiment of the present disclosure;

fig. 7 is a schematic structural diagram of another pixel circuit according to an embodiment of the present disclosure;

fig. 8 is a schematic structural diagram of another pixel circuit according to an embodiment of the present disclosure;

fig. 9 is a schematic structural diagram of an alternative pixel circuit according to an embodiment of the present application;

fig. 10 is a flowchart illustrating a driving method of a display panel according to an embodiment of the present disclosure;

fig. 11 is a schematic flowchart of another driving method for a display panel according to an embodiment of the present disclosure;

fig. 12 is a schematic flowchart illustrating a driving method of a display panel according to another embodiment of the present disclosure;

fig. 13 is a schematic structural diagram of a display device according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. It will be apparent to those skilled in the art that various modifications and variations can be made in the present application without departing from the spirit or scope of the application. Thus, it is intended that the present application cover the modifications and variations of this application provided they come within the scope of the appended claims and their equivalents. It should be noted that the embodiments provided in the embodiments of the present application can be combined with each other without contradiction.

An embodiment of the present application provides a display panel, as shown in fig. 1 and fig. 2, fig. 1 is a schematic view of a top-view structure of the display panel, and fig. 2 is a schematic view of a pixel circuit of the display panel, where the display panel includes:

a substrate 100, and a plurality of light emitting elements LD located on one side of the substrate 100.

A pixel circuit 200 electrically connected to the light emitting element LD, the pixel circuit 200 including a driving transistor MQ, a first initialization module 210, a data writing module 220, and a light emission control module 230; wherein,

the driving period of the pixel circuit 200 includes a reset phase, a data writing phase, and a light emitting phase.

The first initialization module 210 is configured to perform a preset reset process on the first node N1 of the pixel circuit 200 by using the reference signal Vref in response to the first driving signal SA in the reset phase, and a control terminal of the driving transistor MQ is electrically connected to the first node N1.

The reference signal Vref includes a period state signal, each period of the reference signal Vref includes a first state signal and a second state signal which are alternated, the preset reset process includes an alternate reset using the first state signal and the second state signal, and the electric potential of the first node N1 after the alternate reset is made equal to the first state signal, and the phases of the first state signal and the second state signal are different.

The data writing module 220 is configured to write a data signal into the preset reset processed first node N1 in a data writing stage.

And a light emission control module 230 for receiving the first power signal and driving the light emitting element LD to emit light by using the written data signal in the light emission phase.

In addition to the pixel circuit 200 and the substrate 100, fig. 1 also shows a data line 310 and a gate line 320, and the gate driving method shown in fig. 1 is cross driving, in other embodiments of the present application, the gate driving method of the display panel may also be single-side driving or double-side driving, and the like, which is not limited in the present application.

The inventor finds that the image sticking problem of the display panel occurs mainly because the bias Voltage applied by the data signal of the previous frame to the control terminal of the driving transistor MQ is too large, so that the driving transistor MQ is affected by the hysteresis effect, and the defect state in the insulating layer of the control terminal of the driving transistor MQ captures the carriers, so that the Threshold Voltage (Threshold Voltage) is increased, and when the current frame image is displayed, the display panel is affected by the increase of the Threshold Voltage of the driving transistor MQ, so that the display panel is slowly transited from the previous frame image to the current frame image, thereby causing the image sticking problem, which is particularly obvious in the transition process of the display panel from pure black image display to pure white image display.

In order to solve the problem, in the display panel provided in the embodiment of the application, the first initialization module 210 performs a preset reset process on the first node N1 of the pixel circuit 200 by using the reference signal Vref in response to the first driving signal SA in the reset stage, that is, the first node N1 is alternately reset by using the reference signal Vref including the periodic state signal, so as to eliminate a hysteresis effect of the driving transistor MQ caused by a signal applied to the first node N1 in the previous frame of picture display process, thereby avoiding a problem that the pixel circuit 200 is influenced by the previous frame of picture in the process of driving the light emitting element LD to emit light, and effectively solving a picture afterimage problem that may occur in the display panel.

The first status signal and the second status signal may be a high level and a low level, respectively, and specific potentials of the high level and the low level may be the same as a potential of a positive power signal PVDD (i.e., a first power signal) and a negative power signal PVEE (i.e., a second power signal supplied to a cathode of the light emitting element LD, which may receive the second power signal through a second power signal terminal PVEE') that drive the light emitting element LD to emit light, respectively.

Referring to fig. 3, fig. 3 shows a possible waveform relationship diagram of the first driving signal SA and the reference signal Vref, in the reset phase, the first initialization module 210 is turned on in response to the first driving signal SA for multiple times, and in the on state, the first node N1 is alternately reset by using the first state signal and the second state signal of the reference signal Vref, that is, the control terminal of the driving transistor MQ is alternately applied with a positive bias and a negative bias, so as to eliminate the influence of the hysteresis effect caused by the bias of the data signal on the control terminal of the driving transistor MQ when displaying the previous frame of picture, so that the parameters such as the threshold voltage of the driving transistor MQ are recovered to be normal, and the picture ghosting problem when displaying the current frame of picture is avoided.

In addition, it should be noted that after the preset reset process is finished, the potential of the first node N1 after the alternate reset needs to be equal to the first state signal, so that the first state signal biases the driving transistor MQ, and the driving transistor MQ is in a conducting state, thereby ensuring that the subsequent data writing stage and the subsequent light emitting stage can be smoothly performed.

The first driving signal SA shown in fig. 3 is illustrated by taking low level enable as an example, that is, the first state signal is low level, and both the thin film transistor and the driving transistor MQ in the first initialization module 210 are P-type transistors and are turned on when the control terminal receives low level. In other embodiments of the present application, the thin film transistor and the driving transistor MQ in the first initialization module 210 may also be both N-type transistors, where the first state signal is a high level signal, or a part of the first state signal is a P-type transistor and another part of the first state signal is an N-type transistor, which is not limited in this application, depending on the actual situation.

Meanwhile, fig. 2 also shows a capacitor Cst, a second driving signal SC, a Data signal Data, and a third driving signal EM, where one end of the capacitor Cst is electrically connected to the first node N1, and the other end of the capacitor Cst is used for receiving the first power signal, the capacitor Cst may be used for maintaining the potential of the first node N1 after the reset phase is ended, so as to maintain the conduction state of the driving transistor MQ, and the second driving signal SC and the third driving signal EM are respectively used for controlling the conduction state of the Data writing module 220 and the light-emitting control module 230 in the Data writing phase and the light-emitting phase.

Referring to fig. 4, fig. 4 is a schematic top view of a display panel, in which a plurality of light emitting elements LD are arranged in an array to form a plurality of rows of light emitting elements LD, and two adjacent rows of light emitting elements LD form a group of light emitting element groups 400.

Referring to fig. 5 in combination, fig. 5 shows a waveform diagram of a first reference signal Vref1, a second reference signal Vref2 and a first driving signal SA received by each row of light emitting elements LD, the reference signal Vref includes a periodic state signal with a period of 2T, the first driving signal SA includes a reset waveform, the reset waveform includes a periodic state signal with a period of T, the reference signal Vref includes the first reference signal Vref1 and the second reference signal Vref2, and phases of the first reference signal Vref1 and the second reference signal Vref2 are opposite.

The first reference signal Vref1 is used to drive the ith group of light emitting element 400, and the second reference signal Vref2 is used to drive the jth group of light emitting element 400, i is an odd number greater than 0, and j is an even number greater than 0.

In the embodiment provided in the present application, the reference signal Vref is divided into a first reference signal Vref1 and a second reference signal Vref2, the phases of the first reference signal Vref1 and the second reference signal Vref2 are opposite, when the first reference signal Vref1 is used to drive the light emitting element group 400 of the odd number group (i.e., the 1 st, 2 nd, 5 th, 6 th, 9 th, 10 th rows \8230; light emitting element LD), the second reference signal Vref2 is used to drive the light emitting element group 400 of the even number row group (i.e., the 3 rd, 4 th, 7 th, 8 th, 11 th, 12 th rows \8230;. Light emitting element LD), and when the period of the periodic state signal included in the reference signal Vref is 2T, the period of the reset waveform included in the first drive signal SA is T, and when the first drive signal SA is changed to the first state signal twice adjacently, the reference signal Vref is respectively in the first state signal and the second state signal, so as to perform the alternate reset on the first node N1 by using the reference signal Vref.

In addition, in order to ensure that no matter which row of light emitting elements LD is driven, in the reset phase, when the first initialization module 210 is turned on in response to the first driving signal SA for the last time (i.e. when the first driving signal SA is at the last low level in fig. 5), the reference signal Vref should be at the first state signal at this time, so that the driving transistor MQ is in a turned-on state after the reset phase is ended, ensuring that the subsequent data writing module 220 and the light emitting control module 230 can be normally performed, still referring to fig. 5, the reset waveform includes N third state signals, where N is an odd number greater than or equal to 3.

And a fourth state signal is included between every two adjacent third state signals.

The third status signal is a level signal capable of turning on the first initialization module 210, and correspondingly, the fourth status signal is a level signal capable of turning off the first initialization module 210.

When the type of the thin film transistor in the first initialization block 210 is the same as the type of the driving transistor MQ, the third state signal may be the same as the first state signal, and the fourth state signal may be the same as the second state signal.

When the type of the thin film transistor in the first initialization block 210 is different from the type of the driving transistor MQ, the third state signal is generally different from the first state signal, and the fourth state signal is generally different from the second state signal.

In the embodiment provided in this application, the purpose of N being an odd number greater than or equal to 3 is to turn on the first initialization module 210 multiple times in the reset phase, and match with the periodic relationship between the reference signal Vref and the first driving signal SA (as mentioned above, the period of the periodic state signal included in the reference signal Vref is 2T, and the period of the reset waveform included in the first driving signal SA is T, at this time, when the first driving signal SA changes into the first state signal two times adjacently, the reference signal Vref is respectively in the first state signal and the second state signal), and reset the first node N1 alternately by using the first state signal and the second state signal, and on the other hand, the purpose of N being an odd number is to ensure that in one period, when the reset waveform is in the last third state signal, the reference signal Vref is in the first state signal, so that after the first node N1 is in the reset phase, the potential of the first node N1 is equal to the first state signal, and the conduction of the driving transistor MQ is ensured.

Still referring to fig. 5, fig. 5 also shows the second driving signal SC provided to the data writing module 220, where the second driving signal SC includes a fifth status signal, and in the data writing phase, the data writing module 220 controls the data writing module to turn on in response to the fifth status signal, so as to write the data signal into the first node N1 after the preset reset process. The fifth status signal is related to a specific kind of the thin film transistor included in the data writing block 220, and in fig. 5, when the thin film transistor included in the data writing block 220 is a P-type transistor, the fifth status signal is a low level signal. When the thin film transistor included in the data writing module 220 is an N-type transistor, the fifth state signal is a high level signal.

Also shown in fig. 5 is a third driving signal EM supplied to the light emission control module 230, the third driving signal EM including a sixth status signal, and in the light emission phase, the light emission control module 230 receives the first power line signal and drives the light emitting element LD to emit light using the written data signal in response to the sixth status signal.

In fig. 5, EMi denotes a third driving signal supplied to the light emitting element in the ith row, SAi denotes a first driving signal supplied to the light emitting element in the ith row, SCi denotes a second driving signal supplied to the light emitting element in the ith row, and i =1, 2, 3, 4, 5 \8230;.

Possible structures of the first initialization module 210, the data writing module 220, and the light emitting control module 230 are exemplified below.

Referring to fig. 6, fig. 6 shows a possible circuit structure diagram of the pixel circuit 200, the first initialization module 210 includes a first transistor M1, a first terminal of the first transistor M1 is connected to the reference signal terminal Vref ', a second terminal is connected to the first node N1, and a control terminal is connected to the first driving signal terminal SA'.

The reference signal terminal Vref 'is used for receiving the reference signal Vref, and the first driving signal terminal SA' is used for receiving the first driving signal SA.

The first transistor M1 may be a P-type transistor (as shown in fig. 6), in which case the third state signal is a low level signal and the fourth state signal is a high level signal, or the first transistor M1 may be an N-type transistor, in which case the third state signal may be a high level signal and the fourth state signal may be a low level signal. Optionally, the first transistor M1 may specifically be an Indium Gallium Zinc Oxide (IGZO) transistor, a channel material of the indium gallium Zinc Oxide transistor is an indium gallium Zinc Oxide, and a leakage current generated when the thin film transistor of this type is turned off is small, so that when the first transistor M1 is an indium gallium Zinc Oxide transistor, the leakage current generated by the first initialization module 210 may be effectively reduced, the problem of leakage current is improved, and it is beneficial to optimizing a display effect of the display panel in a low refresh rate state.

In addition, referring to fig. 7, fig. 7 shows a schematic structural diagram of another pixel circuit 200, the first transistor M1 may also be a dual-gate or multi-gate structure, that is, the first transistor M1 specifically includes two or more transistors, in fig. 7, taking two transistors as an example, control terminals of the two transistors are electrically connected, a first terminal of the T1 transistor is electrically connected to the reference signal terminal Vref', a second terminal of the T1 transistor is electrically connected to a first terminal of the T2 transistor, and a second terminal of the T2 transistor is connected to the first node N1, and the first transistor M1 in the dual-gate or multi-gate structure is beneficial to reducing a leakage current generated by the first initialization module 210 in an off state, reducing power consumption of the display device, improving stability of a control terminal voltage of the driving transistor MQ, and optimizing a display effect of the display panel.

Alternatively, referring to fig. 8, fig. 8 shows a schematic structural diagram of another pixel circuit 200, where the pixel circuit 200 further includes:

the second initialization module 240, the second initialization module 240 includes a second transistor M2, a second terminal of the second transistor M2 is electrically connected to the anode of the light emitting element LD, and a control terminal is electrically connected to the second driving signal terminal SC'.

The second driving signal terminal SC' is used for receiving a second driving signal SC, and a possible waveform of the second driving signal SC can refer to fig. 5.

The second transistor M2 may reset the anode of the light emitting element LD in response to the second driving signal SC, so that the display panel has better contrast when displaying a zero gray level picture.

For a specific reset manner of the second transistor M2, referring to fig. 8 and 9, fig. 9 shows a schematic structural diagram of another pixel circuit 200, and referring to fig. 8, a first terminal of the second transistor M2 is electrically connected to a control terminal thereof.

Or,

referring to fig. 9, in fig. 9, the first terminal of the second transistor M2 is electrically connected to the reset signal terminal Vref 3'.

In fig. 8, when the first terminal of the second transistor M2 is electrically connected to the control terminal thereof, the second driving signal SC may be used to control the on/off of the second transistor M2 in the data writing stage, or the anode of the light emitting element LD may be directly reset in a state where the second driving signal SC is at a low level when the second transistor M2 is turned on.

In fig. 9, the first terminal of the second transistor M2 is electrically connected to a reset signal terminal Vref3' for supplying a reset signal, which may be all low level signals, and the anode of the light emitting element LD is reset by the reset signal when the second transistor M2 is turned on in response to the second driving signal SC.

Still referring to fig. 6 to 9, also shown in fig. 6 to 9 is a possible structure of the data writing module 220, and the light emitting control module 230 includes: a third transistor M3 and a fourth transistor M4; wherein,

a control terminal of the third transistor M3 is electrically connected to the emission control signal terminal EM ', a first terminal thereof is electrically connected to the first power signal terminal PVDD', and a second terminal thereof is electrically connected to the first terminal of the driving transistor MQ.

The control terminal of the fourth transistor M4 is electrically connected to the emission control signal terminal EM', the first terminal is electrically connected to the second terminal of the driving transistor MQ, and the second terminal is electrically connected to the anode of the light emitting element LD.

With respect to possible configurations of the data writing module 220, still referring to fig. 6-9, the data writing module 220 includes: a fifth transistor M5 and a sixth transistor M6; wherein,

the control end of the fifth transistor M5 is electrically connected with the second driving signal end SC ', the first end is electrically connected with the Data signal end Data', and the second end is electrically connected with the first end of the driving transistor MQ;

the sixth transistor M6 has a first terminal connected to the first node N1 and a second terminal connected to the second terminal of the driving transistor MQ.

The second driving signal terminal SC' is configured to receive a second driving signal SC, a waveform of the second driving signal SC may refer to fig. 5, the second driving signal SC is a fifth state signal only in the data writing stage to control the fifth transistor M5 to be turned on, and both the reset stage and the light emitting stage are sixth state signals to control the fifth transistor M5 to be turned off, so as to avoid turning on the fifth transistor M5 in the reset stage, thereby avoiding a problem that a data signal provided to the light emitting device LD in the previous row is wrongly written into the control terminal of the driving transistor MQ to cause inconsistency of reset effects of different driving transistors MQ, and avoiding a problem of image sticking possibly caused by inconsistency of the reset effects.

For the control terminal of the sixth transistor M6, when the sixth transistor M6 and the fifth transistor M5 are of the same kind (for example, both are P-type transistors or both are N-type transistors), both of them may be electrically connected to the second driving signal terminal SC', and the sixth transistor M6 and the fifth transistor M5 may be controlled to be turned on and off by one second driving signal SC, and when the sixth transistor M6 and the fifth transistor M5 are of different kinds, the control terminal of the sixth transistor M6 may be additionally connected to the fourth driving signal terminal to receive a fourth driving signal with a phase opposite to that of the second driving signal SC.

Optionally, the sixth transistor M6 may be an indium gallium zinc oxide transistor. At this time, the control terminal of the sixth transistor M6 may be turned on when receiving a high level, where the sixth transistor M6 is an indium gallium zinc oxide transistor, which is beneficial to reducing leakage current generated by the sixth transistor M6 in an off state, improving a leakage problem, reducing power consumption of the display device, improving stability of the control terminal voltage of the driving transistor MQ, and optimizing a display effect of the display panel. Optionally, the sixth transistor M6 has a double-gate or multi-gate structure, and the specific arrangement thereof can refer to the first transistor M1.

Accordingly, an embodiment of the present application further provides a driving method of a display panel as described in any one of the above, as shown in fig. 10, fig. 10 is a schematic flow chart of the driving method of the display panel, and the driving method includes:

s101: and in the reset stage, performing preset reset processing on the first node by using the reference signal.

S102: and in the data writing stage, writing the data signal into the first node subjected to the preset reset processing.

S103: in the light-emitting stage, the light-emitting element is driven to emit light by the written data signal.

In the embodiment provided by the application, the first node is alternately reset by using the reference signal comprising the periodic state signal, so that the hysteresis effect of the driving transistor caused by the signal applied to the first node in the display process of the previous frame of picture is eliminated, the problem that the pixel circuit is influenced by the previous frame of picture in the process of driving the light-emitting element to emit light is avoided, and the picture afterimage problem possibly occurring on the display panel is effectively solved.

Optionally, referring to fig. 11, fig. 11 is a schematic flowchart of a driving method of a display panel, where the driving method of the display panel further includes:

s1012: in the data writing phase, the anode of the light emitting element is reset.

The resetting of the anode of the light-emitting element can ensure that the contrast is better when the display panel displays a zero gray scale picture.

Specifically, referring to fig. 12, fig. 12 is a flowchart illustrating a driving method of a display panel, in which resetting an anode of a light emitting element in a data writing phase includes:

s10121: resetting the anode of the light emitting element in response to the second driving signal and using the second driving signal;

or,

the anode of the light emitting element is reset in response to the second driving signal using a reset signal.

Referring to fig. 8 and 9, in fig. 8, when the first terminal of the second transistor is electrically connected to the control terminal thereof, the second driving signal may be used to control the second transistor to be turned on/off in the data writing stage, or the anode of the light emitting element may be directly reset in a state where the second driving signal is at a low level when the second transistor is turned on.

In fig. 9, the first terminal of the second transistor is electrically connected to a reset signal terminal for supplying a reset signal, and the reset signal may be a low-level signal, and when the second transistor is turned on in response to the second driving signal, the anode of the light emitting element is reset by the reset signal.

Accordingly, an embodiment of the present application further provides a display device, and as shown in fig. 13, a display device a100 includes the display panel according to any of the embodiments.

In summary, an embodiment of the present application provides a display panel, a driving method thereof, and a display device, wherein a light emitting element of the display panel is driven by a pixel circuit including a driving transistor, a first initialization module, a data writing module, and a light emitting control module, in a reset stage of a driving period of the pixel circuit, the first initialization module performs a preset reset process on a first node of the pixel circuit by using a reference signal in response to a first driving signal, the reference signal includes a period state signal, each period of the signal includes a first state signal and a second state signal that are alternated, the preset reset process includes an alternate reset by using the first state signal and the second state signal, so as to eliminate a hysteresis effect of the driving transistor caused by a signal applied to the first node in a previous frame of image display process, thereby avoiding a problem that the pixel circuit is influenced by the previous frame of image when driving the light emitting element to emit light, and effectively solving a possible image sticking problem of the display panel.

Features described in the embodiments in the present specification may be replaced with or combined with each other, each embodiment is described with a focus on differences from other embodiments, and the same and similar portions among the embodiments may be referred to each other.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, comprising:

a substrate, a plurality of light emitting elements located at one side of the substrate;

the drive cycle of the pixel circuit comprises a reset phase, a data writing phase and a light-emitting phase;

the first initialization module is used for responding to a first driving signal in the reset stage and performing preset reset processing on a first node of the pixel circuit by using a reference signal, and a control end of the driving transistor is electrically connected with the first node;

the reference signal comprises a periodic state signal, each period of the reference signal comprises a first state signal and a second state signal which are alternated, the preset reset processing comprises utilizing the first state signal and the second state signal to carry out alternation reset, the electric potential of a first node after alternation reset is equal to the first state signal, and the phases of the first state signal and the second state signal are different;

the data writing module is used for writing a data signal into the first node subjected to the preset reset processing in the data writing stage;

and the light-emitting control module is used for receiving a first power supply signal and driving the light-emitting element to emit light by utilizing the written data signal in the light-emitting stage.

2. The display panel according to claim 1, wherein the plurality of light emitting elements constitute a plurality of rows of light emitting elements, and two adjacent rows of light emitting elements constitute a group of light emitting elements;

the reference signal comprises a periodic state signal with a period of 2T, the first driving signal comprises a reset waveform, the reset waveform comprises a periodic state signal with a period of T, the reference signal comprises a first reference signal and a second reference signal, and the phases of the first reference signal and the second reference signal are opposite;

the first reference signal is used for driving the ith group of light-emitting element groups, the second reference signal is used for driving the jth group of light-emitting element groups, i is an odd number greater than 0, and j is an even number greater than 0.

3. The display panel according to claim 2, wherein the reset waveform comprises N third state signals, where N is an odd number greater than or equal to 3;

and a fourth state signal is included between two adjacent third state signals.

4. The display panel according to claim 1, wherein the first initialization module comprises a first transistor, a first terminal of the first transistor is connected to a reference signal terminal, a second terminal of the first transistor is connected to the first node, and a control terminal of the first transistor is connected to a first driving signal terminal.

5. The display panel according to claim 4, wherein the first transistor is an indium gallium zinc oxide transistor.

6. The display panel according to claim 4, further comprising:

and the second initialization module comprises a second transistor, a second end of the second transistor is electrically connected with the anode of the light-emitting element, and a control end of the second transistor is electrically connected with a second driving signal end.

7. The display panel according to claim 6, wherein a first terminal of the second transistor is electrically connected to a control terminal thereof;

or,

the first end of the second transistor is electrically connected with the reset signal end.

8. The display panel according to claim 1, wherein the light emission control module comprises:

a third transistor and a fourth transistor; wherein,

the control end of the third transistor is electrically connected with the light-emitting control signal end, the first end of the third transistor is electrically connected with the first power supply signal end, and the second end of the third transistor is electrically connected with the first end of the driving transistor;

the control end of the fourth transistor is electrically connected with the light-emitting control signal end, the first end of the fourth transistor is electrically connected with the second end of the driving transistor, and the second end of the fourth transistor is electrically connected with the anode of the light-emitting element.

9. The display panel according to claim 1, wherein the data writing module comprises:

a fifth transistor and a sixth transistor; wherein,

the control end of the fifth transistor is electrically connected with the second driving signal end, the first end of the fifth transistor is electrically connected with the data signal end, and the second end of the fifth transistor is electrically connected with the first end of the driving transistor;

a first terminal of the sixth transistor is connected to the first node, and a second terminal thereof is connected to the second terminal of the driving transistor.

10. The display panel according to claim 9, wherein the sixth transistor is an indium gallium zinc oxide transistor.

11. A driving method of the display panel according to any one of claims 1 to 10, wherein the driving method comprises:

in the reset stage, performing preset reset processing on the first node by using the reference signal;

in the data writing stage, writing the data signal into the first node after preset reset processing;

and in the light-emitting stage, driving the light-emitting element to emit light by using the written data signal.

12. The method of claim 11, further comprising:

in the data writing phase, the anode of the light emitting element is reset.

13. The method according to claim 12, wherein resetting the anode of the light emitting element in the data writing phase comprises:

responding to a second driving signal and resetting the anode of the light-emitting element by using the second driving signal;

or,

the anode of the light emitting element is reset in response to a second driving signal and with a reset signal.

14. A display device characterized by comprising the display panel according to any one of claims 1 to 10.