CN112649699A - Test method and device for determining device fault point and storage medium - Google Patents
Test method and device for determining device fault point and storage medium Download PDFInfo
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Abstract
The invention relates to the field of chip testing, and provides a testing method and a testing device for determining a device fault point. The test method for determining the fault point of the device comprises the following steps: applying constant voltage and pulse voltage to a dielectric layer of the device according to time sequence; monitoring the change condition of the pulse voltage, and determining whether a dielectric layer of the device is broken down according to the change condition of the pulse voltage; and stopping applying the pulse voltage at the moment when the dielectric layer of the device is determined to be broken down, and determining a fault point where the device is broken down earliest according to the breakdown condition of the dielectric layer. The invention can immediately sense the change of the voltage and immediately stop applying the voltage at the earliest breakdown time of the device dielectric layer. At the moment, the breakdown damage of the dielectric layer of the device is not serious, and the position of the fault point of the device which has the earliest fault can be accurately positioned according to the damage condition, so that the specific reason of the failure is analyzed, and the design improvement and the manufacturing process improvement are promoted.
Description
Technical Field
The invention relates to the field of chip testing, in particular to a testing method for determining a device fault point, a testing device for determining the device fault point and a storage medium.
Background
In the process of research and development and design of an integrated circuit chip, research and development of new materials and new processes are involved, the chip manufactured by the new materials and the new processes needs to be subjected to reliability test, and the influence of the new materials and the new processes on the performance of the chip is analyzed according to the reliability failure condition, so that the new materials or the new processes are improved.
The TDDB (time dependent dielectric breakdown, also known as time dependent breakdown) test is one of the chip reliability tests. The TDDB test is usually performed by applying a constant voltage to the gate of the MOS device to make the device in an accumulation state, and after a certain period of time, the gate oxide layer will break down, and the time elapsed during this period is the lifetime of the device under the condition. In the TDDB test process, once a chip fails, the test work is stopped, the failure phenomenon of electronic components on the chip is confirmed by various test analysis technologies and analysis programs, the failure mode and the failure mechanism are distinguished, the failure reason is confirmed, suggestions for improving the design and the manufacturing process are provided, the repeated occurrence of failure is prevented, and the reliability of the components is improved.
The prior art can hardly determine the specific reason of the failure of the device. In the TDDB test, the dielectric layer has a small leakage current before breakdown, but a large current flows through the device model at breakdown. Even if there is current limitation in the tester, the large current will damage the first failure site, causing severe burnout defects. At this time, the location of the fault point where the device model is the earliest to fail is difficult to determine, so that it is difficult to analyze the specific cause of the failure, i.e., whether it is the cause of a new process or the cause of a new material cannot be determined.
Disclosure of Invention
The invention aims to provide a test method and a test device for determining a fault point of a device, so as to solve the problem that the position of the fault point of the device which has a fault at the earliest is difficult to determine.
In order to achieve the above object, a first aspect of the present invention provides a test method for determining a failure point of a device, the method comprising:
applying constant voltage and pulse voltage to a dielectric layer of the device according to time sequence;
monitoring the change condition of the pulse voltage, and determining whether a dielectric layer of the device is broken down according to the change condition of the pulse voltage;
and stopping applying the pulse voltage at the moment when the dielectric layer of the device is determined to be broken down, and determining a fault point where the device is broken down earliest according to the breakdown condition of the dielectric layer.
Further, the applying a constant voltage and a pulse voltage to a dielectric layer of a device in time sequence includes:
applying the constant voltage to a dielectric layer of the device within a first preset time;
applying the pulse voltage to the dielectric layer of the device within a second preset time;
the second preset time is consecutive to the first preset time and after the first preset time.
Further, the second preset time is N times a difference between a lifetime time of the device and the first preset time, where N is determined according to a pulse width ratio of the pulse voltage.
Further, the first preset time is 50% -80% of the life time of the device.
Further, the determining whether the dielectric layer of the device is broken down according to the variation condition of the pulse voltage includes: and when the peak value of the pulse voltage is reduced to a preset threshold value, determining that the dielectric layer of the device is broken down.
Further, the pulse voltage is applied to the dielectric layer of the device after flowing through a resistor or inductor.
A second aspect of the present invention provides a test apparatus for determining a point of failure of a device, the apparatus comprising: the device comprises a pressure supply module, a monitoring module and an analysis module;
the voltage supply module is used for applying constant voltage and pulse voltage to the dielectric layer of the device according to time sequence;
the monitoring module is used for monitoring the change condition of the pulse voltage and determining whether a dielectric layer of the device is broken down according to the change condition of the pulse voltage;
the voltage supply module is also used for stopping applying the pulse voltage at the moment when the monitoring module determines that the dielectric layer of the device is broken down;
the analysis module is used for analyzing the breakdown condition of the dielectric layer of the device so as to determine the fault point of the device which has the earliest fault.
Further, the voltage supply module is used for applying the constant voltage to the dielectric layer of the device within a first preset time and applying the pulse voltage to the dielectric layer of the device within a second preset time; the second preset time is consecutive to the first preset time and after the first preset time.
Further, the monitoring module is configured to monitor whether a peak value of the pulse voltage is reduced to a preset threshold, and determine that a dielectric layer of the device is broken down when the peak value of the pulse voltage is reduced to the preset threshold.
The present invention also provides a storage medium having stored thereon computer program instructions which, when executed, implement the above-described test method for determining a failure point of a device.
The invention applies constant voltage at the front stage of the service life of the device and applies pulse voltage at the rear stage of the service life of the device in a mode of combining the constant voltage and the pulse voltage, can immediately sense the change of the voltage at the earliest breakdown of a dielectric layer of the device, determines the breakdown of the dielectric layer of the device and immediately stops applying the voltage. At the moment, the breakdown damage of the dielectric layer of the device is not serious, and the position of the fault point of the device which has the earliest fault can be accurately positioned according to the damage condition, so that the specific reason (whether the reason is a new process or a new material) causing the failure is analyzed, and the design improvement and the manufacturing process improvement are promoted.
Additional features and advantages of embodiments of the invention will be set forth in the detailed description which follows.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the embodiments of the invention without limiting the embodiments of the invention. In the drawings:
FIG. 1 is a flow chart of a test method for determining a failure point of a device according to an embodiment of the present invention;
FIG. 2 is a waveform diagram of a voltage applied to a device dielectric layer according to one embodiment of the present invention;
FIG. 3 is a waveform diagram illustrating a breakdown of a dielectric layer of a device after a pulse voltage is applied across a resistor according to an alternative embodiment of the present invention;
FIG. 4 is a waveform diagram illustrating a breakdown of a dielectric layer of a device after a pulsed voltage is provided across an inductor according to an alternative embodiment of the present invention;
FIG. 5 is a block diagram of a test apparatus for determining a failure point of a device according to an embodiment of the present invention.
Detailed Description
The following detailed description of embodiments of the invention refers to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating the present invention, are given by way of illustration and explanation only, not limitation.
FIG. 1 is a flow chart of a test method for determining a failure point of a device according to an embodiment of the present invention. As shown in fig. 1, the present embodiment provides a test method for determining a device failure point, the method including:
and S1, applying constant voltage and pulse voltage to the dielectric layer of the device according to time sequence.
Specifically, the constant voltage is applied to the dielectric layer of the device within a first preset time, and the pulse voltage is applied to the dielectric layer of the device within a second preset time until the dielectric layer of the device is broken down. The second preset time is N times of the difference between the life time of the device and the first preset time, wherein N is determined according to the pulse width ratio of the pulse voltage. Preferably, the first preset time is 50% -80% of the lifetime of the device.
FIG. 2 is a waveform diagram of a voltage applied to a dielectric layer of a device in accordance with one embodiment of the present invention. In the present embodiment, the pulse voltage is a square-wave pulse voltage. As shown in fig. 2, a constant voltage of 3V is applied to the dielectric layer of the device for a first preset time T1, and a square-wave pulse voltage of 3V is applied to the dielectric layer of the device for a second preset time (T2-T1). If the lifetime of the device is 500 hours, a constant voltage is applied during the first 70% (350 hours) of the lifetime and a positive square-wave pulse voltage is applied during the remaining lifetime (30%). Since the pulse width ratio of the square-wave pulse voltage is 1:2, the time for applying the square-wave pulse voltage is 2 times the remaining life time, i.e., (500-.
And S2, monitoring the change condition of the pulse voltage, and determining whether the dielectric layer of the device is broken down according to the change condition of the pulse voltage.
And applying pulse voltage to the dielectric layer of the device within second preset time, wherein the end time of the service life of the device is near, and the probability of breakdown of the dielectric layer is higher. During the period, whether the change condition of the pulse voltage reaches the voltage drop when the dielectric layer is broken down is determined by judging whether the peak value of the pulse voltage is reduced to a preset threshold value. And when the peak value of the pulse voltage is reduced to a preset threshold value, determining that the dielectric layer of the device is broken down. For example, when the peak value of the pulse voltage is reduced from 3V to 1V or less, the device dielectric layer is considered to be broken down.
And S3, stopping applying the pulse voltage when the dielectric layer of the device is determined to be broken down, and determining the earliest fault point of the device according to the breakdown condition of the dielectric layer.
The method is characterized in that pulse voltage is applied to a dielectric layer of a device, a tester can immediately sense the change of the voltage (the pulse voltage is gradually pressurized pulse by pulse, and the tester can immediately sense the change of the voltage when the voltage drop is generated) at the earliest time when the dielectric layer of the device is broken down, and the tester immediately stops applying the voltage once the change of the voltage drop exceeds a preset threshold value. At the moment, the breakdown damage of the dielectric layer of the device is not serious, and the position of the fault point of the device which has the earliest fault can be accurately positioned according to the damage condition.
If constant voltage is applied in the whole service life of the device, the tester cannot immediately sense that the dielectric layer is broken down at the earliest time when the dielectric layer of the device is broken down. The breakdown of the dielectric layer can generate voltage drop, the tester in the constant voltage mode calculates a voltage value by sampling a current value, the current sampling is periodic, and the voltage feedback is also periodic. The change of the voltage at the moment that the dielectric layer is broken down cannot be fed back to the tester immediately, the tester cannot stop applying the voltage immediately, the voltage is still applied to the dielectric layer at the moment, and when the tester senses that the voltage changes, the damage of the device is very serious. If the pulse voltage is applied in the whole life time of the device, the whole test process takes more time because the longer test time is needed for achieving the same test effect due to the characteristics of the pulse voltage.
The embodiment of the invention adopts a mode of combining constant voltage and pulse voltage, applies constant voltage at the front stage of the service life time of the device (the probability of breakdown of the dielectric layer is very low), and applies pulse voltage at the rear stage of the service life time of the device (the probability of breakdown of the dielectric layer is higher), thereby achieving better test effect and having relatively less cost. The method can immediately sense the voltage change at the earliest breakdown period of the device dielectric layer, determine that the device dielectric layer is broken down, and immediately stop applying the voltage. At the moment, the breakdown damage of the dielectric layer of the device is not serious, and the position of the fault point of the device which has the earliest fault can be accurately positioned according to the damage condition, so that the specific reason (whether the reason is a new process or a new material) causing the failure is analyzed, and the design improvement and the manufacturing process improvement are promoted.
In a preferred embodiment, the pulsed voltage is applied to the dielectric layer of the device after flowing through a resistor or inductor. For example, the pulse voltage output by the tester is applied to the dielectric layer of the device after passing through the resistor or the inductor with larger resistance (kiloohm or megaohm level), and the instantaneous large current generated when the dielectric layer is broken down is absorbed through the resistor or the inductor, so that other structures in the device are prevented from being broken down by the instantaneous large current.
Fig. 3 is a waveform diagram of a device dielectric layer being broken down after a pulse voltage is applied across a resistor according to an alternative embodiment of the present invention. As shown in fig. 3, a pulse voltage of 3V flows through the resistor and then acts on the device dielectric layer, the voltage drop change of the pulse voltage is large at the moment when the dielectric layer is broken down, the voltage drops to within 1V in a pulse period, the voltage application is stopped in a pulse period, and under the current limiting action of the resistor, the breakdown damage of the device dielectric layer is not serious, and the position of a fault point where the device breaks down at the earliest can be accurately positioned according to the damage condition.
Fig. 4 is a waveform diagram illustrating a breakdown of a dielectric layer of a device after a pulse voltage is applied across an inductor according to an alternative embodiment of the present invention. As shown in fig. 4, after a pulse voltage of 3V flows through the inductor, the pulse voltage is applied to the device dielectric layer, the voltage drop change of the pulse voltage is large at the moment when the dielectric layer is broken down, the pulse voltage drops within 1V in a pulse period, the voltage application is stopped in a pulse period, and under the current limiting action of the inductor, the breakdown damage of the device dielectric layer is not serious, and the position of the fault point where the device breaks down at the earliest can be accurately positioned according to the damage condition.
FIG. 5 is a block diagram of a test apparatus for determining a failure point of a device according to an embodiment of the present invention. As shown in fig. 5, the testing apparatus for determining a device failure point according to the embodiment of the present invention includes a voltage supply module, a monitoring module, and an analysis module. The voltage supply module is used for applying constant voltage and pulse voltage to the dielectric layer of the device according to time sequence. The monitoring module is used for monitoring the change condition of the pulse voltage and determining whether a dielectric layer of the device is broken down according to the change condition of the pulse voltage. The voltage supply module is further used for stopping applying the pulse voltage at the moment when the monitoring module determines that the dielectric layer of the device is broken down. The analysis module is used for analyzing the breakdown condition of the dielectric layer of the device so as to determine the fault point of the device which has the earliest fault.
Specifically, the voltage supply module is configured to apply the constant voltage to the dielectric layer of the device within a first preset time, and apply the pulse voltage to the dielectric layer of the device within a second preset time, where the second preset time is continuous with the first preset time and is after the first preset time.
Specifically, the monitoring module is configured to monitor whether a peak value of the pulse voltage is reduced to a preset threshold, and determine that a dielectric layer of the device is broken down when the peak value of the pulse voltage is reduced to the preset threshold.
The testing device for determining the fault point of the device provided by the embodiment of the invention adopts a mode of combining constant voltage and pulse voltage, the constant voltage is applied at the front stage of the service life of the device, and the pulse voltage is applied at the rear stage of the service life of the device. The change of the voltage can be immediately sensed at the earliest time when the dielectric layer of the device is broken down, the dielectric layer of the device is determined to be broken down, and the voltage application is immediately stopped. At the moment, the breakdown damage of the dielectric layer of the device is not serious, and the position of the fault point of the device which has the earliest fault can be accurately positioned according to the damage condition, so that the specific reason (whether the reason is a new process or a new material) causing the failure is analyzed, and the design improvement and the manufacturing process improvement are promoted.
Embodiments of the present invention also provide a storage medium having computer program instructions stored thereon, where the computer program instructions, when executed, implement the above-mentioned test method for determining a device failure point.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, systems and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solutions of the present invention and not for limiting the same, and although the present invention is described in detail with reference to the above embodiments, those of ordinary skill in the art should understand that: modifications and equivalents may be made to the embodiments of the invention without departing from the spirit and scope of the invention, which is to be covered by the claims.
Claims (10)
1. A test method for determining a point of failure of a device, the method comprising:
applying constant voltage and pulse voltage to a dielectric layer of the device according to time sequence;
monitoring the change condition of the pulse voltage, and determining whether a dielectric layer of the device is broken down according to the change condition of the pulse voltage;
and stopping applying the pulse voltage at the moment when the dielectric layer of the device is determined to be broken down, and determining a fault point where the device is broken down earliest according to the breakdown condition of the dielectric layer.
2. The test method of claim 1, wherein the applying a constant voltage and a pulsed voltage to the dielectric layer of the device in a time sequence comprises:
applying the constant voltage to a dielectric layer of the device within a first preset time;
applying the pulse voltage to the dielectric layer of the device within a second preset time;
the second preset time is consecutive to the first preset time and after the first preset time.
3. The test method for determining a device failure point according to claim 2, wherein the second preset time is N times a difference between a lifetime time of the device and the first preset time, where N is determined according to a pulse width ratio of the pulse voltage.
4. The test method for determining a failure point of a device according to claim 3, wherein the first preset time is 50-80% of a lifetime time of the device.
5. The test method for determining the fault point of the device according to claim 1, wherein the determining whether the dielectric layer of the device is broken down according to the variation condition of the pulse voltage comprises:
and when the peak value of the pulse voltage is reduced to a preset threshold value, determining that the dielectric layer of the device is broken down.
6. The test method for determining a failure point of a device according to claim 2, wherein the pulse voltage is applied to a dielectric layer of the device after flowing through a resistor or an inductor.
7. A test apparatus for determining a point of failure of a device, the apparatus comprising: the device comprises a pressure supply module, a monitoring module and an analysis module;
the voltage supply module is used for applying constant voltage and pulse voltage to the dielectric layer of the device according to time sequence;
the monitoring module is used for monitoring the change condition of the pulse voltage and determining whether a dielectric layer of the device is broken down according to the change condition of the pulse voltage;
the voltage supply module is also used for stopping applying the pulse voltage at the moment when the monitoring module determines that the dielectric layer of the device is broken down;
the analysis module is used for analyzing the breakdown condition of the dielectric layer of the device so as to determine the fault point of the device which has the earliest fault.
8. The test apparatus for determining the device failure point according to claim 7, wherein the voltage supply module is configured to apply the constant voltage to the dielectric layer of the device for a first preset time, and apply the pulse voltage to the dielectric layer of the device for a second preset time; the second preset time is consecutive to the first preset time and after the first preset time.
9. The device according to claim 7, wherein the monitoring module is configured to monitor whether a peak value of the pulse voltage is reduced to a preset threshold, and determine that a dielectric layer of the device is broken down when the peak value of the pulse voltage is reduced to the preset threshold.
10. A storage medium having computer program instructions stored thereon which, when executed, implement the test method of determining a device failure point of any of claims 1-6.
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Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1945305A (en) * | 2006-09-30 | 2007-04-11 | 中国科学院电工研究所 | Test method and device for repeated nanosecond pulse medium breakdown characteristic |
| US20090278211A1 (en) * | 2008-05-06 | 2009-11-12 | Korea Institute Of Science And Technology | Composite dielectric thin film, capacitor and field effect transistor using the same, and each fabrication method thereof |
| CN101702005A (en) * | 2009-10-28 | 2010-05-05 | 上海宏力半导体制造有限公司 | Time dependent dielectric breakdown parallel testing circuit |
| JP2012225772A (en) * | 2011-04-20 | 2012-11-15 | Renesas Electronics Corp | Semiconductor device inspection method and inspection device |
| JP2013140759A (en) * | 2012-01-06 | 2013-07-18 | Nissan Motor Co Ltd | Method for inspecting nonaqueous electrolytic secondary battery in short circuit |
| CN106908707A (en) * | 2015-12-23 | 2017-06-30 | 中芯国际集成电路制造(上海)有限公司 | A kind of method of testing of gate oxide breakdown voltage |
| CN109212401A (en) * | 2018-09-03 | 2019-01-15 | 东南大学 | Avalanche semiconductor failure analysis test method and device based on thermal imaging |
| CN109596961A (en) * | 2018-10-23 | 2019-04-09 | 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） | The method for testing reliability of GaN device, device and system |
| CN111707919A (en) * | 2020-06-29 | 2020-09-25 | 全球能源互联网研究院有限公司 | IGBT device test circuit and test method |
| CN111736048A (en) * | 2020-07-16 | 2020-10-02 | 西安交通大学 | Short-time breakdown testing method for magnetic piece insulating medium under high-frequency square wave and sine voltage |
-
2020
- 2020-12-10 CN CN202011455709.2A patent/CN112649699B/en active Active
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1945305A (en) * | 2006-09-30 | 2007-04-11 | 中国科学院电工研究所 | Test method and device for repeated nanosecond pulse medium breakdown characteristic |
| US20090278211A1 (en) * | 2008-05-06 | 2009-11-12 | Korea Institute Of Science And Technology | Composite dielectric thin film, capacitor and field effect transistor using the same, and each fabrication method thereof |
| CN101702005A (en) * | 2009-10-28 | 2010-05-05 | 上海宏力半导体制造有限公司 | Time dependent dielectric breakdown parallel testing circuit |
| JP2012225772A (en) * | 2011-04-20 | 2012-11-15 | Renesas Electronics Corp | Semiconductor device inspection method and inspection device |
| JP2013140759A (en) * | 2012-01-06 | 2013-07-18 | Nissan Motor Co Ltd | Method for inspecting nonaqueous electrolytic secondary battery in short circuit |
| CN106908707A (en) * | 2015-12-23 | 2017-06-30 | 中芯国际集成电路制造(上海)有限公司 | A kind of method of testing of gate oxide breakdown voltage |
| CN109212401A (en) * | 2018-09-03 | 2019-01-15 | 东南大学 | Avalanche semiconductor failure analysis test method and device based on thermal imaging |
| CN109596961A (en) * | 2018-10-23 | 2019-04-09 | 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） | The method for testing reliability of GaN device, device and system |
| CN111707919A (en) * | 2020-06-29 | 2020-09-25 | 全球能源互联网研究院有限公司 | IGBT device test circuit and test method |
| CN111736048A (en) * | 2020-07-16 | 2020-10-02 | 西安交通大学 | Short-time breakdown testing method for magnetic piece insulating medium under high-frequency square wave and sine voltage |
Non-Patent Citations (3)
| Title |
|---|
| K. N. MANJULARANI等: "Simulating degradation of TDDB lifetime due to burn-in using pre-conditioning pulses", 《2007 INTERNATIONAL WORKSHOP ON PHYSICS OF SEMICONDUCTOR DEVICES》 * |
| 刘红侠等: "薄栅介质TDDB效应", 《半导体学报》 * |
| 辛维平等: "片上栅氧经时击穿失效监测电路与方法", 《电子学报》 * |
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