JP2014235060A - Failure detection device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a failure detection device for predicting a failure mode of a semiconductor device.SOLUTION: A failure detection device for predicting a failure mode of an actual operation circuit provided in a semiconductor device includes: at least three failure detection circuits having the same structure as the actual operation circuit; a load circuit for applying load to the failure detection circuits so as to change the load to be applied to the failure detection circuits per unit time; and a failure determination circuit for measuring electrical characteristics of the failure detection circuit and measuring a failure mode of the actual operation circuit on the basis of the electrical characteristics.

Description

  The present invention relates to a failure detection technique for a semiconductor device.

  It is empirically known that the failure rate of a semiconductor device tends to be a so-called bathtub curve with time. The bathtub curve is classified into three regions, an initial failure period, an accidental failure period, and a wear failure period, according to the elapsed time when the failure occurs. That is, immediately after manufacturing, the failure occurrence rate due to manufacturing defects or material defects is high (initial failure), then the failure occurrence rate decreases with the passage of time and becomes only accidental failure (accidental failure). It shows that failures due to aging often occur as time progresses (wear failure).

  Conventionally, in order to prevent the initial failure of the semiconductor device, operate the product under a high load condition against the standard of temperature condition and voltage condition before shipping the product and accelerate the initial failure due to the passage of time. Eliminate burn-in tests, etc. However, the burn-in test cannot prevent accidental failure and frictional failure.

  Therefore, in order to determine the replacement time of the semiconductor device, a technique for predicting a failure of the semiconductor device is used (for example, Patent Document 1). In Patent Document 1, a deterioration check circuit having the same circuit elements as a semiconductor device actually used is provided, and the deterioration check circuit is accelerated and deteriorated by applying a larger load than the circuit elements in the semiconductor device. Thus, a technique for predicting a failure time of a semiconductor device is disclosed.

Japanese Patent Laid-Open No. 07-128384 JP 2002-277503 A JP 2004-226220 A

  If the failure mode (separate failure / accidental failure / abrasion failure) can be determined for the failure of the semiconductor device, drastic countermeasures are taken for the same product (same semiconductor device) as the failed semiconductor device. It becomes possible to take. For example, in the case of initial failure, there are usually many failures due to manufacturing, and the same product manufactured in the same manufacturing process at the same time has a high possibility of failure, so these products should be replaced. It is possible to take drastic measures such as reviewing the manufacturing process. Also, in the case of wear failure, there are many failures due to design, and there is a high possibility that failure will occur in all of the same products. It is possible to take drastic measures such as design changes.

  However, with the configuration described in Patent Document 1, it is possible to determine the replacement time of a certain semiconductor device, but it is not possible to determine the failure mode. For this reason, the failed semiconductor device can be replaced, but the cause of the failure is not known, so that a radical measure cannot be taken.

  In view of the above problems, an object of the present invention is to provide a failure detection device capable of predicting a failure mode of a semiconductor device.

In order to achieve the above object, in the embodiment, the failure detection apparatus
A failure detection device that predicts a failure mode of an actual operation circuit provided in a semiconductor device,
At least three failure detection circuits having the same structure as the actual operation circuit;
A load circuit that applies a load to each of the failure detection circuits, and a load circuit that applies a load so that the load per unit time applied to each of the failure detection circuits is different;
A failure determination circuit that measures electrical characteristics of each of the failure detection circuits and predicts a failure mode of the actual operation circuit based on the electrical characteristics.

  According to the present embodiment, it is possible to provide a failure detection device capable of predicting a failure mode of a semiconductor device.

1 is a block diagram showing a configuration of a semiconductor device 1 including a failure detection device 20 according to a first embodiment. It is a figure which shows an example of the voltage application operation | movement with respect to each circuit 22a, 22b, 22c for failure detection by the load circuit 21 which concerns on 1st Embodiment. It is a figure which shows an example of the voltage application time with respect to each circuit 22a, 22b, 22c for failure detection which concerns on 1st Embodiment. It is a figure explaining the prediction method of the failure mode by the failure detection apparatus 20 (failure determination circuit 23) which concerns on 1st Embodiment. It is a figure explaining the failure determination method of the circuit 22 for failure detection by the failure detection apparatus 20 (failure determination circuit 23) which concerns on 1st Embodiment. 3 is an example of a block diagram illustrating a configuration of a failure determination circuit 23 according to the first embodiment. FIG. It is a figure which shows an example of the failure determination method of the circuit 22a for failure detection by the failure detection apparatus 20 (failure determination circuit 23) which concerns on 2nd Embodiment. It is an example of the block diagram which shows the structure of the failure determination circuit 23 which concerns on 2nd Embodiment. It is a figure explaining the effect | action of the failure detection apparatus 20 which concerns on 2nd Embodiment. It is a block diagram which shows the structure of the failure detection apparatus 20, the semiconductor device 1, and the failure diagnosis apparatus 30 which concern on 3rd Embodiment.

  Hereinafter, embodiments for carrying out the invention will be described with reference to the drawings.

[First Embodiment]
FIG. 1 is a block diagram showing a configuration of a semiconductor device 1 including a failure detection device 20 according to the present embodiment.

  The semiconductor device 1 may be any semiconductor device. In the present embodiment, the semiconductor device 1 is, for example, an ECU (Electric Control Unit) mounted on a vehicle.

  The semiconductor device 1 includes an actual operation circuit 10 and a failure detection device 20.

  The actual operation circuit 10 is a circuit that operates to exhibit the function of the semiconductor device 1. The actual operation circuit 10 operates by supplying power from the power supply 11. The power supply 11 is provided in the actual operation circuit 10 and steps down the DC power of the voltage 12V supplied from the vehicle battery (not shown) to the operating voltage (for example, 5V) of the actual operation circuit 10. 10 is supplied. The power supply 11 may be a switching power supply or a series power supply.

  The actual operation circuit 10 includes at least one circuit element. The circuit element refers to an element constituting a circuit, for example, a semiconductor element such as a diode, wiring, or the like. In the present embodiment, the actual operation circuit 10 includes at least a MOS (Metal Oxide Semiconductor) transistor (not shown) having a gate oxide film such as MOSFET or IGBT. In general, the gate oxide film of a MOS transistor is deteriorated with time when a voltage is applied and a load is applied, and the insulation is lost, resulting in failure. In addition, an initial failure due to a defect (such as contamination) of the gate oxide film of the MOS transistor may occur. Therefore, as will be described later, the failure detection device 20 predicts a failure mode of the actual operation circuit 10 caused by the MOS transistor (gate oxide film).

  The failure detection device 20 predicts a failure mode of the actual operation circuit 10. Specifically, as will be described later, a load is applied to each of the three failure detection circuits 22 so that the time during which the voltage is applied is different, based on the mutual relationship between the electrical characteristics of the three failure detection circuits 22. The failure mode of the actual operation circuit 10 is predicted. Note that the failure mode refers to another of the initial failure, the accidental failure, and the wear failure as described above. In the following, the time during which voltage is applied may be referred to as voltage application time.

  Further, the failure detection device 20 predicts a failure of the actual operation circuit 10. Specifically, as will be described later, the failure of each failure detection circuit 22 is determined when the electrical characteristics of each failure detection circuit 22 reach the failure determination criterion, and the actual operation circuit 10 is determined based on the determination. Predict the failure.

  The load circuit 21 applies a load by applying a voltage to three failure detection circuits 22 described later while the semiconductor device 1 is activated. Similarly to the actual operation circuit 10, the load circuit 21 operates by DC power supplied from the power supply 11, and the same voltage as the actual operation circuit 10 is applied to each failure detection circuit 22. The term “while the semiconductor device 1 is being activated” means that the power is supplied to the semiconductor device 1 and the actual operation circuit 10 is operating by the power supply from the power supply 11. Further, the load circuit 21 applies a load to each failure detection circuit 22 so that the load per unit time is different. Specifically, the voltage applied to each failure detection circuit 22 is the same, and the voltages are applied so that the time during which each failure detection circuit 22 is applied with a voltage is different. The timing for applying a detailed voltage load will be described later. This makes it possible to make a difference in the deterioration progress of each failure detection circuit 22, and as will be described later, by comparing the failure detection circuits 22 having different deterioration progresses, It is possible to predict the progress of deterioration. In the present embodiment, the load circuit 21 changes the time during which a voltage is applied to each failure detection circuit 22 so that the load per unit time applied to each failure detection circuit 22 is different. However, the load applied to each failure detection circuit 22 may be varied by changing the voltage applied to each failure detection circuit 22. Further, the load circuit 21 may change the load per unit time applied to each failure detection circuit 22 by changing both the voltage application time and the applied voltage to each failure detection circuit 22.

  The failure detection circuit 22 is provided to simulate a failure of the actual operation circuit 10 when a load is applied by the load circuit 21. The failure detection circuit 22 includes three failure detection circuits, that is, a first failure detection circuit 22a, a second failure detection circuit 22b, and a third failure detection circuit 22c. Each failure detection circuit 22 has the same structure as the actual operation circuit 10. Here, the same structure refers to a structure that includes a circuit element (a MOS transistor in the present embodiment) that is a failure detection target of the actual operation circuit 10 and can simulate deterioration of the circuit element. In order to improve accuracy in simulating a failure in the actual operation circuit 10, each failure detection circuit 22 is preferably provided in the same process as the actual operation circuit 10. In the present embodiment, in order to detect a failure of the actual operation circuit 10 caused by the MOS transistor, each failure detection circuit 22 includes a MOS transistor, and a voltage is applied to the gate electrode of the MOS transistor to give a load. As a result, the deterioration of the gate oxide film proceeds. As described above, when the load is applied so that the voltage application time to each failure detection circuit 22 is different by the load circuit 21, three failure detection circuits 22 having different degrees of deterioration can be generated. Each failure detection circuit 22 may be a redundant circuit of the actual operation circuit 10. The redundant circuit is a circuit that is normally unused but is used when an abnormality occurs in the actual operation circuit 10. As described above, when at least one of the failure detection circuits 22 also serves as a redundant circuit of the actual operation circuit 10, enlargement of the semiconductor device 1, the failure detection device 20, and the like can be prevented.

  Here, the load timing given to each failure detection circuit 22 by the load circuit 21 and the voltage application time to each failure detection circuit 22 will be specifically described.

  FIG. 2 is a diagram illustrating an example of a voltage application operation to each of the failure detection circuits 22a, 22b, and 22c by the load circuit 21 according to the present embodiment. 2A to 2C are a voltage application timing chart for the first failure detection circuit 22a, a voltage application timing chart for the second failure detection circuit 22b, and a voltage application timing for the third failure detection circuit 22c, respectively. A chart is shown. In the figure, ON indicates that a voltage is applied to each failure detection circuit 22, and OFF indicates that no voltage is applied to each failure detection circuit 22.

  Referring to FIG. 2A, the voltage application timing chart for the first failure detection circuit 22a is always ON. That is, the load is always applied to the first failure detection circuit 22a by the load circuit 21 while the semiconductor device 1 is activated. Thus, the voltage application time for the first failure detection circuit 22a is always longer than the voltage application time for the actual operation circuit 10. Note that the fact that there is an OFF portion at the beginning of the time axis indicates that switching from OFF to ON is possible.

  Referring to FIG. 2B, in the voltage application timing chart for the second failure detection circuit 22b, an OFF time and an ON time that is twice the OFF time are alternately repeated. That is, the voltage application time for the second failure detection circuit 22b is 2/3 of the time during which the semiconductor device 1 is activated, and is 2/3 of the voltage application time for the first failure detection circuit 22a.

  Referring to FIG. 2C, in the voltage application timing chart for the third failure detection circuit 22c, the OFF time and the ON time that is half of the OFF time indicate that the second failure detection circuit 22b in FIG. Are alternately repeated at the same cycle as the voltage application timing chart. That is, the voltage application time for the third failure detection circuit 22c is 1/3 of the time during which the semiconductor device 1 is activated and is 1/3 of the voltage application time for the first failure detection circuit 22a.

  The ratio of the voltage application time to each of the first failure detection circuit 22a, the second failure detection circuit 22b, and the third failure detection circuit 22c is 3: 2: 1. In this way, the load is applied so that the time during which the voltage is applied to each failure detection circuit 22 is different. The ratio, timing, and the like of the voltage application time for each failure detection circuit 22 may be arbitrarily set as long as three failure detection circuits 22 having different voltage application times are generated.

  FIG. 3 is a graph showing an example of the relationship between the voltage application time for each failure detection circuit 22 and the voltage application time 10 for the actual operation circuit 10. The horizontal axis represents the voltage application time for the actual operation circuit 10, and the vertical axis represents the voltage application time for each failure detection circuit 22.

  As described above, the ratio of voltage application time to each of the first failure detection circuit 22a, the second failure detection circuit 22b, and the third failure detection circuit 22c is 3: 2: 1. Is shown as a difference in the inclination of each failure detection circuit 22.

  In the example of FIG. 3, the slope of the graph of the first failure detection circuit 22a is about 1.5, that is, the time during which the voltage is applied to the first failure detection circuit 22a is the actual operation circuit 10. It is shown that it is about 1.5 times. The slope of the graph of the second failure detection circuit 22b is about 1, that is, the time during which the voltage is applied to the second failure detection circuit is substantially the same as that of the actual operation circuit 10. Yes. The slope of the graph of the third failure detection circuit 22c is about 2/3, that is, the time during which the voltage is applied to the third failure detection circuit is about 2/3 of the actual operation circuit 10. It is shown that.

  The voltage application time for the actual operation circuit 10 varies depending on what function the actual operation circuit 10 is in the semiconductor device 1, and the graph corresponding to FIG. 3 also varies accordingly. Further, the failure mode of the actual operation circuit 10 and the failure determination of each failure detection circuit 22 to be described later are preferably performed as early as possible than the timing at which the actual operation circuit 10 fails. Therefore, the voltage application time for all three failure detection circuits 22 is preferably set so that the voltage application time is longer than that of the actual operation circuit 10.

  The load circuit 21 that applies a load to each failure detection circuit 22 at the voltage application timing shown in FIG. 2 can be constituted by a 2-bit counter, a decoder, a semiconductor relay, or the like. For example, the basic clock in the semiconductor device 1 is counted by a 2-bit counter, the count value is decoded by a decoder, and three types of voltage application timing signals corresponding to the voltage application timing chart described above are generated. By performing ON / OFF control of the three semiconductor relays corresponding to the signal, the load circuit 21 can apply a load so that the voltage application time for each failure detection circuit 22 is different.

  The failure determination circuit 23 measures the electrical characteristics of each failure detection circuit 22 and predicts the failure mode of the actual operation circuit 10 based on the electrical characteristics. The failure determination circuit 23 measures the electrical characteristics of each failure detection circuit 22 and determines a failure in each failure detection circuit 22 based on the electrical characteristics. Further, a failure of the actual operation circuit 10 is predicted based on the determination. In the present embodiment, in order to predict a failure mode and a failure due to the deterioration of the gate oxide film of the MOS transistor included in the actual operation circuit 10 over time, the gate of the MOS transistor included in each failure detection circuit 22 is used as the electrical characteristic. Measure the leakage current. A configuration example of the failure determination circuit 23 will be described later.

  Next, the failure mode determination of the actual operation circuit 10 by the failure detection device 20 (failure determination circuit 23) will be described.

  FIG. 4 is a diagram for explaining a failure mode prediction method by the failure detection apparatus 20 (failure determination circuit 23) according to the present embodiment. 4A to 4C, the vertical axis represents the electrical characteristics of each failure detection circuit 22 (in this embodiment, the gate leakage current), and the horizontal axis represents the cumulative load of each failure detection circuit 22 (this embodiment). In the embodiment, as the voltage application time), the electrical characteristics and cumulative load of each failure detection circuit 22 are shown on a graph. Note that the cumulative load of each failure detection circuit 22 means that the load applied to each failure detection circuit 22 by the load circuit 21 is accumulated, and hereinafter, the same meaning is used. Since each failure detection circuit 22 has a different load applied per unit time, the accumulated load is different, and thus the degree of deterioration is different. Further, as described above, each failure detection circuit 22 has the same structure as the actual operation circuit 10. Therefore, by plotting the points represented by the electrical characteristics and the cumulative load of each failure detection circuit 22, how the electrical characteristics of the actual operation circuit 10 change as the cumulative load increases. Can be indirectly predicted. In the present embodiment, the load circuit 21 applies a load to each failure detection circuit 22 such that the voltage is constant and the load per unit time is different by changing the voltage application time. Therefore, voltage application time (time when voltage is applied) is used on the horizontal axis as an index corresponding to the cumulative load. In addition, the electrical characteristics of each failure detection circuit 22 generally show a relatively small value within a predetermined range when normal, and show a large value as the deterioration progresses. Also in this embodiment, the gate leakage current shows a relatively small value within a predetermined range when the insulating layer of the gate oxide film is normal, and when the deterioration progresses, the gate leakage current shows a large value exceeding the predetermined range. . The predetermined range is determined depending on the process of the MOS transistor.

  FIG. 4A is a graph showing the relationship between the electrical characteristics of each failure detection circuit 22 and the accumulated load when the failure mode of the actual operation circuit 10 is predicted to be an initial failure. FIG. 4B is a graph showing the relationship between the electrical characteristics of each failure detection circuit 22 and the cumulative load when the failure mode of the actual operation circuit 10 is predicted to be an accidental failure. Referring to FIGS. 4A and 4B, the points 300 (hereinafter simply referred to as point 300) corresponding to the third failure detection circuit 22c and the second failure detection circuit 22b from the smaller cumulative load are referred to. When a corresponding point 200 (hereinafter simply referred to as the point 200) is compared, there is almost no difference in electrical characteristics (the difference in electrical characteristics is within a predetermined range), and each shows a relatively small value. On the other hand, when comparing the point 200 and the point 100 corresponding to the first failure detection circuit (hereinafter simply referred to as the point 100), the electrical characteristic of the point 100 is relatively larger than the electrical characteristic of the point 200. The slope of the straight line between the point 200 and the point 100 is relatively steep. In this way, the initial failure is a failure mode in which deterioration due to defects progresses steeply, and the accidental failure is also a failure mode that occurs due to sudden deterioration suddenly, so the characteristics on the graph as described above By detecting this, it is possible to predict an initial failure or an accidental failure. Specifically, the slope between the point 100 and the point 200 is greater than or equal to the first predetermined value A1, and the difference between the electrical characteristics of the second failure detection circuit 22b and the electrical characteristics of the third failure detection circuit 22c is When it is less than the second predetermined value A2, the failure mode of the actual operation circuit 10 is predicted to be an initial failure or an accidental failure. The second predetermined value A2 is a value determined by the predetermined range including a relatively small electrical characteristic value shown when each of the failure detection circuits 22 described above is normal. For example, the difference between the maximum value and the minimum value of the predetermined range may be set as the second predetermined value A2.

  Further, when the accumulated load of the second failure detection circuit 22b is compared, the case where the initial failure shown in FIG. 4 (a) is predicted is the case where the initial failure shown in FIG. 4 (b) is predicted. It can also be seen that the cumulative load is small (the voltage application time is short). Thus, an initial failure occurs when the cumulative load is relatively small (voltage application time is relatively short), whereas an accidental failure is a relatively large cumulative load (voltage application time is relatively short). It occurs at a relatively long stage. Therefore, it is possible to predict whether the failure is an initial failure or an accidental failure by detecting features on the graph as described above. Specifically, when the cumulative load (voltage application time) of the second failure detection circuit is less than the third predetermined value A3, the failure mode of the actual operation circuit 10 is predicted to be an initial failure, and the third When it is equal to or greater than the predetermined value, the failure mode of the actual operation circuit 10 is predicted to be an accidental failure.

  FIG. 4C is a graph showing the relationship between the electrical characteristics of each failure detection circuit 22 and the accumulated load when the failure mode of the actual operation circuit 10 is predicted to be a wear failure. Referring to FIG. 4C, when the point 300 and the point 200 are compared from the smaller cumulative load, the electric characteristic at the point 200 shows a value that is somewhat larger than the electric characteristic at the point 300. The straight line between the points 200 is not steep but has a certain degree of inclination. Further, when the point 200 and the point 100 are compared, similarly to the relationship between the point 300 and the point 200, the electric characteristic of the point 100 shows a value that is somewhat larger than the electric characteristic of the point 200. The straight line between and is not steep, but has a certain degree of inclination. As described above, the wear failure is a failure mode in which deterioration gradually proceeds to the failure, so that it can be predicted that the wear failure is detected by detecting the characteristics on the graph as described above. Specifically, when the slope between the point 100 and the point 200 is greater than or equal to the fourth predetermined value A4 and the slope between the point 200 and the point 300 is greater than or equal to the fifth predetermined value A5, The failure mode is predicted to be a wear failure. It should be noted that the fifth predetermined value A5 is a value smaller than the first predetermined value A1 because the wear-out failure gradually deteriorates.

  Next, the failure determination of the failure detection circuit 22 by the failure detection device 20 (failure determination circuit 23) will be described.

  FIG. 5 is a diagram for explaining a failure determination method of the failure detection circuit 22 by the failure detection apparatus 20 (failure determination circuit 23) according to the present embodiment. 5A to 5C, the vertical axis represents the electrical characteristics of each failure detection circuit 22 (gate leakage current in the present embodiment), and the horizontal axis represents the cumulative load of each failure detection circuit 22 (this embodiment). In the embodiment, as the voltage application time), the electrical characteristics and cumulative load of each failure detection circuit 22 are shown on a graph.

  As described above, the electrical characteristics of each failure detection circuit 22 show a relatively small value within a predetermined range when normal, and show a large value beyond the predetermined range as deterioration progresses. Therefore, the failure of each failure detection circuit 22 can be determined when the electrical characteristics of each failure detection circuit 22 are equal to or higher than the failure determination reference value Ist.

  5 (a) to 5 (c) show the electric circuit of the first failure detection circuit 22a when the failure mode of the actual operation circuit 10 described in FIG. 4 is determined as an initial failure, an accidental failure, or a wear failure. A case where the characteristic is equal to or higher than the failure determination reference value Ist is shown. As described above, generally, the electrical characteristics of the first failure detection circuit 22a having the largest accumulated load are initially equal to or higher than the failure determination reference value Ist. Further, the time during which the voltage is applied to the first failure detection circuit 22a by the load circuit 21 is longer than the time during which the voltage is applied to the actual operation circuit 10, as described above. That is, the cumulative load given to the first failure detection circuit 22 a by the load circuit 21 is larger than the cumulative load given to the actual operation circuit 10. Further, as described above, each failure detection circuit 22 has the same structure as the actual operation circuit 10. Therefore, the failure of the first failure detection circuit 22a can be determined, and the failure of the actual operation circuit 10 can be predicted based on the determination. For example, the replacement time of the semiconductor device 1 including the actual operation circuit 10 is predicted from the difference in voltage application time between the first failure detection circuit 22a and the actual operation circuit 10, the use frequency of the semiconductor device 1, the use situation, and the like. Can do. Alternatively, the semiconductor device 1 including the actual operation circuit 10 may be replaced when the failure determination of the first failure detection circuit 22a is made.

  When the second failure detection circuit 22b and the third failure detection circuit 22c are defective, etc., the second failure detection circuit 22b and the third failure detection circuit are preceded by the first failure detection circuit 22a. There is also a possibility that the detection circuit 22c will fail. Therefore, it is preferable that the failure determination is performed also for the second failure detection circuit 22b and the third failure detection circuit 22c. As described above, the second failure detection circuit 22b and the third failure detection circuit 22c also have the second failure detection circuit 22b and the third failure detection circuit when the electrical characteristics are equal to or higher than the failure determination reference value Ist. The failure of the circuit 22c is determined. As described above, when the failure determination is made first in the second failure detection circuit 22b and the third failure detection circuit 22c, the same failure is likely to occur in the actual operation circuit 10 at any time. It is predicted. Therefore, in this case, it is preferable to take measures such as promptly replacing the semiconductor device 1 including the actual operation circuit 10.

  When the load per unit time given to the second failure detection circuit 22b by the load circuit 21 is greater than or equal to the actual operation circuit 10, the failure of the second failure detection circuit 22b is determined, and based on the determination A failure of the actual operation circuit 10 may be predicted. Similarly, when the load per unit time given to the third failure detection circuit 22c is equal to or greater than the actual operation circuit 10, the failure of the third failure detection circuit 22c is determined, and based on the determination, A failure of the operation circuit 10 may be predicted.

  The failure determination circuit 23 for determining the failure mode of the actual operation circuit 10 and determining the failure of each failure detection circuit 22 can be configured by a comparison circuit including a comparator.

  Here, FIG. 6 is a block diagram illustrating an example of the configuration of the failure determination circuit 23 according to the present embodiment.

  Referring to FIG. 6, the failure determination circuit 23 includes a failure mode determination comparison circuit 24, a failure determination comparison circuit 25, an output circuit 26, and the like.

  The failure mode determination comparison circuit 24 includes comparison circuits 24a and 24b.

  The comparison circuit 24a measures each gate leakage current input from the first failure detection circuit 22a and the second failure detection circuit 22b. Further, based on each measured gate leakage current, there is a relationship between the gate leakage current and voltage application time of the first failure detection circuit 22a and the gate leakage current and voltage application time of the second failure detection circuit 22b. It is determined whether the initial failure, accidental failure, or wear failure prediction conditions described above are met.

  Similarly, the comparison circuit 24b measures the gate leakage current input from the second failure detection circuit 22b and the third failure detection circuit 22c. Further, based on each measured gate leakage current, there is a relationship between the gate leakage current and voltage application time of the second failure detection circuit 22b and the gate leakage current and voltage application time of the second failure detection circuit 22c. It is determined whether the initial failure, accidental failure, or wear failure prediction conditions described above are met.

  The voltage application time may be calculated by the failure detection device 20 having a timer (not shown), a counter for counting the number of times of voltage application, or the like, and the comparison circuits 24a and 24b based on the signals input from the timer and the counter. . Further, even when the timer or the counter is not provided, the comparison circuits 24a and 24b may indirectly calculate based on information input from the outside of the failure detection apparatus 20. For example, when the semiconductor device 1 is an ECU or the like mounted on a vehicle, the failure determination circuit 23 receives information on the odometer (odometer) of the vehicle, information on the average vehicle speed, and the like, and based on the information on the odometer and the average vehicle speed. Thus, the voltage application time may be calculated indirectly. When the vehicle is a hybrid vehicle, an electric vehicle, or the like, the failure determination circuit 23 receives information from a storage device that accumulates and stores the usage time of the high-voltage battery mounted on the vehicle, and the usage time of the high-voltage battery. Based on this information, the voltage application time may be calculated indirectly. In addition, when the semiconductor device 1 is mounted other than a vehicle, the failure determination circuit 23 receives information that directly or indirectly represents the time during which the semiconductor device 1 is activated, and based on the information, similarly, The voltage application time may be calculated indirectly.

  Signals of determination results in the comparison circuits 24 a and 24 b are input to the output circuit 26. The output circuit 26 determines whether the failure mode of the actual operation circuit 10 is an initial failure, an accidental failure, or a wear failure based on the determination results of both the comparison circuits 24a and 24b, and sends a determination signal to the failure determination circuit. 23 to the outside. It should be noted that the initial failure, the accidental failure, or the wear failure may not be determined at a time when the actual operation circuit 10 is just started to be used. In this case, the mode may be determined as undecided. Based on the determination signal, a failure mode is notified by a display monitor (not shown), an alarm (not shown), or the like, so that the developer or designer of the semiconductor device 1 knows the failure mode of the actual operation circuit 10. Can do.

  The failure determination comparison circuit 25 includes comparison circuits 25a, 25b, and 25c.

  The comparison circuit 25a measures the gate leakage current input from the first failure detection circuit 22a. Further, it is determined whether or not the first failure detection circuit 22a has failed by determining whether or not the measured gate leakage current is equal to or greater than the above-described failure determination reference value Ist that is a reference value.

  Similarly, the comparison circuits 25b and 25c also measure the gate leakage currents input from the second failure detection circuit 22b and the third failure detection circuit 22c, respectively, and calculate the gate leakage current and the failure determination reference value Ist. Based on the relationship, it is determined whether the second failure detection circuit 22b and the third failure detection circuit 22c are out of order.

  The determination result signals from the comparison circuits 25a, 25b, and 25c are input to the output circuit 26. The output circuit 26 outputs a failure determination signal to the outside of the failure determination circuit 23 when a signal that determines a failure is input from any of the comparison circuits 25a, 25b, and 25c. Based on the failure determination signal, the failure detection circuit 22 is notified by a display monitor, an alarm, or the like, so that the user of the vehicle or the like on which the semiconductor device 1 is mounted or the developer of the semiconductor device 1 A designer or the like can replace the semiconductor device 1 including the actual operation circuit 10. The output circuit 26 predicts the failure time of the actual operation circuit 10 and the like when the signal for determining the failure is input from any of the comparison circuits 25a, 25b, and 25c, and determines the replacement time of the actual operation circuit 10. You may notify by a display monitor etc.

  Next, the operation of the failure detection apparatus 20 according to this embodiment will be described.

  The failure detection apparatus 20 according to the present embodiment includes at least three failure detection circuits 22 having the same structure as the actual operation circuit 10. Further, the load is applied so that the load per unit time given to each failure detection circuit 22 by the load circuit 21 is different. As a result, it is possible to generate three failure detection circuits 22 with different degrees of deterioration, and by comparing the electrical characteristics of the three failure detection circuits 22, how the electrical characteristics of the actual operation circuit 10 are changed. It is possible to simulate the failure mode of the actual operation circuit 10. Therefore, the failure mode of the actual operation circuit 10 can be predicted.

  Further, since the failure mode of the actual operation circuit 10 can be predicted, the cause of failure is narrowed down and the products to be failed (products that are likely to fail due to the same cause among the same products as the semiconductor device 1) are narrowed down. And can take radical measures against the same product. For example, since the initial failure usually has many failures caused by manufacturing, it is possible to narrow down the cause of the failure to the manufacturing process or the like. Also, in the case of initial failure, there are many failures due to manufacturing, so there is a high possibility of failure occurring in the same product manufactured in the same manufacturing process at the same time, and the product can be narrowed down as a product subject to failure. It is possible to take measures such as replacement of a product before the product fails. Furthermore, it is possible to take drastic measures such as reviewing the manufacturing process. On the other hand, since the wear failure usually has many failures due to the design, the cause of the failure can be narrowed down to the design area. Further, since there is a high possibility that a wear failure will occur in all of the same product, it is possible to take measures such as replacing the same product before reaching the elapsed time at which the failure is predicted. Furthermore, drastic measures such as design changes can be taken.

  Specifically, the failure detection apparatus 20 according to the present embodiment includes the electrical characteristics of the first failure detection circuit 22a, the electrical characteristics of the second failure detection circuit 22b, and the third failure detection circuit 22c. Based on the relationship with the electrical characteristics, it can be predicted whether the failure mode is an initial failure, an accidental failure, or a wear failure.

  Further, in the case of an initial failure or an accidental failure, deterioration due to a defect or accidental progresses rapidly. Accordingly, the vertical axis represents the electrical characteristics of each failure detection circuit 22 and the horizontal axis represents the electrical characteristics and cumulative load (voltage application time) of the first failure detection circuit 22a, with the cumulative load of each failure detection circuit 22 being expressed. And the slope of the straight line connecting the point represented by the electrical characteristics of the second failure detection circuit and the accumulated load (voltage application time) is equal to or greater than the first predetermined value A1, and the second failure detection The failure mode of the actual operation circuit 10 is predicted to be an initial failure or an accidental failure when the difference between the electrical characteristics of the circuit 22b and the electrical characteristics of the third failure detection circuit 22c is equal to or less than the second predetermined value A2. can do.

  An initial failure occurs when the cumulative load is relatively small (voltage application time is relatively short), whereas an accidental failure is a relatively large cumulative load (voltage application time is relatively short). Occurs in the (long) stage. Therefore, when the cumulative load (voltage application time) of the second failure detection circuit is less than the third predetermined value A3, the failure mode of the actual operation circuit 10 is predicted to be the initial failure, and the third predetermined If it is greater than or equal to the value A3, it can be predicted that it is an accidental failure.

  Further, in the case of a wear failure, the deterioration progresses slowly and leads to a failure. Therefore, the slope of the straight line connecting the point represented by the electrical characteristics and cumulative load of the first failure detection circuit 22a and the point represented by the electrical characteristics and cumulative load of the second failure detection circuit 22b is the fourth. A point that is equal to or greater than a predetermined value A4 and is represented by the electrical characteristics and cumulative load of the second failure detection circuit 22b, and a point that is represented by the electrical characteristics and cumulative load of the third failure detection circuit 22c. When the slope of the connecting line is equal to or greater than the fifth predetermined value A5, the failure mode of the actual operation circuit 10 can be predicted to be a wear failure.

  In this embodiment, the load per unit time given to at least one of the fault detection circuits 22 (fault detection circuit 22a) is equal to or higher than the load per unit time given to the actual operation circuit 10. is there. Thereby, since the deterioration of the failure detection circuit 22a proceeds more than the actual operation circuit 10, a failure of the actual operation circuit 10 is predicted based on the determination by determining the failure of the failure detection circuit 22a. be able to. Specifically, the electrical characteristics of the failure detection circuit 22a are measured, and when the electrical characteristics are equal to or higher than the failure determination standard Ist, the failure of the failure detection circuit 22a may be determined.

  In the present embodiment, the load circuit 21 applies a load to each failure detection circuit 22 by applying the same voltage as the load applied to the actual operation circuit 10. As a result, since the booster circuit or the like for causing the deterioration of each failure detection circuit 22 to progress more than the actual operation circuit 10 is not used, the failure detection device 20 can be prevented from being enlarged.

  In the present embodiment, each failure detection circuit 22 may be a redundant circuit of the actual operation circuit 10. As a result, when at least one of the failure detection circuits 22 also serves as a redundant circuit of the actual operation circuit 10, enlargement of the semiconductor device 1, the failure detection device 20, and the like can be prevented.

  In the present embodiment, the actual operation circuit 10 and each failure detection circuit 22 include MOS transistors, and by using a gate leakage current as the electrical characteristics, a failure mode and a failure caused by the deterioration of the gate oxide film can be obtained. Can make predictions.

[Second Embodiment]
Next, a second embodiment will be described.

  The failure detection apparatus 20 according to the present embodiment has the first point that failure determination is performed based on the relationship between the electrical characteristics of the first failure detection circuit 22a and the electrical characteristics of the second failure detection circuit 22b. Different from the embodiment. Hereinafter, the same components as those in the first embodiment are denoted by the same reference numerals, and different portions will be mainly described.

  FIG. 1 is a block diagram showing a configuration of a semiconductor device 1 including a failure detection device 20 according to the present embodiment. FIG. 2 is a diagram illustrating an example of a voltage application operation to each of the failure detection circuits 22a, 22b, and 22c by the load circuit 21 according to the present embodiment. FIG. 3 is a diagram showing an example of a graph showing the relationship between the voltage application time for each failure detection circuit 22 and the voltage application time 10 for the actual operation circuit 10. The above is the same as that of the first embodiment, and detailed description thereof is omitted.

  FIG. 4 is a diagram for explaining a failure mode determination method by the failure detection apparatus 20 (failure determination circuit 23) according to the present embodiment. Since the failure mode determination method is the same as that in the first embodiment, a detailed description thereof will be omitted.

  Next, the failure determination of the failure detection circuit 22 by the failure detection apparatus 20 (failure determination circuit 23) according to the present embodiment will be described.

  FIG. 7 is a diagram for explaining a failure determination method of the failure detection circuit 22 by the failure detection apparatus 20 (failure determination circuit 23) according to the present embodiment. 7A to 7C, the vertical axis represents the electrical characteristics of each failure detection circuit 22 (in this embodiment, the gate leakage current), and the horizontal axis represents the cumulative load of each failure detection circuit 22 (this embodiment). In the embodiment, as the voltage application time), the electrical characteristics and cumulative load of each failure detection circuit 22 are shown on a graph.

  As described above, the electrical characteristics of each failure detection circuit 22 show a relatively small value within a predetermined range when normal, and show a large value beyond the predetermined range as deterioration progresses. Here, when the electrical characteristics of each failure detection circuit 22 change suddenly and show a large value, it is considered that the progress of deterioration is accelerated. Therefore, in this embodiment, the failure of each failure detection circuit 22 is determined when the progress of the deterioration is accelerated to some extent.

  As described above, each failure detection circuit 22 has a different accumulated load, and thus has a different degree of deterioration. Each failure detection circuit 22 has the same structure as the actual operation circuit 10. Therefore, the failure of the first failure detection circuit 22a can be determined based on the relationship between the electrical characteristics of the first failure detection circuit 22a and the electrical characteristics of the second failure detection circuit 22b. Similarly, the failure of the second failure detection circuit 22b can be determined based on the relationship between the electrical characteristics of the second failure detection circuit 22b and the electrical characteristics of the third failure detection circuit 22c. . Specifically, the slope of a straight line connecting the point represented by the electrical characteristics and cumulative load of the first failure detection circuit 22a and the point represented by the electrical characteristics and cumulative load of the second failure detection circuit 22b. Can be determined to be a failure of the first failure detection circuit 22a. Similarly, the slope of a straight line connecting the point represented by the electrical characteristics and cumulative load of the second failure detection circuit 22b and the point represented by the electrical characteristics and cumulative load of the third failure detection circuit 22c. Can be determined to be a failure of the second failure detection circuit 22b.

  FIGS. 7A to 7C are diagrams illustrating the electrical operation of the first failure detection circuit 22a when the failure mode of the actual operation circuit 10 described in FIG. 4 is determined as an initial failure, an accidental failure, or a wear failure. The case where the slope of the straight line connecting the point represented by the characteristic and the accumulated load and the point represented by the electrical characteristic and the accumulated load of the second failure detection circuit 22b is equal to or greater than the sixth predetermined value A6 is shown. Yes. As described above, generally, the point represented by the electrical characteristics and cumulative load of the first failure detection circuit 22a having the largest cumulative load, and the point represented by the electrical characteristics and cumulative load of the second failure detection circuit 22b. First, the inclination of becomes a sixth predetermined value A6 or more. Further, the time during which the voltage is applied to the first failure detection circuit 22a by the load circuit 21 is longer than the time during which the voltage is applied to the actual operation circuit 10, as described above. That is, the cumulative load given to the first failure detection circuit 22 a by the load circuit 21 is larger than the cumulative load given to the actual operation circuit 10. Further, as described above, each failure detection circuit 22 has the same structure as the actual operation circuit 10. Therefore, the failure of the first failure detection circuit 22a can be determined, and the failure of the actual operation circuit 10 can be predicted based on the determination. For example, the replacement time of the semiconductor device 1 including the actual operation circuit 10 is predicted from the difference in voltage application time between the first failure detection circuit 22a and the actual operation circuit 10, the use frequency of the semiconductor device 1, the use situation, and the like. Can do. Alternatively, the semiconductor device 1 including the actual operation circuit 10 may be replaced when the failure determination of the first failure detection circuit 22a is made.

  In addition, when the second failure detection circuit 22b is a defective product or the like, the second failure detection circuit 22b may fail before the first failure detection circuit 22a. As described above, when the failure is determined earlier in the second failure detection circuit 22b, it is predicted that the same failure is likely to occur in the actual operation circuit 10 at any time. Therefore, in this case, it is preferable to take measures such as promptly replacing the semiconductor device 1 including the actual operation circuit 10.

  When the load per unit time given to the second failure detection circuit 22b by the load circuit 21 is greater than or equal to the actual operation circuit 10, the second failure detection circuit 22b and the third failure detection circuit 22c The failure of the two failure detection circuit 22b may be determined, and the failure of the actual operation circuit 10 may be predicted based on the determination.

  The failure determination circuit 23 for determining the failure mode of the actual operation circuit 10 and determining the failure of each failure detection circuit 22 may be configured by a comparison circuit including a comparator, as in the first embodiment. Is possible.

  Here, FIG. 8 is a block diagram showing an example of the configuration of the failure determination circuit 23 according to the present embodiment. The failure determination circuit 23 according to the present embodiment is different from the failure determination circuit 23 according to the first embodiment only in the failure determination comparison circuit 25. Hereinafter, a description will be given focusing on parts different from the first embodiment.

  Referring to FIG. 8, the failure determination comparison circuit 25 includes comparison circuits 25a and 25b.

  The comparison circuit 25a measures each gate leakage current input from the first failure detection circuit 22a and the second failure detection circuit 22b. A straight line connecting the gate leakage current and voltage application time of the first failure detection circuit 22a and the gate leakage current and voltage application time of the second failure detection circuit 22b based on the measured gate leakage currents. It is determined whether or not the slope of A is greater than or equal to A6. Thereby, it is determined whether or not the first failure detection circuit 22a has failed.

  Similarly, the comparison circuit 24b measures the gate leakage current input from the second failure detection circuit 22b and the third failure detection circuit 22c. Further, a straight line connecting the gate leakage current and voltage application time of the second failure detection circuit 22b and the gate leakage current and voltage application time of the third failure detection circuit 22c based on each measured gate leakage current. It is determined whether or not the slope of A is greater than or equal to A6. Thereby, it is determined whether or not the second failure detection circuit 22b has failed.

  The determination result signals from the comparison circuits 25 a and 25 b are input to the output circuit 26. The output circuit 26 outputs a failure determination signal to the outside of the failure determination circuit 23 when a signal that determines a failure is input from either of the comparison circuits 25a and 25b. Based on the failure determination signal, the failure detection circuit 22 is notified by a display monitor (not shown), an alarm (not shown) or the like, thereby using a vehicle or the like on which the semiconductor device 1 is mounted. A person, a developer, a designer, etc. of the semiconductor device 1 can exchange the semiconductor device 1 including the actual operation circuit 10. Further, the output circuit 26 predicts the failure time of the actual operation circuit 10 when the signal that determines the failure of the first failure detection circuit 22a is input from the comparison circuit 25a, and the replacement time of the actual operation circuit 10 May be notified by a display monitor or the like.

  Next, the operation of the failure detection apparatus 20 according to this embodiment will be described. Note that the failure detection apparatus 20 according to the present embodiment also has the same operations and effects as those of the first embodiment, and hereinafter, the description will focus on the operation unique to the failure detection apparatus 20 according to the present embodiment.

  In the present embodiment, the load per unit time given to at least one of the failure detection circuits 22 (first failure detection circuit 22a) is equal to or higher than the load per unit time given to the actual operation circuit 10. is there. Thereby, by determining the failure of the failure detection circuit 22a, the failure of the actual operation circuit 10 can be predicted based on the determination.

  Further, the failure detection device 20 determines whether the first failure detection circuit 22a has failed based on the relationship between the electrical characteristics of the first failure detection circuit 22a and the electrical characteristics of the second failure detection circuit 22a. Determine whether or not. Specifically, the slope of a straight line connecting the point represented by the electrical characteristics and cumulative load of the first failure detection circuit 22a and the point represented by the electrical characteristics and cumulative load of the second failure detection circuit 22 Is greater than or equal to the sixth predetermined value A6, it is determined that the first failure detection circuit 22a has failed.

  Here, the effect of the failure determination method by the failure detection apparatus 20 according to the present embodiment will be described.

  FIG. 9 is a diagram for explaining the operation of the failure detection apparatus 20 according to the present embodiment. In FIG. 9A, the vertical axis represents the electrical characteristics of each fault detection circuit 22, the horizontal axis represents the cumulative load of each fault detection circuit 22, and the electrical characteristics and cumulative load of each fault detection circuit 22 are plotted on a graph. It is a figure explaining the time shortening effect | action until failure detection by the failure determination method based on this embodiment shown in FIG. Similarly, in FIG. 9B, the vertical axis represents the electrical characteristics of each failure detection circuit 22, and the horizontal axis represents the cumulative load of each failure detection circuit 22. It is a figure which shows a cumulative load on a graph and shows an example of the failure mode which can be newly detected by the failure determination method which concerns on this embodiment.

  Referring to FIG. 9A, at the top, when the conventional failure determination method (determined as failure when the electrical characteristics are equal to or higher than the failure determination criterion Ist) is used, the first failure detection circuit 22a is It is a figure which shows an example at the time of determining with having failed. The failure mode indicates the case of a wear failure, and a failure is determined when the electrical characteristic of the first failure detection circuit 22a becomes equal to or higher than the failure determination criterion Ist. On the other hand, the middle stage shows a case where the failure determination method according to the present embodiment corresponding to the top diagram is used, and when the slope of the straight line connecting the point 100 and the point 200 is A6 or more. Determine failure. As a result, it becomes possible to detect the time point at which the deterioration progresses earlier with the inclination, and as shown in the figure, it is possible to shorten the time until it is determined that the first failure detection circuit 22a has failed. Can do. Further, it is possible to predict a failure of the actual operation circuit 10 at an early stage based on the determination.

  Further, the number of failure detection circuits 22 may be increased to four or more. The bottom diagram shows a case where the number of failure detection circuits 22 is increased to four. Note that point 400 corresponds to the increased electrical characteristics and cumulative load of the failure detection circuit 22d. By increasing the number of failure detection circuits 22, it is possible to grasp in detail the change in electrical characteristics with respect to the accumulated load that simulates the deterioration of the actual operation circuit 10. Therefore, it becomes possible to detect the time point at which the deterioration progresses earlier, and to shorten the time until it is determined that the first failure detection circuit 22a has failed. Moreover, it becomes possible to predict a failure of the actual operation circuit 10 at an earlier stage based on the determination.

  In addition, referring to FIG. 9B, when the conventional failure determination method is used and the deterioration progress mode as shown in the above diagram is shown, the deterioration is clearly progressing despite the fact that the deterioration progresses. There may be a case where a considerable time is required until the failure determination of the one failure detection circuit 22a, and the failure determination cannot be performed. On the other hand, when the failure determination method according to the present embodiment is used, the failure of the first failure detection circuit 22a is determined based on the slope of the point 100 and the point 200 as shown in the figure below. Even in the case as shown in the figure, the failure of the first failure detection circuit 22a can be determined at an early stage.

[Third Embodiment]
Next, a third embodiment will be described.

  The failure detection device 20 according to the present embodiment is different from the first embodiment in that a failure determination circuit 23 is provided outside the semiconductor device 1. Hereinafter, the same components as those in the first embodiment are denoted by the same reference numerals, and different portions will be mainly described.

  FIG. 10 is a block diagram showing configurations of the failure detection device 20, the semiconductor device 1, and the failure diagnosis device 30 according to the present embodiment.

  Referring to FIG. 10, the failure detection apparatus 20 includes a load circuit 21, a failure detection circuit 22, and a failure determination circuit 23, as in the first embodiment. Unlike the first embodiment, the failure determination circuit 23 is provided in the failure diagnosis device 30 outside the semiconductor device 1.

  The failure diagnosis device 30 is a device that diagnoses a failure or a deterioration state. For example, it is used for a device for monitoring a failure of the semiconductor device 1 provided separately from the semiconductor device 1 or for periodic maintenance of the semiconductor device 1 and connected to the semiconductor device 1 with a cable or the like at the time of maintenance. An apparatus for diagnosing the presence or absence of a failure.

  The failure diagnosis apparatus 30 includes a failure determination circuit 23, a failure diagnosis unit 31 and the like.

  The failure diagnosis unit 31 receives an output signal such as a failure mode determination result and / or a failure determination result from the failure determination circuit 23. The failure diagnosis unit 31 may display a failure mode determination result or the like on a display unit (not shown) of the failure diagnosis device 30 based on an output signal of the failure determination circuit 23 or may perform more detailed failure diagnosis. For example, the output data from the failure determination circuit 23 at the time of past maintenance can be stored historically, configured to be communicable with the outside, and receiving failure information of the same product as the semiconductor device 1, etc. The failure mode, failure cause, failure time, etc. of the semiconductor device 1 may be diagnosed comprehensively.

  Even when the failure determination circuit 23 is provided outside the semiconductor device 1 as in the present embodiment described above, the same operations and effects as in the first embodiment are achieved.

  In the present embodiment, the failure determination circuit 23 of the failure detection device 20 according to the first embodiment is provided outside the semiconductor device 1. However, the failure detection device 20 according to the second embodiment is replaced with the failure detection device 20 according to the second embodiment. You may comprise similarly.

  As mentioned above, although the form for implementing this invention was explained in full detail, this invention is not limited to this specific embodiment, In the range of the summary of this invention described in the claim, various Can be modified or changed.

  In each embodiment described above, the number of failure detection circuits 22 is three, but may be four or more. In this case, the failure mode can be determined by arbitrarily selecting three failure detection circuits 22 and predicting the failure mode of the actual operation circuit 10, and the load per unit time given by the load circuit 21 is larger. Therefore, it is preferable to predict the failure mode using the three failure detection circuits 22. Further, in addition to determining which of the failure modes, detailed progress of deterioration can be analyzed.

  Moreover, in each embodiment mentioned above, although the failure detection apparatus 20 estimates the failure mode and failure of the actual operation circuit 10, you may predict either a failure mode or a failure.

  Further, in each of the above-described embodiments, the failure detection device 20 predicts a failure mode caused by the gate oxide film of the MOS transistor included in the actual operation circuit 10, but the failure mode caused by other circuit elements, etc. It may be predicted, or failure modes caused by a plurality of circuit elements may be predicted. For example, the failure detection apparatus 20 may predict a failure mode of the actual operation circuit 10 due to the wiring in the actual operation circuit 10 that deteriorates due to the migration phenomenon. In this case, each failure detection circuit 22 includes a wiring having the same structure as the wiring in the actual operation circuit 10, and the failure determination circuit 23 predicts a failure mode or the like by measuring a resistance value of the wiring as an electrical characteristic. can do.

DESCRIPTION OF SYMBOLS 1 Semiconductor device 10 Actual operation circuit 20 Failure detection device 21 Load circuit 22 Failure detection circuit 22a First failure detection circuit 22b Second failure detection circuit 22c Third failure detection circuit 23 Failure determination circuit

Claims (11)

A failure detection device that predicts a failure mode of an actual operation circuit provided in a semiconductor device,
At least three failure detection circuits having the same structure as the actual operation circuit;
A load circuit that applies a load to each of the failure detection circuits, and a load circuit that applies a load so that the load per unit time applied to each of the failure detection circuits is different;
A failure determination circuit that measures electrical characteristics of each of the failure detection circuits and predicts a failure mode of the actual operation circuit based on the electrical characteristics; and
Fault detection device. The failure modes include initial failure, accidental failure, and wear failure,
The failure detection apparatus according to claim 1. The at least three failure detection circuits are:
A first failure detection circuit;
A second fault detection circuit in which a load per unit time given by the load circuit is smaller than that of the first fault detection circuit;
A third failure detection circuit having a load per unit time given by the load circuit smaller than the second failure detection circuit;
The failure determination circuit includes:
Based on the relationship between the electrical characteristics of the first failure detection circuit, the electrical characteristics of the second failure detection circuit, and the electrical characteristics of the third failure detection circuit, Predicting failure modes,
The failure detection device according to claim 2. The failure determination circuit includes:
The vertical axis represents the electrical characteristics of each of the failure detection circuits, and the horizontal axis represents the cumulative load given by the load circuit of each of the failure detection circuits.
The point represented by the electrical characteristics of the first failure detection circuit and the cumulative load provided by the load circuit, and the electrical characteristics of the second failure detection circuit and the cumulative load provided by the load circuit. And the slope of the straight line connecting the point represented is equal to or greater than a first predetermined value, and
When the difference between the electrical characteristics of the second failure detection circuit and the electrical characteristics of the third failure detection circuit is equal to or less than a second predetermined value,
The failure mode of the actual operation circuit is predicted to be an initial failure or an accidental failure,
The failure detection apparatus according to claim 3. The failure determination circuit includes:
Furthermore, when the cumulative load provided by the load circuit of the second failure detection circuit is less than a third predetermined value,
The failure mode of the actual operation circuit is determined to be an initial failure,
The failure detection device according to claim 4. The failure determination circuit includes:
Furthermore, when the cumulative load given by the load circuit of the second failure detection circuit is greater than or equal to a third predetermined value,
The failure mode of the actual operation circuit is predicted to be an accidental failure,
The failure detection apparatus according to claim 4 or 5. The failure determination circuit includes:
The vertical axis represents the electrical characteristics of each of the failure detection circuits, and the horizontal axis represents the cumulative load given by the load circuit of each of the failure detection circuits.
The point represented by the electrical characteristics of the first failure detection circuit and the cumulative load provided by the load circuit, and the electrical characteristics of the second failure detection circuit and the cumulative load provided by the load circuit. And the slope of the straight line connecting the point represented is not less than the fourth predetermined value, and
The point represented by the electrical characteristic of the second failure detection circuit and the cumulative load provided by the load circuit, and the electrical characteristic of the third failure detection circuit and the cumulative load provided by the load circuit. When the slope of a straight line connecting the represented point is equal to or greater than a fifth predetermined value,
The failure mode of the actual operation circuit is predicted to be a wear failure,
The failure detection apparatus according to any one of claims 3 to 6. The load circuit is
A load is applied to each failure detection circuit so that a load per unit time given to at least one of the failure detection circuits is equal to or higher than a load per unit time given to the actual operation circuit. ,
The at least three failure detection circuits are:
One fault detection circuit in which a load per unit time given by the load circuit is equal to or higher than a load per unit time given to the actual operation circuit;
A load per unit time given by the load circuit is smaller than the one fault detection circuit, and other fault detection circuits,
The failure determination circuit includes:
Based on the relationship between the electrical characteristics of the one fault detection circuit and the electrical characteristics of the other fault detection circuit, it is determined whether or not the one fault detection circuit is faulty,
Based on the determination, the failure of the actual operation circuit is predicted,
The failure detection apparatus according to any one of claims 1 to 7. The failure determination circuit includes:
The vertical axis represents the electrical characteristics of each of the failure detection circuits, and the horizontal axis represents the cumulative load given by the load circuit of each of the failure detection circuits.
The point expressed by the electrical characteristic of the one fault detection circuit and the cumulative load given by the load circuit, and the electrical characteristic of the other fault detection circuit and the cumulative load given by the load circuit. When the slope of a straight line connecting the represented point is equal to or greater than a sixth predetermined value,
The one fault detection circuit is determined to be faulty,
The failure detection device according to claim 8. The actual operation circuit and each of the failure detection circuits are:
Including a MOS transistor,
The failure detection device according to any one of claims 1 to 9. Of each of the failure detection circuits, at least one is a redundant circuit of the actual operation circuit,
The failure detection apparatus according to any one of claims 1 to 10.

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