CN112635658A - Method for preparing magnetic random access memory - Google Patents
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- CN112635658A CN112635658A CN201910908469.8A CN201910908469A CN112635658A CN 112635658 A CN112635658 A CN 112635658A CN 201910908469 A CN201910908469 A CN 201910908469A CN 112635658 A CN112635658 A CN 112635658A
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Abstract
The invention provides a preparation method of a magnetic random access memory, which comprises the following steps: forming a through hole penetrating through the insulating medium layer on the insulating medium layer and filling a conductive material; sequentially laminating a magnetic tunnel junction bottom electrode layer and a magnetic tunnel junction functional layer on the insulating medium layer and the conductive material; performing first etching on the magnetic tunnel junction functional layer and the magnetic tunnel junction bottom electrode layer according to a target pattern and etching to the lower surface of the magnetic tunnel junction bottom electrode layer to form a pattern groove, a patterned magnetic tunnel junction functional layer and a patterned magnetic tunnel junction bottom electrode layer, wherein the patterned magnetic tunnel junction functional layer and the patterned magnetic tunnel junction bottom electrode layer completely cover the through hole, and redeposited materials generated by the first etching are gathered in the pattern groove; and performing second etching on the insulating medium layer and the redeposited material according to the target pattern so that the redeposited material is not in conductive contact with the magnetic tunnel junction functional layer. The preparation method of the magnetic random access memory can avoid the short circuit of the magnetic tunnel junction functional layer.
Description
Technical Field
The invention relates to the technical field of magnetic memories, in particular to a preparation method of a magnetic random access memory.
Background
In the etching process of the magnetic tunnel junction, the causes of the short circuit phenomenon mainly comprise the functional layer pinhole effect, the defects of the protective film and the influence of generated redeposition conductive substances, wherein the proportion of the short circuit phenomenon caused by the redeposition phenomenon is the highest.
The re-deposition is generated inevitably in the magnetic tunnel junction etching process because the etching and the re-deposition are carried out simultaneously, and the re-deposition is mainly from a metal conductive mixture formed by etching a magnetic tunnel junction metal layer and a magnetic functional layer and can be attached to the periphery of a magnetic tunnel junction structural layer to cause the rapid reduction of the equivalent resistance of the structural layer and cause the occurrence of a short circuit phenomenon.
Disclosure of Invention
The preparation method of the magnetic random access memory can reduce the short circuit phenomenon of the magnetic memory device in the etching process of the magnetic tunnel junction.
The invention provides a preparation method of a magnetic random access memory, which comprises the following steps:
providing an insulating medium layer, forming a through hole penetrating through the insulating medium layer on the insulating medium layer, and filling a conductive material in the through hole;
sequentially laminating a magnetic tunnel junction bottom electrode layer and a magnetic tunnel junction functional layer on the insulating medium layer and the conductive material, and controlling the magnetic tunnel junction bottom electrode layer and the conductive material to be electrically conducted;
carrying out first etching on the magnetic tunnel junction functional layer and the magnetic tunnel junction bottom electrode layer according to a target pattern and etching the magnetic tunnel junction functional layer and the magnetic tunnel junction bottom electrode layer to the lower surface of the magnetic tunnel junction bottom electrode layer so as to form a pattern groove, a patterned magnetic tunnel junction functional layer and a patterned magnetic tunnel junction bottom electrode layer, wherein the patterned magnetic tunnel junction functional layer and the patterned magnetic tunnel junction bottom electrode layer completely cover the through hole, and redeposition materials generated by the first etching are gathered in the pattern groove;
and carrying out secondary etching on the insulating medium layer and the redeposited material according to the target pattern so as to prevent the redeposited material from being in conductive contact with the magnetic tunnel junction functional layer.
Optionally, before providing the insulating medium layer, the method further includes:
providing a bottom conducting layer, and sequentially laminating an etching barrier layer and an insulating medium layer on the bottom conducting layer; the via further penetrates the etch stop layer.
Optionally, before the first etching, the method further includes:
sequentially laminating a metal mask layer and an oxide mask layer on the magnetic tunnel junction functional layer;
and pre-etching the oxide mask layer and the metal mask layer according to the target pattern to form a pattern.
Optionally, after the second etching is completed, the method further includes:
forming a protective layer on the side wall of the graph formed by the pre-etching, the first etching and the second etching and the upper surface of the oxide mask layer;
and controlling the forming temperature of the protective layer to be 200-300 ℃, and controlling the forming thickness of the protective layer to be 10-50 nm.
Optionally, the forming of the insulating dielectric layer includes:
providing one or a combination of more of SiO2, SiON, SiN or SiCN as a forming material of the insulating medium layer;
controlling the forming thickness of the insulating medium layer to be 20-100 nm; and controlling the forming temperature of the insulating medium layer to be 200-300 ℃.
Optionally, the etching depth of the second etching is 30% to 100% of the thickness of the insulating medium layer.
Optionally, the characteristic size of the through hole is 20-40 nm, and the depth-to-width ratio is 2-10.
Optionally, the material of the etching barrier layer includes one or a combination of several of SiN, SiC, SiCN, SiOC, and TiN; the thickness of the etching barrier layer is 5-30 nm.
Optionally, the second etching is ion beam etching or reactive ion etching,
CH3OH + Ar, CO/NH3+ Ar or C2H5OH + Ar are used as reaction gases in the reactive ion etching;
the ion beam etching adopts one or a combination of more of Ar, Kr or Xe as a plasma source.
Optionally, the first etching method is ion beam etching, and the plasma source of the ion beam etching is one or a combination of Ar, Kr and Xe.
According to the preparation method of the magnetic random access memory, the through hole with smaller characteristic dimension is prepared in the insulating medium layer, and the edge of the magnetic tunnel junction graph is arranged outside the edge of the through hole, so that in the second etching process, only the insulating medium of the insulating medium layer is etched without damaging the conductive material filled in the through hole, and the second etching can be smoothly realized. In addition, in the preparation method of the magnetic random access memory, the over-etching space can be increased due to the thicker insulating medium layer, the redeposited material generated in the second etching process is the insulating medium material, the height of the redeposited material is reduced, and the short circuit of the magnetic tunnel junction function layer caused by the first deposited material can be effectively prevented. And in the re-etching process of the insulating medium layer, the generated re-deposition is the re-deposition of the insulating medium material, so that the short circuit of the magnetic tunnel junction functional layer can not be caused.
The preparation method of the magnetic random access memory has high adaptivity, can be directly matched with the existing process of a factory production line, does not cause overlarge influence and change, can be directly adopted, and greatly reduces the implementation difficulty. In addition, the magnetic random access memory prepared by the preparation method of the magnetic random access memory can obtain great improvement on the efficiency of controlling short circuit.
Drawings
FIG. 1 is a schematic structural diagram of a magnetic random access memory according to an embodiment of the present invention after an insulating dielectric layer is formed;
FIG. 2 is a schematic structural diagram of a method for manufacturing a magnetic random access memory according to an embodiment of the present invention after filling a conductive material in a via hole;
FIG. 3 is a schematic structural diagram of a magnetic random access memory according to an embodiment of the present invention after a first etching process is performed;
FIG. 4 is a schematic structural diagram of a magnetic random access memory according to the embodiment of the present invention after a second etching process is completed;
FIG. 5 is a schematic diagram of a second etching position obtained by optical emission spectroscopy according to the method for manufacturing a magnetic random access memory of the embodiment of the present invention;
FIG. 6 is a silicon element signal spectrum diagram of a method for manufacturing a magnetic random access memory according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of a second etching position obtained by time-based control according to the method for manufacturing a magnetic random access memory of the embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the invention, the target pattern refers to a pattern after the etching of the magnetic tunnel junction functional layer is finished. In the present invention, the upper and lower directions are relative directions, and not specific, the description will be given by taking the relative positions of the insulating medium layer and the magnetic tunnel junction functional layer as an example, and the insulating medium layer is located below the magnetic tunnel junction functional layer relative to the magnetic tunnel junction functional layer.
An embodiment of the present invention provides a method for manufacturing a magnetic random access memory, as shown in fig. 1 to 7, the method including:
s1, providing an insulating dielectric layer 330, forming a via penetrating through the insulating dielectric layer 330 on the insulating dielectric layer 330, and filling the via with a conductive material 340.
Optionally, the step S1 includes the following specific steps:
s11: providing a bottom conductive layer 310, and sequentially forming an etching barrier layer 320 and an insulating medium layer 330 on the bottom conductive layer 310;
as an optional implementation manner of the step, the material of the etching barrier layer 320 is TiN, SiN, SiC, SiCN or SiOC, and the thickness is 5-30 nm. The introduction of the etch stop layer 320 can precisely control the etch stop position to prevent the bottom conductive layer 310 from being damaged by over etching during the second etching, and can also be used to stop the upward diffusion of the bottom conductive layer 310.
As an alternative embodiment of this step, the bottom conductive layer 310 may be made of any conductive material, preferably a metal material, and further preferably copper.
As an optional way of this step, the thin film material of the insulating dielectric layer 330 includes, but is not limited to, SiO2, SiON, SIN, or SICN, etc., the thickness is 20-100 nm, the deposition temperature is 200-300 ℃, and the deposition method may be an atomic layer deposition process or a chemical vapor deposition process. Thicker insulating dielectric layer 330 has increased the over-etching space in order not only to raise the whole height of magnetic tunnel junction bottom electrode 350 layer and magnetic tunnel junction functional layer, also makes redeposition material 360 can keep away from the magnetic tunnel junction functional layer simultaneously, has reduced the short circuit phenomenon because redeposition material 360 leads to, introduces one deck thicker bottom insulating dielectric layer 330 in addition, has increased the etching space of magnetic tunnel junction, also helps promoting the homogeneity of magnetic tunnel junction sculpture appearance.
S12: forming a through hole on the insulating medium layer 330 and the etching barrier layer 320; in the process of forming the through hole, controlling the characteristic size of the through hole to be smaller than that of the target graph;
as an optional implementation manner of the step, a pattern with a smaller characteristic size is photoetched on the insulating medium layer 330, then the etching barrier layer 320 and the etching opening are performed, CFx gas is used as a plasma source for etching the insulating medium layer 330, and the CFx gas includes but is not limited to CF4, C4F6, C4F8, SF6 and the like, the characteristic size range of the etched through hole is 20-40 nm, and the etching depth-to-width ratio is 2-10. Methods of fabricating smaller feature size vias include, but are not limited to, deep ultraviolet lithography, multiple mask lithography, and the like. In the embodiment, the characteristic dimension of the through hole is required to be controlled within a range of 20-40 nm, and the dimension of the through hole is relative to the characteristic dimension morphology after the magnetic tunnel junction is etched, in order to achieve the effect of more etching amount, the characteristic dimension of the through hole needs to be always smaller than the characteristic dimension of the magnetic tunnel junction.
S13: the via is filled with a conductive material 340, and the conductive material 340 is in electrical contact with the bottom conductive layer 310.
As an alternative embodiment of this step, the through hole may be filled with any conductive material, preferably, a metal material, and further preferably, copper.
S2, sequentially laminating a magnetic tunnel junction bottom electrode 350 layer and a magnetic tunnel junction functional layer on the insulating medium layer 330 and the conductive material 340; the layer of magnetic tunnel junction bottom electrode 350 is controlled to make electrical conduction with the conductive material 340.
The step S2 includes the following steps:
s21: the filled conductive material 340 and the insulating dielectric layer 330 are planarized.
S22: and preparing a magnetic tunnel junction bottom electrode 350 layer on the conductive material 340 and the insulating medium layer 330 which are subjected to the planarization treatment, ensuring that the magnetic tunnel junction bottom electrode 350 layer is electrically conducted with the conductive material 340, and depositing a magnetic tunnel junction functional layer on the magnetic tunnel junction bottom electrode 350 layer.
As an optional implementation manner of this step, the magnetic tunnel junction functional layer mainly consists of a free layer 390, a tunneling layer 380 and a reference magnetic layer 370; the structural features include, but are not limited to, a single-layer barrier structure and a double-layer barrier structure.
S3, performing first etching on the magnetic tunnel junction functional layer and the magnetic tunnel junction bottom electrode layer 350 according to the target graph and etching to the lower surface of the magnetic tunnel junction bottom electrode layer 350 to form a graph groove, a graphical magnetic tunnel junction functional layer and the magnetic tunnel junction bottom electrode layer 350, wherein the graphical magnetic tunnel junction functional layer and the graphical magnetic tunnel junction bottom electrode layer 350 completely cover the through hole, and redeposition materials 360 generated by the first etching are gathered in the graph groove.
Optionally, a hard mask is used to complete the first etching, and the specific steps are as follows:
s31: a metal mask layer 410 and an oxide mask layer 420 are sequentially formed on the magnetic tunnel junction functional layer.
As an alternative to this step, the metal mask layer, the material includes, but is not limited to, Ta, TiN, or Ta/Ru/Ta, etc. The oxide hard mask is made of materials including but not limited to SiO2, SiN, SiC, SiON, SiCN, etc., wherein the metal mask layer 410 has a thickness of about 40-60 nm, and the oxide mask layer 420 has a thickness of about 40-60 nm.
S32: the oxide mask layer 420 and the metal mask layer 410 are pre-etched according to the target pattern to form a pattern.
As an optional implementation manner of this step, a photoresist is coated on the surface of the metal mask layer 410, and the photoresist is exposed and developed to make a target pattern appear on the photoresist, and the oxide mask layer 420 and the metal mask layer 410 are etched to form a pattern by using an ion beam etching method. The etching process adopts CFx-based plasma for etching, including but not limited to CF4, C4F8, C4F6 or SF6, and the feature size control range of the patterns of the oxide mask layer 420 and the metal mask layer 410 is 40-80 nm.
S33: and carrying out first etching on the magnetic tunnel junction functional layer and the magnetic tunnel junction bottom electrode 350 layer according to the patterns on the oxide mask layer 420 and the metal mask layer 410 to form a pattern.
As an optional implementation manner of this step, according to the patterns on the oxide mask layer 420 and the metal mask layer 410, the free layer 390, the tunneling layer 380, the reference layer 370, and the magnetic tunnel junction bottom electrode 350 layer are sequentially etched, and finally, an etching end point is stopped at an interface between the magnetic tunnel junction bottom electrode 350 and the insulating medium layer 330. The purpose of this etching step is to form the bulk morphology and profile of the magnetic tunnel junction, and the redeposited material 360 formed at this time is mainly concentrated around the functional layer of the magnetic tunnel junction. Since the first etching and the generation of the redeposition material 360 are performed simultaneously, the redeposition material 360 is inevitably generated in the first etching process, and mainly comes from a metal conductive mixture formed by etching the magnetic tunnel junction bottom electrode 350 layer and the magnetic tunnel junction functional layer, and if the redeposition material is not processed, the redeposition material is attached to the periphery of the magnetic tunnel junction functional layer structure layer, so that the equivalent resistance of the magnetic tunnel junction functional layer is sharply reduced, and the short circuit phenomenon is caused. The second etching in the step S4 is required to avoid the occurrence of the short circuit phenomenon.
Alternatively, in this embodiment, the ion beam etching method is used, and the etching is performed by physical bombardment using dissociated plasma of Ar, Kr, or Xe, etc., while the endpoint determination of the first etching is performed using optical emission spectroscopy, which requires that the endpoint of the first etching be stopped on the surface of the insulating dielectric layer 330.
In the present embodiment, the steps S32 and S33 may be performed continuously or stepwise, depending on the actual conditions in the manufacturing process.
S4, performing a second etching on the insulating dielectric layer 330 according to the target pattern, so that the redeposited material 360 does not conductively contact the magnetic tunnel junction functional layer.
As an alternative embodiment of this step, as shown in FIGS. 5-6, this embodiment employs an angularly adjustable ion beam etching apparatus for etching, including but not limited to physical bombardment with plasmas of elements such as Ar, Kr, or Xe; and (3) carrying out endpoint monitoring by using an optical luminescence spectrum (monitoring the light intensity of a luminescence wave band between 284.5 nm and 286.5nm, and carrying out average noise reduction, wherein the spectrum acquisition time is 2 seconds, and the average number of times of noise reduction is 10). Taking silicon as an insulating dielectric layer material as an example, the variation of the silicon element signal spectral line with the etching time is shown in fig. 6.
In this embodiment, the position where the etching insulating dielectric layer 330 stays may be set by capturing an end point by an optical emission spectrum, and the etching is required to stop on the etching stop layer 320. As shown in fig. 5, the points in the insulating dielectric layer in the figure are respectively a first depth, a second depth and a third depth from top to bottom. The first, second and third depths correspond to Sipeak1, Sipeak2, Sipeak3 in the spectral lines of fig. 6. Specifically, when the thickness of the insulating dielectric layer 330 is etched, the position determination conditions may be set to be different according to Sipeak1, Sipeak2, and Sipeak 3.
As another optional implementation manner of this step, in this implementation manner, reactive ion etching is used, including but not limited to CH3OH + Ar, CO/NH3+ Ar, or C2H5OH + Ar, and meanwhile, an etching stop layer (not shown in the figure) is added on the insulating dielectric layer 330 as a first etching end layer, a material of the stop layer may be a conductive metal material such as boron, magnesium, tantalum, ruthenium, or tungsten, and a method of fixing an etching time in an etching process below the etching stop layer, that is, a method of fixing an over-etching amount is adopted to adjust an etching depth of the insulating dielectric layer 330. As shown in fig. 7, three points of the insulating dielectric layer in the figure are OE1, OE2 and OE3 from top to bottom, which correspond to different etching depths at different second etching time points. For example, OE1 is defined as an etch depth of 60s, OE2 is an etch depth of 90s, and OE3 is an etch depth of 120 s.
Optionally, in the two embodiments, the end point of the second etching is in a depth range of 30% to 100% of the thickness of the insulating dielectric layer 330.
In the etching process, the main etching object is the insulating medium layer 330, the etching control variable is the staying position of the etched insulating medium layer 330, low energy and small angle bombardment are mainly adopted in the etching process, the formed redeposition material 360 can be in a proper position, the energy is reduced, the redeposition material in the etching can be reduced, the function of cleaning the side wall of the magnetic tunnel junction function layer can be achieved, the position of the formed redeposition material 360 is further moved downwards, conductive materials in the redeposition material 360 are concentrated around the insulating medium layer 330, and short circuit of the magnetic tunnel junction function layer caused by the redeposition material 360 can be avoided. In this step, since the metal material is mainly generated in the first etching process, and the main cause of short circuit is adhesion of the metal material, the redeposition material 360 generated by the first etching is mainly controlled not to contact with the magnetic tunnel junction function layer. The redeposition material generated by the second etching is mainly insulating material, so that the insulating material can be in contact with the magnetic tunnel junction functional layer.
As an optional implementation manner of this embodiment, after the second etching is completed, the sum of the final remaining thicknesses of the oxide mask layer 420 and the metal mask layer 410 is controlled to be 40 to 60 nm.
As an optional implementation manner of this embodiment, after the second etching is finished, a dielectric protection film is deposited along the periphery of the pattern of the oxide mask, the metal mask, the magnetic tunnel junction functional layer, the magnetic tunnel junction bottom electrode 350, and the insulating dielectric layer 330, the material of the protection film includes but is not limited to SiN, SiCN, SiOC, and the like, the deposition process may be performed by using an atomic layer deposition method or a plasma enhanced chemical vapor deposition method, in the growth process, the temperature control interval is 200 to 300 ℃, and the final growth thickness is controlled between 10 to 50 nm. Further alternatively, the precursors or reactants in the formation of the protective layer include, but are not limited to, SiH4, K5, TSA, or other materials.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. A method for manufacturing a magnetic random access memory is characterized in that: the method comprises the following steps:
providing an insulating medium layer, forming a through hole penetrating through the insulating medium layer on the insulating medium layer, and filling a conductive material in the through hole;
sequentially laminating a magnetic tunnel junction bottom electrode layer and a magnetic tunnel junction functional layer on the insulating medium layer and the conductive material, and controlling the magnetic tunnel junction bottom electrode layer and the conductive material to be electrically conducted;
carrying out first etching on the magnetic tunnel junction functional layer and the magnetic tunnel junction bottom electrode layer according to a target pattern and etching the magnetic tunnel junction functional layer and the magnetic tunnel junction bottom electrode layer to the lower surface of the magnetic tunnel junction bottom electrode layer so as to form a pattern groove, a patterned magnetic tunnel junction functional layer and a patterned magnetic tunnel junction bottom electrode layer, wherein the patterned magnetic tunnel junction functional layer and the patterned magnetic tunnel junction bottom electrode layer completely cover the through hole, and redeposition materials generated by the first etching are gathered in the pattern groove;
and carrying out secondary etching on the insulating medium layer and the redeposited material according to the target pattern so as to prevent the redeposited material from being in conductive contact with the magnetic tunnel junction functional layer.
2. The method of manufacturing a magnetic random access memory according to claim 1, wherein: before providing the insulating medium layer, the method further comprises the following steps:
providing a bottom conducting layer, and sequentially laminating an etching barrier layer and an insulating medium layer on the bottom conducting layer; the via further penetrates the etch stop layer.
3. A method of manufacturing a magnetic random access memory as claimed in claim 2, wherein: before the first etching, the method further comprises the following steps:
sequentially laminating a metal mask layer and an oxide mask layer on the magnetic tunnel junction functional layer;
and pre-etching the oxide mask layer and the metal mask layer according to the target pattern to form a pattern.
4. A method of manufacturing a magnetic random access memory as claimed in claim 3, wherein: after the second etching is finished, the method also comprises the following steps:
forming a protective layer on the side wall of the graph formed by the pre-etching, the first etching and the second etching and the upper surface of the oxide mask layer;
and controlling the forming temperature of the protective layer to be 200-300 ℃, and controlling the forming thickness of the protective layer to be 10-50 nm.
5. The method of manufacturing a magnetic random access memory according to claim 2, wherein: the forming of the insulating medium layer comprises the following steps:
providing one or a combination of more of SiO2, SiON, SiN or SiCN as a forming material of the insulating medium layer;
controlling the forming thickness of the insulating medium layer to be 20-100 nm; and controlling the forming temperature of the insulating medium layer to be 200-300 ℃.
6. A method of manufacturing a magnetic random access memory as claimed in claim 1, wherein: the etching depth of the second etching is 30% -100% of the thickness of the insulating medium layer.
7. The method of manufacturing a magnetic random access memory according to claim 1, wherein: the characteristic size of the through hole is 20-40 nm, and the depth-to-width ratio is 2-10.
8. The method of manufacturing a magnetic random access memory according to claim 6, wherein: the etching barrier layer material comprises one or a combination of more of SiN, SiC, SiCN, SiOC or TiN; the thickness of the etching barrier layer is 5-30 nm.
9. A method of manufacturing a magnetic random access memory as claimed in claim 1, wherein: the second etching adopts ion beam etching or reactive ion etching,
CH3OH + Ar, CO/NH3+ Ar or C2H5OH + Ar are used as reaction gases in the reactive ion etching;
the ion beam etching adopts one or a combination of more of Ar, Kr or Xe as a plasma source.
10. A method of manufacturing a magnetic random access memory as claimed in claim 1, wherein: the first etching method is ion beam etching, and the plasma source of the ion beam etching is one or a combination of more of Ar, Kr or Xe.
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11930720B2 (en) | 2021-04-28 | 2024-03-12 | Institute of Microelectronics, Chinese Academy of Sciences | Voltage control of SOT-MRAM for deterministic writing |
Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9450180B1 (en) * | 2015-11-03 | 2016-09-20 | International Business Machines Corporation | Structure and method to reduce shorting in STT-MRAM device |
CN108232009A (en) * | 2016-12-21 | 2018-06-29 | 上海磁宇信息科技有限公司 | A kind of method for making magnetic RAM |
CN108232007A (en) * | 2016-12-21 | 2018-06-29 | 上海磁宇信息科技有限公司 | A kind of method that gas cluster ion beam trims the magnetic tunnel junction after being etched |
CN108232002A (en) * | 2016-12-14 | 2018-06-29 | 上海磁宇信息科技有限公司 | A kind of method for preparing magnetic tunnel junction array |
US20190103554A1 (en) * | 2017-08-23 | 2019-04-04 | Everspin Technologies, Inc. | Method of manufacturing integrated circuit using encapsulation during an etch process |
CN109713120A (en) * | 2017-10-25 | 2019-05-03 | 上海磁宇信息科技有限公司 | A kind of manufacturing method of magnetic RAM cell array and peripheral circuit line |
CN109713006A (en) * | 2017-10-25 | 2019-05-03 | 上海磁宇信息科技有限公司 | A method of making magnetic RAM cell array and its peripheral circuits |
CN109994600A (en) * | 2017-12-29 | 2019-07-09 | 上海磁宇信息科技有限公司 | A kind of production method of magnetic RAM |
CN110071214A (en) * | 2019-05-07 | 2019-07-30 | 江南大学 | A kind of lithographic method for reducing etch product side wall and depositing again |
CN110098321A (en) * | 2018-01-30 | 2019-08-06 | 上海磁宇信息科技有限公司 | A method of preparing magnetic RAM conductive hard mask |
CN110112288A (en) * | 2019-06-14 | 2019-08-09 | 上海磁宇信息科技有限公司 | A method of preparing magnetic tunneling junction cell array |
-
2019
- 2019-09-24 CN CN201910908469.8A patent/CN112635658A/en active Pending
Patent Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9450180B1 (en) * | 2015-11-03 | 2016-09-20 | International Business Machines Corporation | Structure and method to reduce shorting in STT-MRAM device |
CN108232002A (en) * | 2016-12-14 | 2018-06-29 | 上海磁宇信息科技有限公司 | A kind of method for preparing magnetic tunnel junction array |
CN108232009A (en) * | 2016-12-21 | 2018-06-29 | 上海磁宇信息科技有限公司 | A kind of method for making magnetic RAM |
CN108232007A (en) * | 2016-12-21 | 2018-06-29 | 上海磁宇信息科技有限公司 | A kind of method that gas cluster ion beam trims the magnetic tunnel junction after being etched |
US20190103554A1 (en) * | 2017-08-23 | 2019-04-04 | Everspin Technologies, Inc. | Method of manufacturing integrated circuit using encapsulation during an etch process |
CN109713120A (en) * | 2017-10-25 | 2019-05-03 | 上海磁宇信息科技有限公司 | A kind of manufacturing method of magnetic RAM cell array and peripheral circuit line |
CN109713006A (en) * | 2017-10-25 | 2019-05-03 | 上海磁宇信息科技有限公司 | A method of making magnetic RAM cell array and its peripheral circuits |
CN109994600A (en) * | 2017-12-29 | 2019-07-09 | 上海磁宇信息科技有限公司 | A kind of production method of magnetic RAM |
CN110098321A (en) * | 2018-01-30 | 2019-08-06 | 上海磁宇信息科技有限公司 | A method of preparing magnetic RAM conductive hard mask |
CN110071214A (en) * | 2019-05-07 | 2019-07-30 | 江南大学 | A kind of lithographic method for reducing etch product side wall and depositing again |
CN110112288A (en) * | 2019-06-14 | 2019-08-09 | 上海磁宇信息科技有限公司 | A method of preparing magnetic tunneling junction cell array |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11930720B2 (en) | 2021-04-28 | 2024-03-12 | Institute of Microelectronics, Chinese Academy of Sciences | Voltage control of SOT-MRAM for deterministic writing |
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