TW569386B - Method for forming dual damascene - Google Patents

Abstract

The present invention discloses a method for forming dual damascene, which includes the following steps: forming a dielectric layer on the semiconductor substrate; next, forming a penetrated opening in the via hole on the dielectric layer; forming a second photoresist with trench patters on the dielectric layer; etching the dielectric with the second photoresist as the mask to form a trench; removing the residual photoresist; conducting the first plasma etching with the first pressure for a first period of time; then, conducting the second plasma etching with the second pressure for a second period of time to remove a portion of dielectric layer on the sidewall above the opening of the via hole; in which, the first pressure and the second pressure are between 10 to 200 mTorr, and the first pressure is smaller than the second pressure; next, conducting the third plasma etching with the oxygen and nitrogen mixture to remove the impurities on the via hole and the trench sidewall; and, finally, depositing the conductive material to form the dual damascene interconnect structure.

Description

569386 V. Description of the invention (1) Field of the invention The present invention relates to a semiconductor process technology, and more particularly to a method for manufacturing a dual damascene (dua 1 damascene) with a via hole with an enlarged opening. BACKGROUND OF THE INVENTION In the development of semiconductor interconnect technology, in conjunction with the dual damascene interconnect structure developed by the copper process, a via hole can be made in advance on the dielectric layer of the semiconductor substrate. ) And interconnect pattern trenches, and then fill the via holes and interconnect pattern trenches with a conductive copper metal material, and cooperate with a chemical mechanical polishing process to remove excess copper metal over the dielectric layer. A metal contact plug and a metal interconnection structure are formed at the same time, thereby achieving the effect of simplifying the process steps. The dual damascene process can be divided into two types, one is to first form a via hole opening and then a wire trench opening, and the other is to form a wire trench opening and then a via hole opening. The following = FIGS. 1A to 1F illustrate a conventional “damascene structure” method of forming a via hole opening and then a wire trench opening. As shown in FIG. 1A, after the formation of both—for example, copper or I Lu's semiconductor substrate 丄: of / belongs to the interconnect structure 102 and then-the gasification of the second substrate 202 is formed first-the dielectric through the second dielectric layer 108. As a stop layer for money engraving. In FIG. 1B, during the photolithographic etching process of the dielectric line, the photoresist layer ho is compounded at the dielectric layer 108 = U8, and enters the domain to form a dielectric hole opening 112. Then—corresponds to the interconnect structure 1 The area 2 is the photoresist layer 11 and the dielectric layer 108.

Page 4 〇503-8201TWf; TSMC2001-1759; Peggy.ptd 569386 V. Description of the invention (2) After the mask is continued to etch the silicon nitride layer 106 and the dielectric layer 10 and the resistive layer no, a dielectric layer is formed. Full penetration = first as shown in Figure 1C. j 1 接. Refer to FIG. 1D, cover a photoresist layer 114 on the dielectric layer 108, and use a lithography process to define a pattern 116 of a conductive trench to be formed on the photoresist layer 丨 4. Part of the photoresist material will remain in the interlayer hole 2a, forming a photoresist plug 1 1 4 a. Then, the trench pattern of the photoresist layer 114 is used as a curtain, and etching is performed to etch the gasified stone layer 10 of the second stop layer 1 to form a wire ‘groove’, as shown in the figure. At this time, the photoresist plug 114a which is too high may cause the bottom of the trench 116 to be incompletely etched, and a residue of the dielectric material may be generated. / Finally, the silicon nitride etch stop layer in the wire trench is removed, as shown in FIG. 1F. After the metal conductive material is filled in and the excess conductive material is removed, a metal plug and a metal interconnect structure are formed. According to the above method, the sidewalls of the trenches 116 and the vias 112 are formed in steep shapes. In this case of high aspect rati〇: It's half as long! The accumulation of institutional processes is more obvious. ❿The high aspect ratio makes it difficult to deposit barrier layers and fill copper. At the same time, because of the steepness of the double-inlaid structure, the gaps or holes are easily formed during the process of sedimentation resistance, barrier layer and copper metal filling, which reduces the reliability of the interconnected structure. In addition, the photoresist material used to define the trench pattern will fill the openings of the vias formed previously to form photoresist plugs 114 &, and react with the dielectric layer etchant to generate by-products, such as polymerization Residues, 0503-8201TWf; TSMC200M759; Peggy.ptd page 5 569386 5. Description of the invention (3) Unremovable 'and the formation of a so-called fence on the upper side wall of the via 丨 2 ) 'As shown in Figure 1 j ?. This fence will hinder the filling of the conductive metal material, and it is easy to form the irregular shape of the metal wire in the dual damascene pattern. In addition, the existence of the 'barrier' will also cause the current to flow through the wires and the plugs of the interlayer vias, thereby forming electron migration holes, which reduces the reliability of the product. These problems will seriously affect the quality of the interconnect (consisting of multilayer wires and via plugs). In US Patent No. 6211068, a dual damascene process is proposed, which mainly forms an additional silicon oxynitride layer on the surface of the dielectric layer as an anti-reflection coating ', which can make the shape of the trench openings better controlled during trench etching. U.S. Patent No. 639 9483 teaches a dual damascene process, which mainly forms an anti-reflection layer to cover the inner side wall of the via hole after forming the via hole and before forming the trench opening, thereby forming a better profile. In the double-embedded structure, U.S. Patent No. 640347 1 discloses a dual-damascene process, mainly after forming a via hole and a trench opening, and then removing an etching stop layer between the via hole and the semiconductor bottom. The upper side wall of the meso-cavity in the double damascene opening is enlarged by heat treatment, and is more uniform and smooth, which is helpful for subsequent filling. Negative. However, for the dual-town private process in which a via hole is formed first and then a trench, the above technology still cannot simultaneously increase the fence between the upper side wall of the via hole and the same hole between the via hole and the trench. '' BRIEF SUMMARY OF THE INVENTION In view of the problems encountered in the above dual damascene process, one of the present invention

0503-8201TWf; TSMC200M759; Peggy.ptd ^ β pages " ----- 569386

The purpose is to provide a double-mosaic junction with an enlarged upper opening, which is helpful for the following another object of the present invention. The method uses the occurrence of a peach pinch in the via hole and the trench side. The formation method of the structure can fill the via hole with a conductive material. In order to provide a pre-treatment of the formation wall of the dual mosaic structure to avoid the dual mosaic system, a method for forming a dual mosaic structure according to the present invention, the steps are as follows. First, a semiconductor substrate is provided, and a dielectric layer is formed on the semiconductor substrate. A first light having a pattern of a hole in the dielectric layer is formed on the dielectric layer and the first photoresist is used as a mask. The dielectric layer is etched to form a through hole. Through hole opening. Continue to form a second photoresist having a trench pattern on the dielectric layer and use the second photoresist as a mask, and then etch a predetermined depth of the dielectric layer to form a trench. After removing all the remaining photoresist, the first plasma is etched for a first time with a first pressure, and the second plasma etching is performed for a second time with a second pressure to remove the upper side wall of the via of the via. Part of the dielectric layer, wherein the first pressure and the second pressure are between 10 and 200 millitorr, and the first pressure is less than the second pressure. Then, a third plasma etching is performed with a mixed gas of oxygen and nitrogen to remove impurities in the via hole and the sidewall of the trench. Finally, a conductive material is deposited to fill the vias and trenches of the interlayer to form a double damascene interconnect structure. According to another method of forming a dual mosaic structure according to the present invention, the steps are briefly described as follows. On a semiconductor substrate having a conductive layer or element structure, a first etch stop layer, a first dielectric layer, a second etch stop layer, a second dielectric layer and a cover layer are sequentially formed. Then, a first photoresist having a pattern of a via hole is formed on the cover layer, and the cover layer, the second dielectric layer, the first etch stop layer and the first dielectric layer are etched by using the first photoresist as a mask to form

II

II I

0503-820lTWf »TSMC2001-1759 * Peggy.ptd Page 7 569386 V. Description of the invention (5) Fully penetrating via hole opening. Pattern the second photoresist, and form a trench layer to a second etch stop layer on the cover layer to form: the etched cover layer and the second dielectric are subjected to the first pressure at the first pressure ^: After the photoresist is removed, a second plasma etching is performed for a period of time, and then a part of the second side wall—a layer of electrical layer $ m—divided the opening of the interlayer hole at 10 to 100 millitorr, and the second two -A first pressure and a second pressure, a mixed gas of nitrogen gas and a first pressure. Afterwards, in the presence of oxygen, Jie Guangdong and the cover were engraved with f-plasma to remove the first etch stop layer at the bottom of the trench and the first etch stop layer at the fourth electro-P in the above process. And the bottom layer of the interstitial hole: ί layer. Finally, a conductive material is deposited to fill the interstitial holes and trenches' to form a dual damascene interconnect structure. In the above method, through the second low-voltage plasma etching, the dielectric layer opened at the upper part of the dielectric hole can be removed moderately to form a dielectric hole with a larger opening, and the possible barrier phenomenon can be removed at the same time. By using a third plasma etching mixed with radon and oxygen, the impurities in the side walls of the dual damascene openings can be removed to create a via hole with a rounded angle, which is helpful for the subsequent interconnection of the two barrier layers and conductive metal materials. filling. Detailed description of the invention The present invention provides a dual damascene process in which a via hole opening (via ho 1 e) is formed before a wire trench opening is formed. The dual damascene process can be used in conjunction with the application of plasma etching. A via hole structure with a large opening and a smooth angle is formed, and the plasma etching process is performed to avoid the formation of a fence by the residual impurities. The first embodiment and implementation

569386

Example 2 details the method flow of forming a dual mosaic structure according to the present invention. Embodiment 1 The method flow for forming a mosaic structure according to the present invention will be described in detail below with reference to FIGS. 2A to 2G. First, referring to FIG. 2A, a semiconductor substrate 200 is provided, in which a conductive layer structure 202 including interconnects is electrically connected to a semiconductor element (not shown). On the semiconductor substrate 200, a chemical vapor deposition (CVD) method is used to deposit a fluorine-doped silicon dioxide (FSG) material as the first dielectric layer 204, and the thickness thereof may be between 1K and 20K. Around 4900 Angstroms. The dielectric layer can also be made of plasma silicon oxide, low dielectric constant spin-on glass, tetraethoxy silicon glass, lin-doped silicon oxide, fluorinated silicon oxide (F — s 丨 &), vermiculite glass (PSG), undoped silica glass (HDp — USG) deposited by high density plasma, silicon oxide (HDp — Si〇2) deposited by high density plasma, SACVD The deposited oxide stone, and the silicon oxide deposited by ozone-tetraethoxy stone burn (〇3_TEOS), etc., the present invention is not limited thereto. A nitride nitride (SiN) layer with a thickness of 10 to 1000 angstroms can be optionally formed on the first dielectric layer 204 by a chemical vapor deposition (CVD) method as #etching. The stop layer 20 6 has a preferred thickness of about ο Angstroms to control the depth of the trenches to be formed later. Then, by chemical vapor deposition, a fluorine-doped silicon dioxide (FSG) material is deposited on the etch stop layer 206 as the first layer. The thickness of the second dielectric layer 208 ′ may be between 11 (to 2 (2) 1 (, preferably “about Angstroms.”) And the second dielectric layer 208 may be the same as or different from the first dielectric layer 208.

569386

Then referring to FIG. 2B, a photoresist layer 21 with a via pattern is formed on the second dielectric layer 208 by a lithography process, and the photoresist layer 21 is used as a screen cover. The second dielectric is etched first. The electric layer 2 08 is formed to form a via hole pattern 2 1 2. Next, referring to FIG. 2C, using the photoresist layer 210 and the second dielectric layer 208 as a mask 'continue to etch the silicon nitride etch stop layer 20 and the first dielectric layer 204' below to form The via hole 212 is completely penetrated, and the bean layer structure 202 is exposed. 8 / Next, referring to FIG. 2D, after removing the photoresist 210, a photolithography process is continued to form a photoresist 214 having a trench pattern on the second dielectric layer 208. When the photoresist 214 is filled in the via hole 212, it will remain in the via hole 212 to form a photoresist plug 214a. Generally speaking, the photoresist plug 214a can protect the underlying conductive layer structure 202 from being damaged by etching. In addition, the photoresist plug 21 "also protects the sidewall of the via hole from being etched during subsequent trench etching to maintain its vertical sidewall. However, the top of the photoresist plug 2 丨" The two dielectric layers 208 are in contact, so that during trench etching, the top of the photoresist plug 214a and the sidewall of the dielectric layer 208 form impurities that are not easily removed, which may cause a fence after the trench I is etched. Then, the trench pattern of the photoresist 214 is used as a mask, and the second dielectric layer 208 is etched until the etching stop layer 206 is formed to form a trench opening 216. Next, the remaining photoresist is removed, including photoresist 214 and photoresist plug 21 ", and then the trench opening 216 and the interlayer hole opening as shown in Fig. 2E are formed. However, as shown in Fig. 2E, The aspect ratio hole opening 2 1 2 will be created, and the filling condition of the continuous conductive material is not @, so then the first plasma etching is performed with a low voltage into the lamp first. The pressure range is controlled to 10 ~ 200 millitorr ear

569386 V. Description of Invention (8)

Utorr), preferably 40 millitorr, and the last gas selection ratio is highly etchable for the dielectric layer 204 material, rather than the etching gas of the etching stop layer 206, such as Octafluorocyclobutane (C4F8), carbon monoxide (C0) and chlorine (Ar) are preferably in the ratio of 丨: 丨: to 50.0 · 10000 ·· 1000. The ratio is 10: 200: 400. The energy of the electric source of the electro-etching is between 1 and 2000 watts, preferably about 1 500 watts. While the force is adjusted back but still kept in a relatively low pressure range, such as between 丨 〇 ～ 丨 〇 Torr, the better is adjusted to 100 mTorr, the rest of the conditions are with the first slurry etching phase 1¾, more than 3 The second plasma etch is controlled in about 7 seconds. The etching results are shown in the first figure. 'As can be seen in Figure 2F, by controlling the pressure of the electropolymerization in the low-pressure state, the free path of the ions is longer, so it can be carried in for a while without affecting the opening of the upper trench 216. size. The selection ratio of the substrate is only the electrical layer 204 of the upper side wall of the via hole, and avoids direct etching as an etching step. At the same time, if the photoresistive plug = "layer hole contour blocking phenomenon" in the above process, the etching gas can be simultaneously produced to produce a larger hole contour of the male W T. 电 电 # 二During the fabrication process, the trench 216 and the interlayer hole m-side soil form impurities or residues, so the third gas is polymerized to remove impurities and shape the surface of the electrical layer. This third electrical engraving can Plasma etching is performed at a mixing ratio of • to · 6 for 5 to 100 seconds, preferably 0503-8201TWf; TSMC2001-1759; Peggy.ptd page 11 569386 5. Description of the invention (9) " ~ The mixing ratio of oxygen and nitrogen is 1.6, and it is processed under the pressure of 1 Q millitorr for about 15 seconds, and the energy range of its plasma source is between 丨 and "⑽Watt, the better About 3 7 5 watts. With the good etching selection ratio of the oxygen / nitrogen plasma etching, the impurities on the side walls of the trench 216 and the dielectric hole 212 can be effectively removed without damaging the dielectric layers 204 and 2008, and the etching termination ^ 2 0 6 'can maintain the integrity of the side wall of the double mosaic opening. / Next, a fourth plasma etching is performed to remove the etching stop layer 206 at the bottom of the trenches 2 and 6 which is in contact with the via 212. This step can be performed by general plasma etching which generally removes the nitride etch stop layer 206. For example, plasma etching using tetrafluoromethane (CD and nitrogen (N2) at a mixing ratio of 1: 1 to ϊ00: 100) is performed for 1 to 100 seconds. Preferably, tetrafluoromethane (CF4) and nitrogen (W Mix at M: 30 and perform 40 seconds at 80 millitorr to remove the exposed end layer 206 in the exposed part of Shi Xi. The result is as shown in Figure 2G, with a large opening and a smooth angle. Via hole 2 1 2. Finally, as shown in FIG. 2H, 'Diffusion barrier layers (not shown) such as button (Ta), nitride button (TaN' ⑽ 'or It is commonly used in the conventional process, such as TiN, chemical vapor deposition (CVD), physical vapor phase, six-dimensional ^^】 +., Cut porous phase deposition (PVD), Or electroplating deposition method (EleCtrplatplat) is used to make copper and gold to fill the interstitial holes 212 and trenches 216 on the barrier layer. It is better to go and bite the heart: flatten f 'available ionization is now a thunder plasma (IMP) First deposit a layer of & snn lRnn on the substrate. A seed layer (not shown) of about d 〇 〇 ～ 1 5 〇0 A per year, and then complete the copper tomb mine by electroplating M ^ Sunburst Layer I Take 70 for the deposition of the conductive layer. Then the double-mosaic inner 踝 Mian reverse ankle structure that leads to the conductive layer structure 202 is formed. Because the upper opening of the via 2 2 is large and the angle is rounded, and i ^ M # I 1 on the door, 1 side of the electrical layer has been removed

569386 V. Description of the invention (ίο) The quality of the conductive material is better, and it can form a good interconnect structure. / Embodiment 2 The method flow of another dual damascene structure according to the present invention will be described in detail below with reference to FIGS. 3A to 3H. First, referring to FIG. 3A, a semiconductor substrate 300 is provided, which includes the conductive layer structure 3 of the interconnect. 2 Electrically connect the semiconductor elements (not shown). On the semiconductor substrate 300, a first etch stop layer 30 is formed first to prevent the conductive layer structure 302 from being exposed to oxygen or other corrosive chemical processes. The material of the first etch stop layer 303 may be silicon nitride (SiN), the formation method thereof may be plasma enhanced chemical vapor deposition (PECVD), and the thickness thereof may be about 10 angstroms to 1,000 angstroms, preferably It is 500 Angstroms. Then, a first dielectric stop layer 304 is deposited on the first etch stop layer 303 by chemical vapor deposition (CVD) as a first dielectric layer 304, and the thickness thereof may be between 1,000 and 1,000. To 200,000 Angstroms (in), preferably about 4 Angstroms. Dielectric can also be used with polycrystalline oxide oxide, dielectric constant spin-on glass, tetraethoxy, Shixi glass, Λ-doped oxide Xi, fluorinated oxygen cutting (F-Si〇2), stone filling Xibo? !! SJ) Oxygen-cutting oxide deposited on un-doped silica glass (HDP-USG) deposited by plasma of the same density (method) and oxidized yttrium oxide and ruthenium-tetrasilane deposited on o3-teos Porous fossils are only used in the present invention. Then, on the first dielectric layer 30, #Nitride dry rolling phase deposition (CVD) method with a thickness of 10 to 1,000 angstroms is formed. I fossil evening layer as the second etch stop layer

569386, invention description (U) 306 ', its preferred thickness is about 300 Angstroms. See also Figure 3A, and then use chemical vapor deposition to deposit fluorinated silicon dioxide (SiO2) on the worm etched and stop layer 306. The material is used as the second dielectric layer 308. Its thickness may be between 1000 and 2000 Angstroms (in). Preferably it is about 4300 Angstroms. The second dielectric layer 308 may use the same or different dielectrics as the first dielectric layer 304. An electrical material is formed on the second dielectric ^ 3 08, such as a chemical vapor deposition method to form a silicon nitride or silicon oxynitride (with a thickness of 100 to 5000 angstroms) Preferably, silicon oxynitride is formed into a cover layer of about 1200 angstroms. Next, referring to FIG. 3B, a photoresist layer 310 having a via hole pattern is formed on the cover layer 309, and the photoresist layer 310 is used as a curtain. First, the cover layer 309 and the second dielectric layer 308 are etched to form a dielectric hole pattern 312. Next, referring to FIG. 3C, the photoresist layer 310, the cover layer 309, and the second dielectric layer 308 are used as a mask, and the etching is continued The silicon nitride second etch stop layer 306 and the first dielectric layer 304 below it, and the first etch stop layer 303 form a through dielectric layer The interlayer hole opening 312 of 308 and 304. Next, referring to FIG. 3D, after removing the photoresist 31, the photolithography process is continued to form a photoresist 3 with a trench pattern on the cover layer 309. The photoresist 314 is When the via hole 312 is filled, a photoresist plug 314a remains in the via hole 312. The photoresist plug 314a can protect the underlying structure of the via hole 312 from being damaged by etching. In addition, the photoresist The plug 3 丨 4a also protects the sidewall of the via 312 from being etched during subsequent trench contacting, and maintains its vertical sidewall with θ. However, the top of the photoresist plug 3 丨 4a is easy to contact The second dielectric layer 308 is in contact with the top of the photoresist plug 314a during trench etching

0503-8201TWf; TSMC2001-1759; Peggy.ptd page 14 569386 V. Description of the invention (12) and " electrical layer 3 0 8 side walls form impurities that are not easy to remove, resulting in the formation of fences | fences after the engraving (fence) . Then, the trench pattern of the photoresist 3 1 4 is used as a screen cover, and the second dielectric layer 308 is etched to the etching stop layer 3 06 to form a trench opening 3 1 6. After removing the remaining photoresist, including photoresist 3 1 4 and photoresist plug 3 1 4 a, a trench opening 3 1 6 and a via hole 3 1 2 as shown in FIG. 3E are formed. However, as shown in FIG. 3E, the openings of the vias with a high aspect ratio 3 1 2 will cause a poor filling condition of the subsequent conductive material. Therefore, the first plasma etching is performed at a low voltage first. The pressure range is controlled to about 10 to 200 millitorr (mtorr), preferably 40 millitorr, and the etching choice of the etching gas is higher than that for the dielectric layer 304 material. Without affecting = termination, the etching gas of 306, such as octafluorocyclobutane (dagger), carbon monoxide (C0), and argon (Ar), the ratio can be between 丨: 丨: 丨 to 5〇: 1〇 〇〇: 〇 00, the preferred ratio is 10: 2000: 400. The plasma source for plasma etching has an energy between 1 and 200 watts, preferably about 1500 watts. While = hour? More than 3 seconds, preferably about 7 seconds. Next, the electric pressure engraved ~ but still / held at the lower pressure range ❿ is between 10% t, the better is adjusted to 100 millitorr, the other conditions are with f: plasma The etching is the same, and the second electric etching is performed for more than 3 seconds, and the better one is also controlled at about 7 seconds. The results are shown in the figure. It can be seen from the 3F diagram that by controlling the low-pressure state of the margin, the free path of the white Λe Jin Dao She Zhou 010 ^ D is longer, so it can enter the via 312 for etching without affecting the upper trench. The critical dimension of the slot m opening. And because the adjustment of the etching gas selection m L ^ ”is hard and the selection ratio, so only the upper side of its via hole is etched

569386 V. Description of the invention (13) " --------- The first dielectric layer 304 of the wall, and avoid directly engraving =: = 6yu as the ending layer of the last name. If the blocking phenomenon is caused by the photoresist plug 3i4a in the above process, ▼ the etching gas-and at the same time to support / form ° contour of the large via hole shown in Figure 3f . In order to avoid the formation of impurities or residues on the sidewalls of the trenches 3, 6 and the interlayer holes 2 during the above-mentioned etching process, @: =: = poly㈣, in order to remove the impurities and the heart circle Si to 1. 6 of? Person f. Plasma etching can be performed by plasma etching with oxygen and nitrogen at a mixed σ ratio of 2: 1 to 1.6. 5 to 100 cases' processing gas at a pressure of 110 = Torr and 375 Watts / Nitrogen plasma etching is good: I and oxygen on the side wall of the via 312 ::; engraved; = closed: = groove outline, and the etching stop layer 306, can be guaranteed without injury To the dielectric layer 304 and sexual. The complete side wall of the double-inlay opening of the 1 indicator is then subjected to a fourth plasma etching to remove the 312-connected #etch stop layer 3G6 11) the bottom layer and the layer

The general electrical destruction of the etch stop layer 306 can be performed in the following steps: generally remove nitrogen (CF4) and nitrogen (N2) m: 41〇 /: 1〇〇 仃, and use 1 to 100 sintering process second. The better one is to mix the Teflon 30 with tetrafluorodi: ratio and perform it at 80 mTorr ;;: pure gas (N2) to 3 (silicon etching stop layer 30 6). As a result, the bare part is removed. Like the opening, and the angle of the interstitial hole 3 丨 2 rounds are not, forming a more

569386 V. Description of the invention (14) The stop layer 306 and the bottom of the via 312 are removed, and the blocking layer 303 is filled in the via 312 and the trench 316. The double-mosaic interconnection of the conductive layer structure 302 is turned on. structure. For electrical materials, the upper opening of the shape 3Ϊ2 is large and the angle is smooth, and the two-layer hole removes impurities, so the filling effect of subsequent conductive materials is better. Although I have achieved good results, although the present invention is disclosed as i in the preferred embodiment, it is not the present invention. Anyone skilled in the art will not deviate from the scope defined in the appended application patents. "巳 0503-820lTWf; TSMC2001-1759; Peggy.ptd p.17 569386 The diagram is briefly explained. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, the following detailed description will be given in conjunction with the attached drawings. Figures 1A to 1F show a conventional method of a dual damascene structure in which a via hole opening is formed and then a wire trench opening is formed. Figures 2A to 2H show an embodiment according to the present invention In one, a method flow for forming a dual damascene structure. Figures 3A to 3H show a method flow for forming a dual damascene structure in accordance with a second embodiment of the present invention. Symbols indicate a semiconductor substrate ~ 100, 20 0 '300; Conductive layer structure ~ 102, 202, 302; Etching stop layer ~ 106, 206, 303, 306; Dielectric layer ~ 104, 108, 204, 208, 304, 3 08; Curtain layer ~ 309; Photoresistor ~ 110, 114, 220, 214, 310, 314; Photoresistive plugs ~ 114a, 214a, 314a; Via openings ~ 11 2, 2 1 2, 3 1 2; Trench openings ~ 11 6, 2 1 6, 3 1 6.

0503-8201TWf; TSMC2001-1759; Peggy.ptd page 18

Claims (1)

569386 VI. Scope of patent application 1. A method for forming a dual damascene structure, comprising the following steps: providing a semiconductor substrate; forming a dielectric layer on the semiconductor substrate; and forming a dielectric layer pattern on the dielectric layer A first photoresist; using the first photoresist as a screen cover, etching the dielectric layer to form a completely penetrating via hole; forming a second photoresist having a trench pattern on the dielectric layer; The second photoresist is a mask, and the dielectric layer is etched to a predetermined depth to form a trench; all remaining photoresists are removed; the first plasma etching is performed with a first pressure for a first time, and continued with Performing a second plasma etching at a second pressure for a second time to remove a part of the dielectric layer on the upper side wall of the opening of the dielectric layer, wherein the first pressure and the second pressure are between 10 and 200 millitorr, And the first pressure is less than the second pressure; performing a third plasma etching with a mixed gas of oxygen and nitrogen to remove impurities in the via hole and the sidewall of the trench; and depositing a conductive material to fill the via layer Hole with the groove, shaped One pair of the damascene interconnect structure. 2. The method for forming a dual damascene structure according to item 1 of the scope of the patent application, wherein the dielectric layer is fluorine-doped silicon glass (FSG). 3. The method for forming a dual damascene structure according to item 1 of the scope of the patent application, wherein the reaction gases for the first and second plasma etching include octafluorocyclobutane (C4F8), carbon monoxide (CO), and argon ( Ar). 4. Forming a dual mosaic structure as described in item 3 of the scope of patent application 0503-8201TWf; TSMC2001-1759; Peggy.ptd Page 19 569386 6. Method of applying for a patent, in which the mixing ratio of octafluorocyclobutane (C4F8), carbon monoxide (C0) and argon (Ar) is between 1 ··· 1: 1 to 50: 100: 100. 5. The method of forming a dual damascene structure according to item 4 of the scope of the patent application, wherein the first pressure of the first plasma etching is about 40 mTorr, and the second plasma etching of the second The pressure is about 丨 00 millitorr. 6. The method for forming a dual damascene structure according to item 4 of the scope of the patent application, wherein the plasma source energy of the first and second plasma etching is between 1 and 200,000 watts. 7. The method of forming a dual damascene structure according to item 1 of the scope of the patent application, wherein the third plasma etching is performed by plasma etching with oxygen and nitrogen at a mixing ratio of 2: 1 to 1: 6 from 5 to 10. 〇 seconds. 8. The method of forming a dual damascene structure according to item 7 of the scope of the patent application, wherein the plasma source energy of the third plasma etching plasma etching is between 2000 watts. 9. A method of forming a dual damascene structure, including the following steps: providing a semiconductor substrate; and sequentially forming a first etch stop layer, a first dielectric layer, a second etch stop layer, and a first etch stop layer on the semiconductor substrate. Two dielectric layers and a cover layer; forming a first photoresist having a hole pattern of the dielectric layer on the cover layer; and using the first photoresist as a screen cover, etching the cover layer, the second dielectric layer, the A first etch stop layer and the first dielectric layer to form a completely penetrating via hole; forming a second photoresist with a trench pattern on the cover layer; 0503-8201TWf i TSMC2001-1759 ♦ Peggy.ptd Page 20 569386 VI. Patent application scope Dielectric layer to Xi = The second photoresist is a curtain cover, and the cover layer and the first etch stop layer are etched to form a Trench; remove all remaining photoresist; sign a first pressure to perform the first plasma etching for a first time, and continue a second pressure engraving with a pressure for a second time to remove the via hole ^ _ Part of the side wall of the first-dielectric layer, wherein the first pressure and the = Dingbao force is between 10 ~ 20 millitorr, and the first pressure is less than the second pressure and mixed with oxygen and nitrogen A third plasma etching is performed by the gas to remove impurities in the μ " layer hole and the sidewall of the trench. A fourth plasma etching is performed to remove the second etch stop layer at the bottom of the trench and the bottom of the via hole. A first etched final soil layer; and, depositing a conductive material to fill the via hole and the trench to form a mosaic interconnect structure. 10. The method for forming a dual damascene structure as described in item 9 of the patent scope of Shenying ', wherein the first and second dielectric layers are fluorine-doped silicon glass (FSG). 11. The method for forming a dual damascene structure according to item 9 of the scope of the patent application, wherein the first and second etch stop layers are silicon nitride (s i n). 1 2. The method of forming a dual damascene structure according to item 9 of the scope of the patent application, wherein the cover layer is silicon oxynitride (SiON). 1 3 · The method for forming a dual mosaic structure according to item 9 of the scope of the patent application, wherein the reaction gas of the first and second plasmas includes octafluorocyclobutane (C4F8), carbon monoxide (c) and Mixed gas of argon (Ar). 1 4 · Form a double mosaic structure as described in item 13 of the scope of patent application 0503-8201TWf; TSMC200M759; Peggy.ptd page 21 569386 6. Method of patent application 'Among them, the mixing ratio of octafluorocyclobutane (c4f8), tritium carbon oxide (c0) and argon (A r) The mixing ratio of fluorocyclobutadiene (q dagger), carbon monoxide (C 0) and rat gas (Ar) is between 1 and 50: 1000: 1000 of fal 〇 '1 5 · According to item 14 of the scope of patent application The method for forming a double-inlay structure, wherein the first pressure of the first plasma etching is about 40 mTorr 'and the second pressure of the second plasma | worming is about 100 mTorr . 16 · The method for forming a dual damascene structure according to item 1 of the scope of the patent application, wherein the plasma source energy of the first and second electro-etching is between i and 2000 watts. 1 7 · The method for forming a dual damascene structure according to item 9 of the scope of the patent application, wherein the third plasma etching is performed by plasma etching with oxygen and nitrogen at a mixing ratio of 2: 1 to 1: 6 5 to 1 〇〇 seconds. 18. The method for forming a dual mosaic structure according to item 9 of the scope of the patent application, wherein the plasma source energy of the third plasma is between 1 and 2000 watts. 19. The method of forming a dual damascene structure according to item 9 of the scope of the patent application, wherein the fourth plasma etching is performed by using tetrafluoromethane (CF4) and nitrogen by 1: 1 to 1 0: 1 0 0 Plasma etching is performed at a mixing ratio for 1 to 100 seconds. 0503-8201TWf; TSMC200M759: Peggy.ptd Page 22