CN112585759A

CN112585759A - Novel superlattice cell structure with reduced programming current and thermal crosstalk for 3D cross-point memory and manufacturing method

Info

Publication number: CN112585759A
Application number: CN202080003785.1A
Authority: CN
Inventors: 刘峻
Original assignee: Yangtze River Advanced Storage Industry Innovation Center Co Ltd
Current assignee: Yangtze River Advanced Storage Industry Innovation Center Co Ltd
Priority date: 2020-11-24
Filing date: 2020-11-24
Publication date: 2021-03-30
Also published as: WO2022109773A1

Abstract

A new cell structure for a 3D cross-point memory is proposed that allows for reduced programming current and reduced thermal cross-talk compared to prior art 3D cross-point memory cell structures. In one embodiment of the new cell structure, each Phase Change Memory (PCM) memory cell is formed using a superlattice cell structure. PCM memory cells may be formed using a superlattice made of germanium telluride (GeTe). A larger distance between adjacent memory cells causes less thermal crosstalk. PCM cells having a superlattice cell structure allow for less current density requirements than current state-of-the-art memory cells.

Description

Novel superlattice cell structure with reduced programming current and thermal crosstalk for 3D cross-point memory and manufacturing method

Technical Field

The present disclosure relates generally to three-dimensional electronic memories and, more particularly, to reducing programming current and thermal crosstalk in adjacent memory cells.

Background

Planar memory cells are scaled to smaller dimensions by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of memory cells approaches the lower limit, planar processes and fabrication techniques become challenging and costly. As such, the storage density for planar memory cells approaches an upper limit. Three-dimensional (3D) memory architectures are able to address density limitations in planar memory cells.

Phase Change Memory (PCM) is a non-volatile solid-state memory technology that employs reversible, thermally-assisted switching of phase change materials, such as chalcogenide compounds (e.g., GST (germanium-antimony-tellurium), between states having different resistances. The basic memory cell ("cell") can be programmed into several different states or levels, which exhibit different resistance characteristics. Programmable cell states can be used to represent different data values, allowing information to be stored.

PCM cells are programmed or erased by heating themselves to induce an amorphous or crystalline state to represent 1's and 0's. The programming current is proportional to the size and cross-sectional area of the PCM cell. In a single-level PCM device, each cell may be SET to one of two states, a "SET" state and a "RESET" state, allowing each cell to store one bit. In the RESET state (which corresponds to the bulk amorphous state of the phase change material), the resistance of the cell is very high. By heating to a temperature above its crystallization point and subsequent cooling, the phase change material can be converted to a fully crystalline state of low resistance. This low resistance state provides the SET state of the cell. If the cell is subsequently heated to a high temperature above the melting point of the phase change material, the material will revert to a fully amorphous RESET state upon rapid cooling.

Due to the nature of thermal self-heating, cross talk (cross talk) can occur when programming neighboring cells. Crosstalk is the interference between signals. Due to the scaling of process technologies, the pitch between adjacent interconnects is shrinking. Switching of one signal may affect the other signal. In the worst case this may result in a change of value of another element or may delay signal transitions affecting the timing. This situation is classified as a signal integrity problem.

In addition, large programming current requirements also result in large programming voltage requirements due to IR drop (IR voltage current resistance). Reading and writing of data in PCM cells is accomplished by applying appropriate voltages to the phase change material through a pair of electrodes associated with each cell. In a write operation, the resulting programming signal causes the phase change material to be joule heated to an appropriate temperature to induce the desired cell state when cooled. Reading of a PCM cell is performed using cell resistance as a measure of the cell state. The applied read voltage causes a current to flow through the cell, which depends on the resistance of the cell. Thus, measurement of the cell current provides an indication of the programmed cell state. A sufficiently low read voltage is used for the resistance measurement to ensure that the application of the read voltage does not disturb the programmed cell state. Cell state detection may then be performed by comparing the resistance metric to a predefined reference level. The programming current (I) is typically on the order of 100-200 μ A. If the Write Line (WL) and Bit Line (BL) in a cell encounter large resistance and the current is too large, the voltage drop may be large.

When the WL and BL are formed perpendicular to each other, a 3D cross-point memory is formed. The memory cells are formed self-aligned at the intersection of the WL and BL. The memory cell is a vertical square pillar shape having a single material composition.

Thus, there remains a need for memory cells that provide reduced programming current and reduced thermal crosstalk.

Disclosure of Invention

The following summary is included to provide a basic understanding of aspects and features of the disclosure. This summary is not an extensive overview and, thus, it is not intended to identify key or critical elements or to delineate the scope of the disclosure. Its sole purpose is to present concepts in a summary format.

In one aspect, a method for 3D cross point memory is presentedA new cell structure for a memory that allows for reduced programming current and reduced thermal cross-talk as compared to prior art 3D cross-point memory cell structures. In the current new cell structure, each Phase Change Memory (PCM) memory cell is formed using a superlattice cell structure. By using germanium telluride (GeTe), antimony telluride (Sb)₂Te₃) The resulting superlattice material, or another suitable superlattice material, forms a PCM memory cell using self-aligned double patterning (SADP) in both X and Y directions to form a vertical pillar cell having multiple encapsulation layers. Each stack consists of vertical word lines and bit lines. The memory cells are self-aligned to the word lines and bit lines. Patterning for each direction requires two partial etches to form the PCM memory cell. The first etch is complete up to the PCM and is followed by the nitride and oxide encapsulation layers. After encapsulation, a second etch is performed on the ovonic threshold switch stack and a second encapsulation is performed with the nitride layer and the gap filler. Due to the reduced thermal diffusivity of the superlattice cell material, programming current and thermal cross talk are greatly reduced.

In another aspect, a method for forming a new cell structure for a 3D cross-point memory with reduced programming current and reduced thermal cross-talk is disclosed. The method includes forming a cross-point memory array having parallel Bit Lines (BL) and vertical Word Lines (WL). Using GeTe, Sb₂Te₃Or other superlattice materials, using SADP to form vertical pillar cells with multiple encapsulation layers to form memory cells (PCMs). Patterning requires two partial etches to form the PCM. The first etch is followed by a nitrogen/oxygen encapsulation. A second etch is then performed on the Ovonic Threshold Switch (OTS) stack, and followed by nitrogen encapsulation and gap filling. The superlattice cell material has a reduced thermal diffusivity, thereby greatly reducing programming current and thermal crosstalk. A smaller PCM thermal diffusivity results in less current required to program the cell. Since the RESET temperature is lower, less thermal cross talk occurs between cells. Having lower SET and RESET current requirements improves the reliability of the cell. In addition, in the cell manufacturing process, a superlattice is usedThe cell structure provides better protection and less contamination for the PCM and OTS.

In another aspect, a 3D cross-point memory die architecture includes a plurality of memory arrays (tiles) separated by small spaces. A memory array is comprised of a plurality of memory cells (PCMs) made of a superlattice material.

According to one aspect, a three-dimensional memory cell structure includes at least one memory cell stack having a selector, a phase change memory cell, and first and second electrodes. The phase change memory cell is disposed between a first electrode and a second electrode. The phase change memory cell, the selector, and the first and second electrodes each have a dimension relative to a first direction and a second direction. The word lines and bit lines are perpendicular to each other and coupled to the storage cell stack. The phase change memory cells are self-aligned with respect to the word lines and bit lines. The phase change memory cell is a superlattice phase change memory cell structure having a plurality of encapsulation layers, wherein the superlattice phase change memory cell structure includes a nitride and a substrate encapsulation layer and a nitride encapsulation layer on the selector.

Some aspects include a three-dimensional cross-point memory die architecture comprising: a plurality of top arrays or blocks of phase change memory cells, a plurality of bottom arrays or blocks of phase change memory cells, a plurality of bit lines coupled to the top arrays and coupled to the bottom arrays. The plurality of word lines include: a set of top cell word lines coupled to the top array and a set of bottom cell word lines coupled to the bottom array. The top arrays of memory cells are each separated by a first space defined by adjacent phase change memory cells in the top array. The bottom arrays of phase change memory cells are each separated by a second space defined by adjacent phase change memory cells in the bottom arrays.

In another embodiment, a method of forming a three-dimensional memory includes: forming a cross-point memory array having parallel bit lines and vertical word lines; forming a memory cell at an intersection of a word line and a bit line, wherein the memory cell is self-aligned; and germanium telluride (GeTe), antimony telluride (Sb)₂Te₃) Superlattice materialMemory cells are formed using self-aligned double patterning in both horizontal and vertical directions to form vertical pillar cells with multiple encapsulation layers.

Drawings

The foregoing aspects, features and advantages of the present disclosure will be further appreciated when considered with reference to the following description of exemplary embodiments and the accompanying drawings, in which like reference numerals refer to like elements. In describing exemplary embodiments of the present disclosure illustrated in the drawings, specific terminology may be employed for the sake of clarity.

However, aspects of the disclosure are not intended to be limited to the specific terminology used.

Fig. 1A and 1B are isometric views of a prior art multi-section (section) and single section, respectively, of a three-dimensional cross-point memory.

Fig. 2A is a plan view showing a cross section of a three-dimensional cross-point memory of a bottom cell stack, and fig. 2B is a diagram showing abbreviations of layers in the cell stack.

Fig. 3A and 3B are plan views of a three-dimensional cross-point memory with an encapsulation layer according to the embodiment of fig. 2A and 2B, and fig. 3C is a cross-sectional view of a section of fig. 3A.

Fig. 4A and 4B are plan views of a three-dimensional cross-point memory according to the embodiment of fig. 3A and 3B, showing a gap fill layer and chemical mechanical polishing.

Fig. 5A and 5B are plan views of a three-dimensional cross-point memory according to the embodiment of fig. 4A and 4B, showing word line metal deposition.

Fig. 6A and 6B are plan views of a three-dimensional cross-point memory according to the embodiment of fig. 5A and 5B, showing the bottom cell word lines double patterned to form parallel bottom cell word lines perpendicular to the bit lines.

Fig. 7A and 7B are plan views of a three-dimensional cross-point memory according to the embodiment of fig. 7A and 7B, showing encapsulation and gap filling of the cell stack.

Fig. 8 is a plan view of a three-dimensional cross-point memory according to the embodiment of fig. 7A and 7B, showing a second stack of storage cells deposited on top of the stack shown in fig. 7A.

Detailed Description

While specific configurations and arrangements are discussed, it should be understood that this is done for exemplary purposes only. One skilled in the relevant art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to those skilled in the relevant art that the present disclosure may also be used in a variety of other applications.

It is worthy to note that any reference in the specification to "one embodiment," "an exemplary embodiment," "some embodiments," or the like, means only that the embodiment described may include a particular feature, structure, or characteristic, and that such terms are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the relevant art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

In general, terms may be understood at least in part according to usage in context. For example, the term "one or more" as used herein may be used in the singular to describe any feature, structure, or characteristic, or may be used to describe a plural combination of features, structures, or characteristics, depending at least in part on the context. Similarly, terms such as "a," "an," or "the" may also be understood to convey a singular use or to convey a plural use, depending at least in part on the context.

It should be readily understood that the meaning of "above …", "above …" and "above …" herein should be interpreted in the broadest manner such that "above …" means not only "directly on something", but also includes on something with an intermediate feature or layer therebetween, and "above …" or "above …" means not only on or above something, but may also include the meaning of having no intermediate feature or layer therebetween (i.e., directly on something).

Furthermore, spatially relative terms such as "below …," "below …," "lower," "above …," "upper," and the like may be used herein to describe one component or feature's relationship to another component or feature as illustrated in the figures for ease of description. These spatially relative terms are intended to encompass different orientations or directions of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The term "substrate" as used herein may refer to any workpiece on which it is desired to form or process a layer of material. Non-limiting examples include silicon, germanium, silicon dioxide, sapphire, zinc oxide, silicon carbide, aluminum nitride, gallium nitride, spinel, silicon on oxide, silicon carbide on oxide, glass, gallium nitride, indium nitride, aluminum nitride, glass, combinations or alloys thereof, and other solid materials. The substrate itself may be patterned. The added material on top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may comprise a wide range of semiconductor materials including, but not limited to, silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafers.

As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. The extent of the layer may extend over the entire underlying or overlying structure, or it may be less than the extent of the underlying or overlying structure. In addition, a layer may be a region of uniform or non-uniform continuous structure, which may have a thickness less than the thickness of the continuous structure. For example, a layer may be located at any pair of horizontal planes between the top and bottom surfaces of the continuous structure, or at the top and bottom surfaces of the continuous structure. The layers may extend horizontally, vertically, and/or along the tapered surface. The substrate may be a layer, which may include one or more layers, and/or may have one or more layers above and/or below it. The layer may comprise multiple layers. For example, the interconnect layer may include one or more conductors and contact layers (in which contacts, interconnect lines, and/or vias are formed) and one or more dielectric layers.

The term "horizontal" as used herein will be understood to be defined as a plane parallel to the plane or surface of the substrate, regardless of the orientation of the substrate. The term "vertical" shall mean a direction perpendicular to the horizontal as previously defined. Terms such as "above … …," "below … …," "bottom," "top," "side" (e.g., side wall), "high," "low," "upper," "above," and "below" are defined with respect to a horizontal plane. The term "on … …" means that there is direct contact between the elements. The term "above … …" will allow for intervening elements.

As used herein, a material (e.g., a dielectric material or an electrode material) will be considered "crystalline" if it exhibits a crystallinity of greater than or equal to 30% as measured by a technique such as x-ray diffraction (XRD). Amorphous material is considered to be amorphous.

As used herein, the terms "first," "second," and other ordinal words are to be understood to provide a distinction only, and not to limit any particular spatial or temporal order.

As used herein, the term "oxide" of an element will be understood to include additional components in addition to the element and oxygen, including, but not limited to, dopants or alloys. As used herein, the term "nitride" of an element will be understood to include additional components in addition to the element and nitrogen, including, but not limited to, dopants or alloys.

The technology is applied to the field of three-dimensional memories. A general prior art example of a three-dimensional (3D) memory is shown in fig. 1A. Specifically, fig. 1 is an isometric view of a cross section of a three-dimensional cross-point memory. The memory comprises a first layer of memory cells 5 and a second layer of memory cells 10. Between the first level memory cells 5 and the second level memory cells are a number of word lines 15 extending in the X-direction. Above the first level of memory cells 5 are a number of first bit lines 20 extending in the Y-direction and below the second level of memory cells are a number of second bit lines 25 extending in the Y-direction. Furthermore, as can be seen from the figure, the sequential structure of bit line-memory cell-word line-memory cell can be repeated along the Z-direction to achieve a stacked configuration. In any event, the single memory cell can be accessed by selectively activating the word line and bit line corresponding to the cell.

In FIG. 1B, a single cross-section 100 of the cell structure of FIG. 1A is shown. A top cell bit line 110 is shown connected to a top cell stack 150. The stack 150 is composed of several layers, which will be described herein in the context of a modification of this standard stack 150. Perpendicular to top cell bit line 110 are top cell write line 130 and bottom cell write line 140. Connected to the bottom cell write line 140 is a bottom cell stack 160. Parallel to the top cell bit line 110 is a bottom cell bit line 120. The bottom cell bit line 120 is coupled to the bottom cell stack 160. Like the cell stack 150, the cell stack 160 is also composed of several layers. Fig. 1A and 1B illustrate the general structure of a 3D cross-point memory cell, which term is used herein to describe the improvements. Fig. 1A depicts a cross section viewed in the Z (depth) direction. The cross section includes a number of word lines (e.g., word lines 130, 140 extending in an X (horizontal) direction), a number of top cell bit lines (e.g.,

bit lines

110, 120 extending in a Y (vertical) direction and corresponding to memory cells 150 of the top cell array), and a number of bottom cell bit lines (extending in a vertical direction and corresponding to memory cells 160 of the bottom cell array). The word lines, top cell bit lines, and bottom cell bit lines are typically formed according to a 20nm/20nm line/space (L/S) pattern and are formed on a silicon substrate. Further, the memory may employ Complementary Metal Oxide Semiconductor (CMOS) technology.

As described above, a crosstalk problem may occur in the neighboring cells. The present disclosure addresses this problem as well as the problem of reducing the current required for the memory cell. Note that fig. 2A is a plan view of the structure shown in fig. 1B in the Y direction. The three-dimensional cross-point memory shows

exemplary cell stacks

1, 2, and 3. Each stack consists of several layers. The cell stacks are similar in function and construction. For the purposes of describing the materials disclosed herein, like reference numbers in the various figures for common elements indicate like materials and functions of the elements shown and described.

Bottom cell stack deposition is shown in fig. 2A. The

layers

208a and 208b may be tungsten-based compounds or cobalt-based compounds and function as conductors, among other things. According to embodiments, the conductor may be composed of other materials having conductive properties. According to an embodiment, the electrode may be a carbon electrode or any other electrode known to a person skilled in the art. The electrodes may be formed of any convenient conductive material, typically a metallic material (e.g., pure metal or a metal compound, alloy or other mixture) or a doped semiconductor material, such as silicon. Furthermore, although the features described are particularly advantageous for multi-layer cells, in some embodiments, these features may also be applied to advantage in single layer cells.

Layers

205a, 205b, and 205C are a-C or electrode layers. Layer 206 is a Phase Change Memory (PCM) cell made of a superlattice material, which may be germanium telluride (GeTe), antimony telluride (Sb)₂Te₃) Or other suitable superlattice materials with self-aligned double patterns. As shown in fig. 2A, a superlattice material PCM 206 may be disposed between the electrodes in the stack. A selector or ovonic threshold switch 207 is also provided between the electrodes in the stack, as shown in figure 2A. Layer 209 may be a substrate or represent a bottom bitline, depending on the embodiment. The first encapsulation layer 204a deposition for covering

stacks

1, 2 and 3 occurs after the first etch to protect the exposed superlattice phase change memory cells in each stack. A second encapsulation layer 204b deposition for covering

stacks

1, 2 and 3 occurs after the second etch to protect the exposed ovonic threshold switch 207 in each stack and to protect the substrate 209. Gap fillers 210 are placed on the

stacks

1, 2 and 3. Gap fill may be obtained by atomic layer deposition of oxide, Spin On Dielectric (SOD), or flowable Chemical Vapor Deposition (CVD) oxide. Examples of gap filling materials include, but are not limited to: gallium arsenide (GaAs), indium gallium arsenide (InGaAs), gallium nitride (GaN), aluminum nitride (AlN), cadmium sulfide (CdS), cadmium selenide (CdSe), cadmium telluride (CdTe), zinc sulfide (ZnS), lead sulfide (PbS), and lead selenide (PbSe), as well as cobalt-based compounds and any combination thereof. FIG. 2B is a block diagram illustrating a system for various of the aspects described hereinDiagram of layer abbreviations.

As recognized by the present techniques described herein, existing configurations, as illustrated in fig. 1A and 1B, are inefficient in their use of storage areas (or "storage assets"). This configuration is susceptible to crosstalk from neighboring cells, causing interference to the memory cells. In addition, as the demand for additional memory increases, the power requirements increase dramatically as the number of cells increases. The disclosed new configurations and materials provide reduced cross talk and power requirements for the memory cells. The new configuration includes a reduced size PCM relative to the selector and/or the electrodes in their respective stacks. New materials require a lower RESET temperature which in turn reduces the current requirements to improve cell reliability. This configuration and material also provides better protection for the PCM and OTS and prevents contamination during cell fabrication. This configuration and cross-sectional area can be seen, for example, starting from the process shown in fig. 3A and 3B to fig. 9.

FIG. 3A is a cross-sectional view taken along line 3B-3B from FIG. 3B, with FIG. 3B showing the various layers depicted in FIG. 3A. Fig. 3B is a plan view of the cell stacks 1, 2, and 3. In this figure, a nitride layer 203 is disposed on top of an electrode 205 a. Examples of such materials include metal nitrides (e.g., TiN, TiAlN, TaN, BN), metal oxynitrides (e.g., TiON), metal silicides (e.g., PtSi), semiconductors (e.g., silicon or germanium) (doped and undoped), reduced metal oxides (e.g., TiOx (x <2 represents reduction), metals (e.g., W, Ni, Co, or carbon based materials), a first etch occurs to etch through the superlattice PCM 206, and stops on the electrodes 205b to form parallel lines according to embodiments, the etch may be accomplished, for example, using hydrogen peroxide or ammonium hydroxide, hi fig. 3C, an encapsulation layer 204a deposition is shown covering the

stacks

1, 2, and 3 to protect the exposed superlattice phase change memory cells 206 in each stack, the encapsulation layer 204a may be composed of silicon nitride or other

suitable materials

2 and 3.

Fig. 4A shows a second etch that etches through the remaining

electrodes

205b, 205c, the ovonic thermal switch 207, and the conductor 208. An encapsulation layer

204b covering stacks

1, 2 and 3 is deposited to protect the now exposed bidirectional thermal switches 207 in each stack. After encapsulation, gap filler 210 covers

stacks

1, 2, and 3. Gap fill may be obtained by atomic layer deposition of oxide, Spin On Dielectric (SOD), or flowable Chemical Vapor Deposition (CVD) oxide. Examples of gap filling materials include, but are not limited to: gallium arsenide (GaAs), indium gallium arsenide (InGaAs), gallium nitride (GaN), aluminum nitride (AlN), cadmium sulfide (CdS), cadmium selenide (CdSe), cadmium telluride (CdTe), zinc sulfide (ZnS), lead sulfide (PbS), and lead selenide (PbSe), as well as cobalt-based compounds and any combination thereof. Figure 4B shows an oxide/nitride Chemical Mechanical Polishing (CMP) process for

stacks

1, 2 and 3. As shown in fig. 4B, the CMP process is stopped on the carbon electrode 205 a.

Fig. 5A shows a wordline metal and nitride metal deposition step. Shown in the X direction with reference to fig. 2B, a metal layer 501 and a nitride layer 502 are produced. The metal layer 501 may be tungsten or any other conductive metal. The nitride layer 502 may be TiN, TiAlN, TaN, BN, a metal oxynitride (e.g., TiON), a metal silicide (e.g., PtSi), a semiconductor (e.g., silicon or germanium) (doped and undoped), a reduced metal oxide (e.g., TiOx (x <2 represents reduction), a metal (e.g., W, Ni, Co, or carbon-based material), generally deposition may be accomplished by Chemical Vapor Deposition (CVD).

Fig. 6A and 6B illustrate bottom cell word line double patterning, where a first portion is etched through the superlattice phase cell memory to form parallel lines. In fig. 6B, as shown in the relevant cell stacks 601, 602, and 603, the superlattice PCM 206 is not reduced in the Y direction, and there are no encapsulation layers 204a and 204B around the

layers

501, 502.

Fig. 7A is a deposition of an encapsulation layer 704a for covering

stacks

1, 2 and 3 for protecting the exposed superlattice phase change memory cells 206 in each stack. The encapsulation layer 704a may be composed of silicon nitride or other suitable material. The

stacks

1, 2 and 3 may be further encapsulated with a layer 709 comprising a substrate. In FIG. 7A, a second etch is shown that etches through the remaining

electrodes

205b, 205c, the bidirectional thermal switch 207, and the conductor 208. An encapsulation layer

704b covering stacks

1, 2 and 3 is deposited to protect the now exposed bidirectional thermal switches 207 in each stack. After encapsulation, gap filler 710 covers

stacks

1, 2, and 3. Gap fill may be obtained by atomic layer deposition of oxide, Spin On Dielectric (SOD), or flowable Chemical Vapor Deposition (CVD) oxide. Examples of gap filling materials include, but are not limited to: gallium arsenide (GaAs), indium gallium arsenide (InGaAs), gallium nitride (GaN), aluminum nitride (AlN), cadmium sulfide (CdS), cadmium selenide (CdSe), cadmium telluride (CdTe), zinc sulfide (ZnS), lead sulfide (PbS), and lead selenide (PbSe), as well as cobalt-based compounds and any combination thereof. Figure 7B shows an oxide/nitride Chemical Mechanical Polishing (CMP) process for

stacks

1, 2 and 3. As shown in fig. 7B, the CMP process stops on the metal layer 501.

Fig. 8 illustrates a second stack of memory cell deposits and patterning having the novel cell structure described herein with a phase cell memory comprised of a superlattice material. Both the top section 801 and the bottom section 803 are shown with superlattice memory cells 206. As shown in portion 902, the top cell write line and the bottom cell write line separate the two stacks in fig. 9.

Most of the foregoing alternative examples are not mutually exclusive and can be implemented in various combinations to achieve unique advantages. As these and other variations and combinations of the features discussed above can be utilized without departing from the subject matter defined by the claims, the foregoing description of the embodiments should be taken by way of illustration rather than by way of limitation of the subject matter defined by the claims. For example, the foregoing operations need not be performed in the exact order described above. Rather, various steps may be processed in a different order, such as a reverse order, or simultaneously. Steps may also be omitted unless otherwise indicated. Furthermore, the examples described herein, as well as the provision of terms such as "such as," "including," and the like, should not be construed to limit the claimed subject matter to the particular examples; rather, the example is intended to illustrate only one example of many possible embodiments. Further, the same reference numbers in different drawings may identify the same or similar elements.

Although the disclosure has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present disclosure. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present disclosure as defined by the appended claims.

Claims

1. A three-dimensional memory cell structure comprising:

at least one storage cell stack having a selector, a phase change storage cell, and first and second electrodes; the phase change memory cell is disposed between the first electrode and the second electrode, and wherein the phase change memory cell, the selector, and the first and second electrodes each have a dimension relative to a first direction and a second direction;

a word line and a bit line perpendicular to each other and coupled to the stack of storage cells, wherein the phase change storage cells are self-aligned with respect to the word line and the bit line; and is

Wherein the phase change memory cell comprises a superlattice phase change memory cell structure having a plurality of encapsulation layers, wherein the superlattice phase change memory cell structure comprises a nitride and a substrate encapsulation layer and a nitride encapsulation layer on the selector.

2. The three-dimensional memory of claim 1, wherein the selector is an ovonic threshold switch.

3. The three-dimensional memory of claim 1, further comprising additional memory cells in regions above or below the two-dimensional region defined by the word line.

4. The three-dimensional memory of claim 1, wherein the cell stack further comprises a nitride layer, a tungsten layer, an oxide layer, a gap fill layer, and the first and second electrodes are carbon electrodes.

5. The three-dimensional memory of claim 4, wherein the gap fill layer comprises a material selected from the group consisting of: cobalt-based materials, gallium arsenide (GaAs), indium gallium arsenide (InGaAs), gallium nitride (GaN), aluminum nitride (AlN), cadmium sulfide (CdS), cadmium selenide (CdSe), cadmium telluride (CdTe), zinc sulfide (ZnS), lead sulfide (PbS), and lead selenide (PbSe), and any combination thereof.

6. A three-dimensional cross point memory die architecture, comprising:

a plurality of top arrays or blocks of phase change memory cells;

a plurality of bottom arrays or bottom blocks of phase change memory cells;

a plurality of bit lines coupled to the top array and to the bottom array;

a plurality of word lines, comprising: a set of top cell word lines coupled to the top array and a set of bottom cell word lines coupled to the bottom array; and is

Wherein the top arrays of memory cells are each separated by a first space defined by adjacent phase change memory cells in the top array, and the bottom arrays of phase change memory cells are each separated by a second space defined by adjacent phase change memory cells in the bottom array.

7. The three-dimensional architecture of claim 6, wherein the top word line and the bottom word line are coupled to each other.

8. The three-dimensional architecture of claim 6, wherein the top and bottom arrays of phase change memory cells have phase change memory cells comprising a superlattice material.

9. A method of forming a three-dimensional memory, comprising:

forming a cross-point memory array having parallel bit lines and vertical word lines;

forming a memory cell at an intersection of the word line and the bit line, wherein the memory cell is self-aligned; and

using germanium telluride (GeTe), antimony telluride (Sb)₂Te₃) A superlattice material that forms the memory cell with self-aligned double patterning in both horizontal and vertical directions to form a vertical pillar cell having a plurality of encapsulation layers.

10. The method of claim 9, further comprising:

forming a bottom cell stack deposition having the following layers: the phase change memory comprises a cobalt material, a first carbon electrode, an ovonic threshold switch, a second carbon electrode, a phase change memory, a third carbon electrode and a nitride layer;

double patterning using a bottom cell to form a bottom cell and a bottom bit line in parallel;

grooving the phase change memory cell by using ammonium hydroxide or hydrogen peroxide for dry etching or wet etching so as to reduce the critical dimension of the phase change memory cell in one direction;

applying a first encapsulation layer to protect the exposed phase change memory cells;

applying a second encapsulation layer to protect the exposed ovonic threshold switch;

applying a gap fill to the cell stack with an atomic layer deposited oxide, a spin on dielectric, or a flowable chemical vapor deposited oxide;

applying a chemical mechanical polish stopping on the third carbon electrode to the cell stack with an oxide and/or nitride compound;

applying a word line metal deposition to the cell stack; and

forming a bottom cell word line double pattern to form parallel bottom cell word lines perpendicular to the bit lines in contact with the third carbon electrodes.

11. The method of claim 10, applying a deposition of a nitride and oxide compound encapsulation of the phase change memory cell, and applying a deposition of a nitride compound encapsulation of the ovonic threshold switch.

12. The method of claim 11, wherein gap filling is applied to the cell stack after deposition of the nitride and oxide.

13. The method of claim 12, further comprising: an oxide chemical mechanical polish is applied and the chemical mechanical polish is stopped on the tungsten level of the cell stack.

14. The method of claim 13, further comprising: deposition and patterning of a second storage cell stack with a new cell structure having recesses and reduced dimensions is applied.