CN112564630A - Millimeter wave amplifying circuit - Google Patents
Millimeter wave amplifying circuit Download PDFInfo
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- CN112564630A CN112564630A CN202011236660.1A CN202011236660A CN112564630A CN 112564630 A CN112564630 A CN 112564630A CN 202011236660 A CN202011236660 A CN 202011236660A CN 112564630 A CN112564630 A CN 112564630A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
- H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/42—Modifications of amplifiers to extend the bandwidth
Abstract
The invention discloses a millimeter wave amplifying circuit, which comprises a direct current bias unit and a signal amplifying unit; the direct current bias unit comprises a filter circuit, a first voltage generation unit and a second voltage generation unit, receives a power supply voltage, converts the power supply voltage into a bias voltage and outputs a first bias voltage, a second bias voltage, a third bias voltage and a fourth bias voltage; the signal amplification unit comprises an input matching circuit, a first-stage signal amplification unit, an interstage matching circuit, a second-stage signal amplification unit and an output matching circuit; a second input end of the input matching circuit receives a radio frequency signal; the first-stage signal amplification unit receives the first bias voltage and the second bias voltage; the second-stage signal amplification unit receives the third bias voltage and the fourth bias voltage, and a sixth output end of the output matching circuit outputs the amplified radio-frequency signal.
Description
Technical Field
The invention relates to the field of millimeter wave signal processing. And more particularly, to a millimeter wave amplification circuit.
Background
In a receiver system, a low-noise amplifier positioned at a front stage plays a decisive role in the noise performance of the whole receiving system, and the noise of a circuit at a rear stage of the receiver is suppressed through the extremely low noise and high gain of the low-noise amplifier, so that the signal-to-noise ratio of the receiving system is improved. With the development of technologies such as aerospace, radar, microwave communication and the like, the requirements of a radio frequency receiving system on a low-noise amplifier chip are increasingly developed to miniaturization, broadband and low power consumption, and meanwhile, the requirements on performances such as noise, gain, matching and the like are also increasingly high
Disclosure of Invention
An object of the present invention is to provide a millimeter wave amplification circuit that solves at least one of the above problems, comprising:
a direct current bias unit and a signal amplification unit, wherein,
the direct current bias unit comprises a filter circuit, a first voltage generation unit and a second voltage generation unit, a first input end of the direct current bias unit receives a power supply voltage and converts the power supply voltage into a bias voltage, and a first voltage output end and a second voltage output end of the first voltage generation unit and a third voltage output end and a fourth voltage output end of the second voltage generation unit respectively output a first bias voltage, a second bias voltage, a third bias voltage and a fourth bias voltage;
the signal amplification unit comprises an input matching circuit, a first-stage signal amplification unit, an interstage matching circuit, a second-stage signal amplification unit and an output matching circuit; a second input end of the input matching circuit receives a radio frequency signal; the third input end and the fourth input end of the first-stage signal amplification unit are respectively connected with the first voltage output end and the second voltage output end; and a fifth input end and a sixth input end of the second-stage signal amplification unit are respectively connected with the third voltage output end and the fourth voltage output end, and a sixth output end of the output matching circuit outputs the amplified radio-frequency signal.
The filter circuit includes a ninth capacitor and a first resistor, wherein
The first end of the ninth capacitor is connected with the first input end, and the second end of the ninth capacitor is grounded through the first resistor.
The first voltage generation unit includes a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, and a fifth transistor, wherein
The first end of the second resistor is connected with the first input end and receives the power supply voltage, and the second end of the second resistor is connected with the first end of the third resistor; a second terminal of the third resistor serves as the second voltage output terminal and outputs the second bias voltage;
the first end of the fourth resistor is connected with the second end of the second resistor, and the second end of the fourth resistor is connected with the first end of the fifth resistor; a second end of the fifth resistor serves as the first voltage output end and outputs the first bias voltage;
and the grid electrode of the fifth transistor is in short circuit with the drain electrode and is connected with the second end of the sixth resistor, and the source electrode of the fifth transistor is grounded.
The second voltage generator includes a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, and a sixth transistor, wherein
A first end of the seventh resistor is connected with the first input end and receives the power supply voltage, and a second end of the seventh resistor is connected with a first end of the eighth resistor; a second terminal of the eighth resistor serves as the fourth voltage output terminal and outputs the fourth bias voltage;
a first end of the ninth resistor is connected with a second end of the seventh resistor, and a second end is connected with a first end of the tenth resistor; a second terminal of the tenth resistor serves as the third voltage output terminal and outputs the third bias voltage;
and the grid electrode and the drain electrode of the sixth transistor are in short circuit and are connected with the second end of the sixth resistor, and the source electrode of the sixth transistor is grounded.
The input matching circuit comprises a first capacitor, a second capacitor and a first inductor, wherein
The first end of the first capacitor is used as the second input end and receives the radio frequency signal, and the second end of the first capacitor is grounded through the first inductor and is connected with the first end of the second capacitor; and the second end of the second capacitor is connected with the second end of the fifth resistor and outputs a radio frequency signal.
The first stage amplification unit comprises a first transistor, a second inductor, a first regulation unit, a fourth capacitor, a second transistor, a fifth inductor and a sixth inductor, wherein
The source electrode of the first transistor is grounded through a second inductor, the grid electrode of the first transistor is connected with the first voltage output end and receives the first bias voltage, and the drain electrode of the first transistor is connected with the seventh input end of the first regulating unit and outputs a first-stage amplified radio-frequency signal; a first end of the fourth capacitor is connected with the drain electrode of the first transistor and the seventh input end and receives the primary amplified radio frequency signal, and a second end of the fourth capacitor is connected with the grid electrode of the second transistor;
the grid electrode of the second transistor is connected with the second voltage output end and receives the second bias voltage and the primary amplified radio frequency signal, and the drain electrode of the second transistor is connected with the first end of the fifth inductor; the second end of the fifth inductor is connected with the first end of the sixth inductor and the eighth input end of the interstage matching circuit and outputs a two-stage amplified radio frequency signal; a second end of the sixth inductor is connected to the first input terminal.
The first regulating unit comprises a third inductor, a fourth inductor, a third capacitor and a fourth capacitor, and is used for building a direct current path, so that the primary amplified radio frequency signal output by the first transistor cannot enter the source electrode of the second transistor, wherein,
a first end of the third inductor is used as the seventh input end, and a second end of the third inductor is connected with a first end of the fourth inductor and grounded through a third capacitor; a second end of the fourth inductor is connected to a source of the second transistor.
The interstage matching circuit comprises a seventh inductor and a fifth capacitor, wherein
A first end of the seventh inductor is connected as the eighth input terminal with a second end of the fifth inductor and a first end of the sixth inductor, and a second end is connected with a first end of the fifth capacitor; and the second end of the fifth capacitor is connected with the ninth input end of the second-stage signal amplification unit and outputs the second-stage amplified radio-frequency signal.
The second-stage signal amplifying unit includes: a third transistor, a second adjusting unit, a seventh capacitor, a fourth transistor, a tenth inductor, and an eleventh inductor;
the source electrode of the third transistor is grounded, the grid electrode of the third transistor is connected with the third voltage output end and receives the third bias voltage and the second-stage amplified radio frequency signal, and the drain electrode of the third transistor is connected with the ninth input end of the second regulating unit and the first end of the seventh capacitor and outputs a third-stage amplified radio frequency signal; a first end of the seventh capacitor receives the three-stage amplified radio frequency signal, and a second end of the seventh capacitor is connected with a grid electrode of the fourth transistor;
a gate of the fourth transistor is connected to the fourth voltage output terminal and receives the fourth bias voltage and the third-level amplified radio frequency signal, and a drain of the fourth transistor is connected to the first end of the tenth inductor; a second end of the tenth inductor is connected with a first end of the eleventh inductor and outputs the four-stage amplified radio frequency signal; a second end of the eleventh inductor is connected with the first input port.
The output matching circuit includes: a twelfth inductor and an eighth capacitor, wherein
The first end of the twelfth inductor is connected with the second end of the tenth inductor and receives the four-stage amplified radio frequency signal, and the second end of the twelfth inductor is connected with the sixth output end through the eighth capacitor and outputs the amplified radio frequency signal.
The invention has the following beneficial effects:
the invention has extremely low power consumption on the basis of realizing broadband signal amplification, and provides high enough gain and low enough noise coefficient, thereby better suppressing the noise of a post-stage circuit and improving the signal-to-noise ratio and the power consumption performance of a system.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a block diagram of a millimeter wave amplifier circuit according to the present invention;
fig. 2 shows a circuit diagram of a millimeter wave amplification circuit in the present invention.
Detailed Description
In order to make the technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
It should be noted that similar components in the drawings are denoted by the same reference numerals. It is to be understood by persons skilled in the art that the following detailed description is illustrative and not restrictive, and is not to be taken as limiting the scope of the invention.
In one aspect, an embodiment of the present invention provides a millimeter wave amplification circuit, as shown in fig. 1, including:
a direct current bias unit for outputting a bias voltage to the signal amplification unit;
the signal amplification unit is used for amplifying an input radio frequency signal, receiving the bias voltage and outputting the amplified radio frequency signal;
in which, as shown in figure 2,
the DC bias unit includes:
a filter circuit, a first voltage generator and a second voltage generator,
wherein the content of the first and second substances,
the filter circuit comprises a ninth capacitor C9And a first resistor R1Said C is9Port 1 is connected to the supply voltage VDD, port 2 and the first resistor R1Are connected with each other; the first resistor R1The second terminal of (1) is grounded;
the first voltage generator comprises a second resistor R2A third resistor R3A fourth resistor R4A fifth resistor R5A sixth resistor R6And a fifth enhancement mode field effect transistor M5(ii) a For generating a first voltage and a second voltage.
The R is2 Port 3 and C9Port 4 is connected to a third resistor R3Are connected with the port 5; third resistor R3Port 6 and second enhancement mode field effect transistor M2The grid of the first transistor is connected with the grid of the second transistor and outputs a second voltage;
fourth resistor R4Is connected with the port 4 of the second resistor, and the second end is connected with the fifth resistor R5Are connected with each other; resistor R5Second terminal and first enhancement mode field effect transistor M1The grid electrodes are connected and output a first voltage;
sixth resistor R6And the fourth resistor R4Is connected with the second terminal of the fifth enhancement mode FET M5The gate and the drain of (1) are connected; fifth enhancement mode field effect transistor M5Is grounded.
The second voltage generator comprises a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor and a sixth enhancement type field effect transistor M6(ii) a For generating a third voltage and a fourth voltage.
Seventh resistor R7First end of (1) and (C)9Is connected to port 1, and the second end is connected to an eighth resistor R8Is connected with the port 9; r8Is connected to the gate of the fourth enhancement mode field effect transistor and outputs a fourth voltage;
ninth resistor R9First end of (2) and the R7Is connected to the tenth resistor R10Are connected with each other; r10A second terminal of the first transistor is connected with a gate of the first enhancement mode field effect transistor and outputs a first voltage;
eleventh resistor R11First terminal and ninth resistor R9Is connected with the sixth enhancement mode FET M6The grid electrode and the drain electrode are connected; m6Is grounded.
The signal amplification unit specifically includes: the circuit comprises an input matching circuit, a first-stage signal amplification circuit, a second-stage signal amplification circuit, an interstage matching circuit and an output matching circuit.
The first signal amplifying unit includes: the low-noise input matching unit, the second inductor, the first enhancement type field effect transistor, the second enhancement type field effect transistor and the first adjusting unit; a fifth inductor and a sixth inductor are also included.
The low noise input matching unit includes a first capacitor, a second capacitor and a first inductor, the first capacitor C1First terminal of (2) is connected to radio frequency signal RFinSaid C is1Second terminal of and second capacitor C2Is connected with the port 20; c2Port 21 and M1The grid electrodes are connected; inductor L1The first terminal of (A) is grounded, the second terminal is connected with C2Is connected to port 20 of, wherein, C1The effect of isolating direct current is achieved, and the influence of a direct current item of a preceding stage circuit on the signal amplification circuit is eliminated;
first enhancement mode field effect transistor M1Gate of and C2Is connected to receive a first voltage from said first voltage generator, a source and a second inductor L2Is connected to the second terminal of the third inductor L, and the drain electrode is connected to the third inductor L3Is connected to port 22; second inductor L2The first end of (1) is grounded;
the first regulating unit comprises a third inductor L3A fourth inductor L4A third capacitor C3And a fourth capacitor C4Forming a second enhancement type field effect transistor M2Source to first enhancement mode field effect transistor M1A DC path of the drain electrode for preventing the first enhancement type FET M1The radio frequency signal output by the drain electrode enters the second enhancement type field effect transistor M2The source electrode plays a role in adjusting stability, input matching and gain.
Third inductor L3Port 22 and first enhancement mode field effect transistor M1Is connected to the drain of the first transistor,port 23 and third capacitor C3Is connected with the second end of the first end; third capacitor C3The first end of (1) is grounded; fourth inductor L4Is connected with the port 23 of the third inductor and the second end is connected with the second enhancement mode fet M2The source electrodes of the first and second transistors are connected; second enhancement mode FET M2With the port 6 of the first voltage generating unit and the fourth capacitor C4Is connected to receive a second voltage; fourth capacitor C4Port 24 and third inductor L3Is connected to port 22.
Second enhancement mode FET M2Is connected to a port 6 of the dc bias unit and receives a second voltage, and has a drain connected to a fifth inductor L5Are connected with each other; fifth inductor L5Second terminal and sixth inductor L6Are connected with each other; sixth inductor L6Second terminal and ninth capacitor C9Port 1 of (a) is connected.
The interstage matching circuit comprises a seventh inductor L7And a fifth capacitor C5Wherein L is7Is connected to a first end of the sixth inductor and a second end of the fifth inductor, the second end being connected to a fifth capacitor C5Are connected with each other; c5And a tenth resistor R of the DC bias unit10Is connected with the second end of the first connecting rod;
the second-stage signal amplification circuit includes:
the power supply comprises a third enhancement mode field effect transistor, a fourth enhancement mode field effect transistor, a second regulating unit, a tenth inductor, an eleventh inductor, a twelfth inductor and an eighth capacitor.
Specifically, the third enhancement mode fet M3Has a source connected to ground, a drain connected to a first end of the eighth inductor, and a gate connected to a tenth resistor R of the dc bias unit10Is connected to receive a third voltage;
the second regulating unit comprises a sixth capacitor, a seventh capacitor, an eighth inductor and a ninth inductor, wherein a first end of the eighth inductor is connected with the M3OfPole phase connected to each other, and the second terminal connected to the third terminal via a sixth capacitor C6Grounding; ninth inductor L9First terminal and eighth inductor L8The second end of the first transistor is connected with the source electrode of the first enhancement mode field effect transistor; seventh capacitor C7First end of (1) and (M)3Is connected with the drain electrode of the fourth enhancement mode field effect transistor M4Are connected.
Wherein the content of the first and second substances,
eighth inductor L7And a ninth inductor L8And a sixth capacitor C6And a seventh capacitor C7Forming a fourth enhancement type field effect transistor M4Source to third enhancement mode field effect transistor M3A DC path of the drain electrode for preventing the third enhancement type FET M3The radio frequency signal output by the drain electrode enters the fourth enhancement type field effect transistor M4The source electrode plays a role in adjusting stability, input matching and gain.
Fourth enhancement mode FET M4Is connected to port 10 of the eighth resistor of the dc biasing unit and receives the fourth voltage, and has a drain connected to port 27 of the tenth inductor; tenth inductor L10Port 28 and tenth inductor L11A second end of the eleventh inductor is connected with port 1 of the ninth capacitor of the dc biasing unit; twelfth inductor L12Is connected to port 28 of said tenth inductor, and port 30 outputs a radio frequency signal RF via an eighth capacitorout。
First enhancement mode field effect transistor M in signal amplification unit1A second enhancement mode FET M2And a fifth enhancement mode field effect transistor M in the bias circuit5The transistors together form a current input-voltage output type negative feedback structure when the first enhancement type field effect transistor M1A second enhancement mode FET M2And a fifth enhancement mode field effect transistor M5When the transconductance of the fifth enhancement mode field effect transistor M is influenced by factors such as process, voltage and temperature (PVT), etc5The first enhancement mode field effect transistor M can be influenced by negative feedback1And a second enhancement type field effect transistor M2Bias voltage to partially cancel the first enhancement type FET M in the amplifier circuit1And a second enhancement type field effect transistor M2The change of the transconductance reduces the influence of PVT factors on the performance of the low-noise amplifier. In the same way, the sixth enhancement mode field effect transistor M6For the third enhancement mode FET M3And a fourth enhancement type field effect transistor M4The same effect is obtained.
It should be understood that the above-mentioned embodiments of the present invention are only examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention, and it will be obvious to those skilled in the art that other variations or modifications may be made on the basis of the above description, and all embodiments may not be exhaustive, and all obvious variations or modifications may be included within the scope of the present invention.
Claims (10)
1. A millimeter wave amplifier circuit, comprising,
a direct current bias unit and a signal amplification unit, wherein,
the direct current bias unit comprises a filter circuit, a first voltage generation unit and a second voltage generation unit, a first input end of the direct current bias unit receives a power supply Voltage (VDD) and converts the power supply voltage into a bias voltage, and a first voltage output end and a second voltage output end of the first voltage generation unit and a third voltage output end and a fourth voltage output end of the second voltage generation unit respectively output a first bias voltage, a second bias voltage, a third bias voltage and a fourth bias voltage;
the signal amplification unit comprises an input matching circuit, a first-stage signal amplification unit, an interstage matching circuit, a second-stage signal amplification unit and an output matching circuit; a second input of the input matching circuit receives a radio frequency signal (RF)in) (ii) a A third input end of the first-stage signal amplifying unitThe fourth input end is connected with the first voltage output end and the second voltage output end respectively; a fifth input end and a sixth input end of the second-stage signal amplification unit are respectively connected with the third voltage output end and the fourth voltage output end, and a sixth output end of the output matching circuit outputs an amplified radio frequency signal (RF)out)。
2. The circuit of claim 1,
the filter circuit includes a ninth capacitor and a first resistor, wherein
The first end of the ninth capacitor is connected with the first input end, and the second end of the ninth capacitor is grounded through the first resistor.
3. The circuit of claim 1,
the first voltage generating unit includes a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, and a fifth transistor (M)5) Wherein
A first terminal of the second resistor is connected to the first input terminal and receives the power supply Voltage (VDD), and a second terminal is connected to a first terminal of the third resistor; a second terminal of the third resistor serves as the second voltage output terminal and outputs the second bias voltage;
the first end of the fourth resistor is connected with the second end of the second resistor, and the second end of the fourth resistor is connected with the first end of the fifth resistor; a second end of the fifth resistor serves as the first voltage output end and outputs the first bias voltage;
the fifth transistor (M)5) Is shorted to the drain and connected to the second terminal of the sixth resistor, and has its source connected to ground.
4. The circuit of claim 1,
the second voltage generator includes a seventh resistor, an eighth resistor, a ninth resistor, and a tenth resistorA resistor, an eleventh resistor and a sixth transistor (M)6) Wherein
A first terminal of the seventh resistor is connected to the first input terminal and receives the power supply Voltage (VDD), and a second terminal is connected to a first terminal of the eighth resistor; a second terminal of the eighth resistor serves as the fourth voltage output terminal and outputs the fourth bias voltage;
a first end of the ninth resistor is connected with a second end of the seventh resistor, and a second end is connected with a first end of the tenth resistor; a second terminal of the tenth resistor serves as the third voltage output terminal and outputs the third bias voltage;
the sixth transistor (M)6) Is shorted to the drain and connected to the second terminal of the sixth resistor, and has its source connected to ground.
5. The circuit of claim 1,
the input matching circuit comprises a first capacitor, a second capacitor and a first inductor, wherein
The first terminal of the first capacitor is used as the second input terminal and receives the radio frequency signal (RF)in) A second terminal connected to ground through the first inductor and to a first terminal of the second capacitor; and the second end of the second capacitor is connected with the second end of the fifth resistor and outputs a radio frequency signal.
6. The circuit of claim 1,
the first stage amplifying unit includes a first transistor (M)1) A second inductor, a first regulating unit, a fourth capacitor, a second transistor (M)2) A fifth inductor and a sixth inductor, wherein
The first transistor (M)1) The source electrode of the first regulating unit is grounded through a second inductor, the grid electrode of the first regulating unit is connected with the first voltage output end and receives the first bias voltage, and the drain electrode of the first regulating unit is connected with the seventh input end of the first regulating unit and outputs a first-stage amplified radio frequency signalNumber; a first terminal of the fourth capacitor and the first transistor (M)1) Is connected to the seventh input terminal and receives the primary amplified radio frequency signal, and a second terminal is connected to the gate of the second transistor (M2);
the second transistor (M)2) The gate of the first inductor is connected with the second voltage output end and receives the second bias voltage and the first-stage amplified radio frequency signal, and the drain of the first inductor is connected with the first end of the fifth inductor; the second end of the fifth inductor is connected with the first end of the sixth inductor and the eighth input end of the interstage matching circuit and outputs a two-stage amplified radio frequency signal; a second end of the sixth inductor is connected to the first input terminal.
7. The circuit of claim 6,
the first regulating unit comprises a third inductor, a fourth inductor, a third capacitor and a fourth capacitor, and is used for building a direct current path, so that the first-stage amplified radio-frequency signal output by the first transistor cannot enter the second transistor (M)2) The source of (a), wherein,
a first end of the third inductor is used as the seventh input end, and a second end of the third inductor is connected with a first end of the fourth inductor and grounded through a third capacitor; a second end of the fourth inductor and the second transistor (M)2) Are connected.
8. The circuit of claim 1,
the interstage matching circuit comprises a seventh inductor and a fifth capacitor, wherein
A first end of the seventh inductor is connected as the eighth input terminal with a second end of the fifth inductor and a first end of the sixth inductor, and a second end is connected with a first end of the fifth capacitor; and the second end of the fifth capacitor is connected with the ninth input end of the second-stage signal amplification unit and outputs the second-stage amplified radio-frequency signal.
9. The circuit of claim 1,
the second-stage signal amplifying unit includes: third transistor (M)3) A second regulating unit, a seventh capacitor, a fourth transistor (M)4) A tenth inductor and an eleventh inductor;
the third transistor (M)3) The gate is connected with the third voltage output end and receives the third bias voltage and the second-stage amplified radio frequency signal, and the drain is connected with the ninth input end of the second regulating unit and the first end of the seventh capacitor and outputs a third-stage amplified radio frequency signal; a first end of the seventh capacitor receives the three-stage amplified radio frequency signal, and a second end of the seventh capacitor is connected with a grid electrode of the fourth transistor;
the fourth transistor (M)4) The gate of the third inductor is connected with the fourth voltage output end and receives the fourth bias voltage and the three-level amplified radio frequency signal, and the drain of the third inductor is connected with the first end of the tenth inductor; a second end of the tenth inductor is connected with a first end of the eleventh inductor and outputs the four-stage amplified radio frequency signal; a second end of the eleventh inductor is connected with the first input port.
10. The circuit of claim 1,
the output matching circuit includes: a twelfth inductor and an eighth capacitor, wherein
A first end of the twelfth inductor is connected to a second end of the tenth inductor and receives the four-stage amplified radio frequency signal, and a second end of the twelfth inductor is connected to the sixth output end through the eighth capacitor and outputs an amplified radio frequency signal (RF)out)。
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| CN113595514A (en) * | 2021-06-21 | 2021-11-02 | 北京无线电测量研究所 | Amplifying circuit |
| CN115765634A (en) * | 2022-11-18 | 2023-03-07 | 北京无线电测量研究所 | Power amplifying circuit |
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| CN110138345A (en) * | 2019-05-15 | 2019-08-16 | 北京无线电测量研究所 | A kind of wideband amplification circuit |
| CN110401422A (en) * | 2019-06-21 | 2019-11-01 | 厦门科塔电子有限公司 | A kind of high-frequency low noise amplifier circuit configuration |
| CN111147032A (en) * | 2019-12-30 | 2020-05-12 | 河北新华北集成电路有限公司 | Amplifier and radio frequency integrated circuit |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113242019A (en) * | 2021-03-30 | 2021-08-10 | 北京无线电测量研究所 | Amplifying circuit |
| CN113595514A (en) * | 2021-06-21 | 2021-11-02 | 北京无线电测量研究所 | Amplifying circuit |
| CN115765634A (en) * | 2022-11-18 | 2023-03-07 | 北京无线电测量研究所 | Power amplifying circuit |
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