CN220798224U - Cascade amplifying circuit, radar equipment, radar system and electronic equipment - Google Patents
Cascade amplifying circuit, radar equipment, radar system and electronic equipment Download PDFInfo
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Abstract
The utility model provides a cascode amplifying circuit, radar equipment, a radar system and electronic equipment, wherein one end of a first blocking capacitor receives an input signal, and the other end of the first blocking capacitor is coupled to a second amplifying module through a second blocking capacitor and is also respectively coupled to a first biasing module, an inductor and the first amplifying module; the first amplifying module is coupled to the second amplifying module through a third blocking capacitor, and is also coupled to the first biasing module, the third biasing module, the transconductance and the first load module respectively; the second amplifying module is respectively coupled with the third biasing module, the second biasing module and the second load module, and one ends of the inductor and the second biasing module are grounded; the transconductance, the first load module and the second load module are respectively connected with the fourth bias module in a coupling mode, and the first ends of the transconductance, the first load module and the second load module are respectively used for outputting amplified signals; therefore, the utility model can improve the noise cancellation effect of the output signal under the condition of reducing the power consumption of the common-gate and common-source amplifying circuit.
Description
Technical Field
The present utility model relates to the field of power electronics, and in particular, to a cascode circuit, a radar apparatus, a radar system, and an electronic apparatus.
Background
In recent years, the common-gate and common-source amplifier is widely applied in the fields of analog-to-digital converters, gain amplifiers and the like due to the advantages of inherent noise cancellation characteristics, high stability, low sensitivity, capability of realizing higher output voltage and the like.
In the existing broadband low-noise common-gate common-source amplifying circuit, input matching of the circuit is generally completed by utilizing input impedance of a common-gate tube, but the size of the common-gate tube is limited, the transconductance of the common-gate tube is set to be a fixed value, and under the condition that the transconductance of the common-gate tube is higher, the power consumption of the circuit is correspondingly increased; and because the size of the common-gate tube is limited, the noise of the circuit can be considered to be mainly derived from the common-gate tube, and in ideal cases, referring to fig. 1, the channel noise current of the common-gate tube can be set at V IN And V is equal to OUT+ Generating opposite noise voltages at both ends, in particular, if V IN At the end there is in-phase noise voltage, V OUT+ The terminals are the inverse noise voltages. V (V) IN The in-phase noise voltage at the end is amplified by a common source tube and is shown as V OUT- The terminals generate an inverted noise voltage due to V OUT+ End and V OUT- The terminals are all opposite phase noise voltages, and finally V is calculated in a differential mode OUT+ End and V OUT- The noise at both ends is subtracted so that the noise will be cancelled, however, this circuit topology requiresIn practical use, an inductor generally provides a direct current ground path for the common-gate branch, and parasitic resistance exists in the inductor, which results in different potentials of sources of the common-gate transistor and the common-source transistor, and the potential of the source of the common-gate transistor is higher than the source potential of the common-source transistor, so that the noise cancellation effect of the common-gate common-source amplifying circuit is poor in practical use.
Therefore, how to reduce the power consumption of the cascode circuit and improve the noise cancellation effect of the output signal thereof has become a technical problem to be solved in the industry.
Disclosure of Invention
The utility model provides a cascode amplifying circuit, radar equipment, a radar system and electronic equipment, which are used for solving the problem of how to improve the noise cancellation effect of output signals of the cascode amplifying circuit under the condition of reducing the power consumption of the cascode amplifying circuit.
According to a first aspect of the present utility model, there is provided a cascode circuit comprising a first bias module, a second bias module, a third bias module, a fourth bias module, a transconductance and first load module, a second load module, a first amplification module, a second amplification module, and an inductance;
the first end of the first blocking capacitor receives an input signal, the second end of the first blocking capacitor is respectively coupled to the first end of the first biasing module, the first end of the inductor and the first end of the first amplifying module, the second end of the first blocking capacitor is also coupled to the first end of the second amplifying module through a second blocking capacitor, and the second end of the inductor is grounded; the second end and the third end of the first bias module are respectively coupled to the second end and the third end of the first amplification module, the fourth end of the first amplification module is coupled to the first end of the third bias module, the fifth end of the first amplification module is coupled to the second end of the second amplification module through a third blocking capacitor, and the sixth end of the first amplification module is coupled to the first ends of the transconductance and the first load module; the third end of the second amplifying module is coupled to the second end of the third biasing module, the fourth end, the fifth end and the sixth end of the second amplifying module are respectively coupled to the first end, the second end and the third end of the second biasing module, the third end of the second biasing module is grounded, and the seventh end of the second amplifying module is coupled to the first end of the second load module; the first ends of the transconductance and the first load module and the first end of the second load module are used for outputting amplified signals, the second ends of the transconductance and the first load module and the second end of the second load module respectively receive a supply voltage, and the third ends of the transconductance and the first load module and the third end of the second load module are respectively coupled to the first end and the second end of the fourth bias module;
wherein the amplified signal is the same as the waveform of the input signal, and the amplitude of the amplified signal is greater than the amplitude of the input signal.
Optionally, the first amplifying module includes a first NMOS tube and a second NMOS tube; the second amplifying module comprises a third NMOS tube and a fourth NMOS tube; wherein:
the drain electrode of the second NMOS tube is coupled to the first end of the transconductance and the first load module, the source electrode of the second NMOS tube is coupled to the drain electrode of the first NMOS tube, the grid electrode of the second NMOS tube is coupled to the second end of the first bias module, and the grid electrode of the second NMOS tube is also coupled to the first end of the third bias module;
the source electrode of the first NMOS tube is grounded, the grid electrode of the first NMOS tube is coupled to the third end of the first bias module, and the grid electrode of the first NMOS tube is also coupled to the source electrode of the third NMOS tube through the third blocking capacitor;
the drain electrode of the third NMOS tube is coupled to the first end of the second load module, the source electrode of the third NMOS tube is also coupled to the drain electrode of the fourth NMOS tube, the grid electrode of the third NMOS tube is coupled to the first end of the second bias module, and the grid electrode of the third NMOS tube is also coupled to the second end of the third bias module;
the source electrode of the fourth NMOS tube is grounded, the grid electrode of the fourth NMOS tube is coupled to the second end of the first blocking capacitor through the second blocking capacitor, and the grid electrode of the fourth NMOS tube is also coupled to the second end of the second biasing module.
Optionally, the first bias module includes a fifth NMOS transistor, a sixth NMOS transistor, and a first resistor; the second bias module comprises a seventh NMOS tube, an eighth NMOS tube and a second resistor; wherein:
the grid electrode of the fifth NMOS tube and the drain electrode of the sixth NMOS tube respectively receive a first bias current, the source electrode of the sixth NMOS tube is coupled to the drain electrode of the fifth NMOS tube, the grid electrode of the sixth NMOS tube is coupled to the grid electrode of the second NMOS tube, the source electrode of the fifth NMOS tube is coupled to the second end of the first blocking capacitor, and the grid electrode of the fifth NMOS tube is coupled to the grid electrode of the first NMOS tube through the first resistor;
the drain electrode of the seventh NMOS tube and the grid electrode of the eighth NMOS tube respectively receive a second bias current, the grid electrode of the seventh NMOS tube is coupled to the grid electrode of the third NMOS tube, the source electrode of the seventh NMOS tube is coupled to the drain electrode of the eighth NMOS tube, the grid electrode of the eighth NMOS tube is coupled to the grid electrode of the fourth NMOS tube through the second resistor, and the source electrode of the eighth NMOS tube is grounded.
Optionally, the third bias module includes a third resistor; wherein:
the first end of the third resistor receives a first bias voltage, and the second end of the third resistor is coupled to the grid electrode of the second NMOS tube and the grid electrode of the third NMOS tube respectively.
Optionally, the transconductance and the first load module include a first PMOS transistor, a second PMOS transistor, and a first self-bias resistor; wherein:
the source electrode of the first PMOS tube receives the power supply voltage, the grid electrode of the first PMOS tube is coupled to the drain electrode of the second PMOS tube through the first self-bias resistor, the drain electrode of the first PMOS tube is coupled to the source electrode of the second PMOS tube, the grid electrode of the second PMOS tube is coupled to the first end of the fourth bias module, and the drain electrode of the second PMOS tube is further coupled to the drain electrode of the second NMOS tube.
Optionally, the second load module includes a third PMOS transistor, a fourth PMOS transistor, a second self-bias resistor, and a fourth blocking capacitor; wherein:
the source electrode of the third PMOS tube receives the power supply voltage, the grid electrode of the third PMOS tube is coupled to the second end of the first blocking capacitor through the fourth blocking capacitor, the grid electrode of the third PMOS tube is further coupled to the drain electrode of the fourth PMOS tube through the second self-bias resistor, the drain electrode of the third PMOS tube is coupled to the source electrode of the fourth PMOS tube, the grid electrode of the fourth PMOS tube is coupled to the second end of the fourth bias module, and the drain electrode of the fourth PMOS tube is coupled to the drain electrode of the third NMOS tube.
Optionally, the fourth bias module includes a fourth resistor; wherein:
the first end of the fourth resistor receives a second bias voltage, and the second end of the fourth resistor is coupled to the grid electrode of the second PMOS tube and the grid electrode of the fourth PMOS tube respectively.
Optionally, the gain of the transconductance and the branch formed by the first load module and the first amplifying module is equal to the gain of the branch formed by the second load module and the second amplifying module.
According to a second aspect of the present utility model, there is provided a radar apparatus comprising a cascode circuit provided in any one of the first aspects of the present utility model.
According to a third aspect of the present utility model there is provided a radar system comprising a radar apparatus as provided in the second aspect of the present utility model.
According to a fourth aspect of the present utility model there is provided a radar system comprising the radar apparatus provided in the second aspect of the present utility model.
According to a fifth aspect of the present utility model there is provided an electronic device comprising a cascode circuit provided in any one of the first aspects of the present utility model.
In the cascode amplifying circuit, the radar device, the radar system and the electronic device provided by the utility model, one end of a first blocking capacitor is used for receiving an input signal, and the other end of the first blocking capacitor is coupled to a second amplifying module through a second blocking capacitor and is also respectively coupled to a first biasing module, an inductor and the first amplifying module; the first amplifying module is coupled to the second amplifying module through a third blocking capacitor, and is also coupled to the first biasing module, the third biasing module, the transconductance and the first load module respectively; the second amplifying module is respectively coupled to the third biasing module, the second biasing module and the second load module, and one ends of the inductor and the second biasing module are grounded; the transconductance, the first load module and the second load module are respectively connected with the fourth bias module in a coupling mode, and the first ends of the transconductance, the first load module and the second load module are respectively used for outputting amplified signals; therefore, the utility model can improve the noise cancellation effect of the output signal under the condition of reducing the power consumption of the common-gate and common-source amplifying circuit.
Drawings
In order to more clearly illustrate the embodiments of the utility model or the technical solutions in the prior art, the following description will briefly explain the drawings used in the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are only some embodiments of the utility model, and that other drawings can be obtained according to these drawings without inventive effort to a person skilled in the art.
FIG. 1 is a schematic diagram of a prior art cascode circuit configuration;
FIG. 2 is a schematic diagram of a common-source common-gate amplifying circuit in the present utility model;
reference numerals illustrate:
10-a first bias module;
20-a second bias module;
30-transconductance and first load module;
40-a second load module;
50-a first amplification module;
60-a second amplification module;
70-a fourth bias module;
80-a third bias module;
l0-inductance;
RF 1-a first self-bias resistor;
RF 2-a second self-bias resistor;
ib_n1-a first bias current;
ib_n2-second bias current;
VB_N-a first bias voltage;
VB_P-second bias voltage.
Detailed Description
The following description of the embodiments of the present utility model will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present utility model, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.
The terms "first," "second," "third," "fourth" and the like in the description and in the claims and in the above drawings, if any, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the utility model described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
The technical scheme of the utility model is described in detail below by specific examples. The following embodiments may be combined with each other, and some embodiments may not be repeated for the same or similar concepts or processes.
In view of the prior art, there is a problem that it is difficult to ensure that the noise cancellation effect of the output signal can be improved while reducing the power consumption of the cascode circuit. The utility model provides a cascode amplifying circuit, which is characterized in that one end of a first blocking capacitor is used for receiving an input signal, the other end of the first blocking capacitor is coupled to a second amplifying module through a second blocking capacitor, and the first blocking capacitor is also respectively coupled to a first biasing module, an inductor and a first amplifying module; the first amplifying module is coupled to the second amplifying module through a third blocking capacitor, and is also coupled to the first biasing module, the third biasing module, the transconductance and the first load module respectively; the second amplifying module is respectively coupled to the third biasing module, the second biasing module and the second load module, and one ends of the inductor and the second biasing module are grounded; the transconductance, the first load module and the second load module are respectively connected with the fourth bias module in a coupling mode, and the first ends of the transconductance, the first load module and the second load module are respectively used for outputting amplified signals; therefore, the utility model can improve the noise cancellation effect of the output signal under the condition of reducing the power consumption of the common-gate and common-source amplifying circuit.
Referring to fig. 2, an embodiment of the present utility model provides a cascode circuit, which includes a first bias module 10, a second bias module 20, a third bias module 80, a fourth bias module 70, a transconductance and first load module 30, a second load module 40, a first amplifying module 50, a second amplifying module 60, and an inductor L0;
a first end of the first blocking capacitor C1 receives an input signal RFIN, a second end thereof is coupled to the first end of the first bias module 10, the first end of the inductor L0 and the first end of the first amplifying module 50, respectively, the second end of the first blocking capacitor C1 is further coupled to the first end of the second amplifying module 60 through a second blocking capacitor C2, and the second end of the inductor L0 is grounded; the second end and the third end of the first bias module 10 are respectively coupled to the second end and the third end of the first amplification module 50, the fourth end of the first amplification module 50 is coupled to the first end of the third bias module 80, the fifth end of the first amplification module 50 is coupled to the second end of the second amplification module 60 through a third blocking capacitor C3, and the sixth end of the first amplification module 50 is coupled to the first end of the transconductance and the first load module 30; the third end of the second amplifying module 60 is coupled to the second end of the third biasing module 80, the fourth end, the fifth end and the sixth end of the second amplifying module 60 are respectively coupled to the first end, the second end and the third end of the second biasing module 20, the third end of the second biasing module 20 is grounded, and the seventh end of the second amplifying module 60 is coupled to the first end of the second load module 40; the first end of the transconductance and first load module 30 and the first end of the second load module 40 are configured to output the amplified signal VOUT, the second end of the transconductance and first load module 30 and the second end of the second load module 40 respectively receive a supply voltage VDD, and the third end of the transconductance and first load module 30 and the third end of the second load module 40 are respectively coupled to the first end and the second end of the fourth bias module 70;
wherein the amplified signal VOUT is the same waveform as the input signal RFIN, and the amplitude of the amplified signal VOUT is greater than the amplitude of the input signal RFIN.
The inductance L0 provides a dc ground path for the cascode branch without shorting the input signal RFIN to ground.
In an embodiment, referring to fig. 2, the first amplifying module 50 includes a first NMOS transistor N1 and a second NMOS transistor N2; the second amplifying module 60 includes a third NMOS transistor N3 and a fourth NMOS transistor N4; wherein:
the drain electrode of the second NMOS transistor N2 is coupled to the first end of the transconductance and first load module 30, the source electrode of the second NMOS transistor N2 is coupled to the drain electrode of the first NMOS transistor N1, the gate electrode of the second NMOS transistor N2 is coupled to the second end of the first bias module 10, and the gate electrode of the second NMOS transistor N2 is further coupled to the first end of the third bias module 80;
the source electrode of the first NMOS transistor N1 is grounded, the gate electrode of the first NMOS transistor N1 is coupled to the third end of the first bias module 10, and the gate electrode of the first NMOS transistor N1 is further coupled to the source electrode of the third NMOS transistor N3 through the third blocking capacitor C3;
the drain of the third NMOS transistor N3 is coupled to the first end of the second load module 40, the source of the third NMOS transistor N3 is further coupled to the drain of the fourth NMOS transistor N4, the gate of the third NMOS transistor N3 is coupled to the first end of the second bias module 20, and the gate of the third NMOS transistor N3 is further coupled to the second end of the third bias module 80;
the source electrode of the fourth NMOS transistor N4 is grounded, the gate electrode thereof is coupled to the second end of the first blocking capacitor C1 through the second blocking capacitor C2, and the gate electrode of the fourth NMOS transistor N4 is further coupled to the second end of the second bias module 20.
The first NMOS transistor N1 and the fourth NMOS transistor N4 form an amplifying stage of the input signal RFIN of the cascode amplifying circuit, and the second NMOS transistor N2 and the third NMOS transistor N3 are respectively used as a common-gate common-source transistor of the first NMOS transistor N1 and a common-gate common-source transistor of the fourth NMOS transistor N4, so as to inhibit the miller effect, improve the reverse isolation, and increase the circuit stability, thereby preventing the input and output impedance matching networks from affecting each other. Meanwhile, the third NMOS N3 serves as a transconductance enhancement stage of the first NMOS N1, and the transconductance of the third NMOS N3 is raised to a set value, so as to complete input matching.
In a preferred embodiment, the first NMOS transistor N1 and the fourth NMOS transistor N4 operate in a subthreshold region, so that the transconductance efficiency thereof is high.
In this case, in one specific embodiment, the first bias module 10 includes a fifth NMOS transistor N5, a sixth NMOS transistor N6, and a first resistor R1; the second bias module 20 includes a seventh NMOS transistor N7, an eighth NMOS transistor N8, and a second resistor R2; wherein:
the gate of the fifth NMOS transistor N5 and the drain of the sixth NMOS transistor N6 respectively receive a first bias current ib_n1, the source of the sixth NMOS transistor N6 is coupled to the drain of the fifth NMOS transistor N5, the gate of the sixth NMOS transistor N6 is coupled to the gate of the second NMOS transistor N2, the source of the fifth NMOS transistor N5 is coupled to the second end of the first blocking capacitor C1, and the gate of the fifth NMOS transistor N5 is coupled to the gate of the first NMOS transistor N1 through the first resistor R1;
the drain electrode of the seventh NMOS transistor N7 and the gate electrode of the eighth NMOS transistor N8 respectively receive the second bias current ib_n2, the gate electrode of the seventh NMOS transistor N7 is coupled to the gate electrode of the third NMOS transistor N3, the source electrode of the seventh NMOS transistor N7 is coupled to the drain electrode of the eighth NMOS transistor N8, the gate electrode of the eighth NMOS transistor N8 is coupled to the gate electrode of the fourth NMOS transistor N4 through the second resistor R2, and the source electrode of the eighth NMOS transistor N8 is grounded.
The fifth NMOS transistor N5, the sixth NMOS transistor N6, the seventh NMOS transistor N7, and the eighth NMOS transistor N8 form a bias circuit to dynamically bias the first NMOS transistor N1, the second NMOS transistor N2, the third NMOS transistor N3, and the fourth NMOS transistor N4, and the first resistor R1 and the second resistor R2 are used to reduce the noise influence of the first bias current ib_n1 and the second bias current ib_n2 on the core amplifying circuit, where the core amplifying circuit is an amplifying stage of the input signal RFIN of the cascode amplifying circuit formed by the first NMOS transistor N1 and the fourth NMOS transistor N4.
In a preferred embodiment, the current value of the first bias current ib_n1 is equal to the current value of the second bias current ib_n2, and the fifth NMOS transistor N5, the sixth NMOS transistor N6, the seventh NMOS transistor N7, and the eighth NMOS transistor N8 have the same size.
In one embodiment, the third bias module 80 includes a third resistor R3; wherein:
the first end of the third resistor R3 receives the first bias voltage vb_n, and the second end thereof is coupled to the gate of the second NMOS transistor N2 and the gate of the third NMOS transistor N3, respectively.
Wherein the third resistor R3 is configured to reduce the noise influence of the external first bias voltage vb_n on the core amplifying circuit.
In order to make the power consumption of the circuit smaller, in one embodiment, the transconductance and first load module 30 includes a first PMOS transistor P1, a second PMOS transistor P2, and a first self-bias resistor RF1; wherein:
the source electrode of the first PMOS transistor P1 receives the supply voltage VDD, the gate electrode of the first PMOS transistor P1 is coupled to the drain electrode of the second PMOS transistor P2 through the first self-bias resistor RF1, the drain electrode of the first PMOS transistor P1 is coupled to the source electrode of the second PMOS transistor P2, the gate electrode of the second PMOS transistor P2 is coupled to the first end of the fourth bias module 70, and the drain electrode of the second PMOS transistor P2 is further coupled to the drain electrode of the second NMOS transistor N2.
This is because the first amplifying module 50 and the transconductance and the first load module 30 form a current multiplexing structure, so that the transconductance of the common-gate branch is the sum of the transconductance of the first amplifying module 50 and the transconductance of the transconductance and the first load module 30, thereby reducing the power consumption of the circuit.
Because the third NMOS transistor N3 is used as the transconductance enhancement stage of the first NMOS transistor N1 in the common-source branch, a transconductance enhancement structure is implemented, so that the transconductance of the common-gate branch and the transconductance of the common-source branch are the same to achieve the noise cancellation effect, in one embodiment, the second load module 40 includes a third PMOS transistor P3, a fourth PMOS transistor P4, a second self-bias resistor RF2, and a fourth blocking capacitor C4; wherein:
the source electrode of the third PMOS transistor P3 receives the supply voltage VDD, the gate electrode of the third PMOS transistor P3 is coupled to the second end of the first blocking capacitor C1 through the fourth blocking capacitor C4, the gate electrode of the third PMOS transistor P3 is further coupled to the drain electrode of the fourth PMOS transistor P4 through the second self-bias resistor RF2, the drain electrode of the third PMOS transistor P3 is coupled to the source electrode of the fourth PMOS transistor P4, the gate electrode of the fourth PMOS transistor P4 is coupled to the second end of the fourth bias module 70, and the drain electrode of the fourth PMOS transistor P4 is coupled to the drain electrode of the third NMOS transistor N3.
In one embodiment, the fourth bias module 70 includes a fourth resistor R4; wherein:
the first end of the fourth resistor R4 receives the second bias voltage vb_p, and the second end thereof is coupled to the gate of the second PMOS transistor P2 and the gate of the fourth PMOS transistor P4, respectively.
Wherein the fourth resistor R4 is configured to reduce the noise influence of the second bias voltage vb_p on the core amplifying circuit.
In order to optimize the differential characteristics and thus to optimize the noise cancellation effect, in a preferred embodiment, the gain of the branch formed by the transconductance and first load block 30 and the first amplifying block 50 is equal to the gain of the branch formed by the second load block 40 and the second amplifying block 60.
This is because the present utility model separates the bias of the common source and the common gate amplifying tube (i.e., the fourth NMOS tube N4 and the first NMOS tube N1) to become the bias of the equal overdrive voltage, so that the gains of the two noise cancellation branches are equal, and the noise cancellation effect is improved.
In order to better demonstrate the noise cancellation effect of the cascode amplifying circuit provided by the utility model, the operation effects of the cascode amplifying circuit in the prior art and the cascode amplifying circuit provided by the utility model are compared by combining the cascode amplifying circuits of fig. 1 and 2:
referring to fig. 1, in the conventional cascode circuit shown in fig. 1, input matching of the circuit is completed by using input impedance of the cascode tube, but the size of the cascode tube is limited, transconductance of the cascode tube is set to be a fixed value, and power consumption of the circuit is correspondingly increased under the condition that transconductance of the cascode tube is higher; in practical use, an inductance L0 generally provides a direct current ground path for the common-gate branch, and the inductance L0 has a parasitic resistance value, which will cause the difference in the potential between the common-gate transistor and the source of the common-source transistor, the parasitic resistance value of the external inductance L0 causes the point of the source of the common-gate amplifier to be higher than the source of the common-source amplifier, and the transconductance between the common-gate amplifier and the common-source amplifier is different due to the liner bias effect, i.e., the VSB (i.e., the voltage between the substrate and the source) of the common-gate amplifier is different from the VSB of the common-source amplifier, so that the threshold voltages Vth of the common-gate amplifier and the common-source amplifier are also unequal, thereby causing attenuation of noise cancellation effects.
In the cascode circuit (as shown in fig. 2) provided by the present utility model, the transconductance of the cascode branch circuit is divided into the transconductance and the transconductance of the first load module 30 and the transconductance of the first amplifying module 50, so that the power consumption of the circuit is lower by the current multiplexing technology, the first NMOS transistor N1 in the first amplifying module 50 is used as a common-gate amplifying transistor, and the second NMOS transistor N2 is used as a common-gate common-source transistor of the first NMOS transistor N1, so that the transconductance of the first NMOS can be configured as required in the cascode branch circuit;
meanwhile, the transconductance of the common-source branch is the transconductance of the second amplifying module 60, and the transconductance of the common-source branch is the same as the transconductance of the common-gate branch through a transconductance enhancement technology, wherein the fourth NMOS tube N4 in the second amplifying module 60 is used as a common-gate amplifying tube, the third NMOS tube N3 is used as a common-gate common-source tube of the fourth NMOS tube N4, and the third NMOS tube N3 is used as a transconductance enhancement stage of the first NMOS tube N1, so that input matching is completed;
the second NMOS transistor N2 and the third NMOS transistor N3 can inhibit miller effect, improve reverse isolation, and increase circuit stability, so that the input/output impedance matching networks do not affect each other.
With continued reference to fig. 2, since the source voltage of the fifth NMOS transistor N5 is equal to the source voltage of the first NMOS transistor N1, the source voltage of the eighth NMOS transistor N8 is equal to the source voltage of the fourth NMOS transistor N4, and when the current value of the first bias current ib_n1 is equal to the current value of the second bias current ib_n2 and the overdrive voltage of the eighth NMOS transistor N8 is equal to the overdrive voltage of the fourth NMOS transistor N4, the overdrive voltages of the fifth NMOS transistor N5, the sixth NMOS transistor N6, the seventh NMOS transistor N7 and the eighth NMOS transistor N8 are equal, and when the overdrive voltage of the first NMOS transistor N1 is equal to the overdrive voltage of the fourth NMOS transistor N4, the transconductance of the first NMOS transistor N1 is equal to the overdrive voltage of the fourth NMOS transistor N4, so that the noise cancellation effect of the common-gate branch circuit and the common-source circuit is better than that of the common-gate circuit is better;
the overdrive voltage vov=vgs-Vth of the MOS transistor, wherein Vgs is the gate-source voltage of the MOS transistor, and Vth is the threshold voltage of the MOS transistor.
Furthermore, the cascode amplifying circuit provided by the utility model generates noise i generated by thermal noise of the channel resistance of the cascode tube (namely the first NMOS tube N1) n Equivalent to the input end to obtain V n,in ＝k·i n ·R S The method comprises the steps of carrying out a first treatment on the surface of the Equivalent to the output end to obtain V n,GG ＝-k·i n ·R CG WhereinWhen the input impedance is matched, the value is 1/2, and the noise generated by the common source tube (namely the fourth NMOS tube N4) at the drain end is V n,CS ＝V n,in ·A v,CG When A is v,CS ＝-A v,CG I.e. in equilibrium, V n,CG ＝V n,CS After the difference is subtracted, the effect of noise cancellation is achieved;
wherein R is S For external impedance, R CG Impedance of common-gate branch, A v,CG For gain of common-gate branch, V n,in To input noise voltage, V n,CS Is the noise voltage of the common source stage branch circuit, V n,CG Is the noise voltage of the common-gate branch.
In addition, the utility model also provides radar equipment, which comprises the cascode circuit. The input signal RFIN may be, for example, a radio frequency signal, but may be any other signal that needs to be transmitted.
In addition, the utility model also provides a radar system comprising the radar device. By way of example, the radar system may be a millimeter wave radar system.
In addition, the utility model also provides electronic equipment, which comprises the cascode circuit. For example, the above-mentioned cascode circuit may be formed as a chip, and integrated into a device that needs to transmit signals.
In summary, in the present utility model, one end of the first blocking capacitor receives an input signal, and the other end thereof is coupled to the second amplifying module through the second blocking capacitor, and is further coupled to the first biasing module, the inductor and the first amplifying module respectively; the first amplifying module is coupled to the second amplifying module through a third blocking capacitor, and is also coupled to the first biasing module, the third biasing module, the transconductance and the first load module respectively; the second amplifying module is respectively coupled to the third biasing module, the second biasing module and the second load module, and one ends of the inductor and the second biasing module are grounded; the transconductance, the first load module and the second load module are respectively connected with the fourth bias module in a coupling mode, and the first ends of the transconductance, the first load module and the second load module are respectively used for outputting amplified signals; therefore, the utility model can improve the noise cancellation effect of the output signal under the condition of reducing the power consumption of the common-gate and common-source amplifying circuit.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present utility model, and not for limiting the same; although the utility model has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the utility model.
Claims (11)
1. The cascode amplifying circuit is characterized by comprising a first bias module, a second bias module, a third bias module, a fourth bias module, a transconductance, a first load module, a second load module, a first amplifying module, a second amplifying module and an inductor;
the first end of the first blocking capacitor receives an input signal, the second end of the first blocking capacitor is respectively coupled to the first end of the first biasing module, the first end of the inductor and the first end of the first amplifying module, the second end of the first blocking capacitor is also coupled to the first end of the second amplifying module through a second blocking capacitor, and the second end of the inductor is grounded; the second end and the third end of the first bias module are respectively coupled to the second end and the third end of the first amplification module, the fourth end of the first amplification module is coupled to the first end of the third bias module, the fifth end of the first amplification module is coupled to the second end of the second amplification module through a third blocking capacitor, and the sixth end of the first amplification module is coupled to the first ends of the transconductance and the first load module; the third end of the second amplifying module is coupled to the second end of the third biasing module, the fourth end, the fifth end and the sixth end of the second amplifying module are respectively coupled to the first end, the second end and the third end of the second biasing module, the third end of the second biasing module is grounded, and the seventh end of the second amplifying module is coupled to the first end of the second load module; the first ends of the transconductance and the first load module and the first end of the second load module are used for outputting amplified signals, the second ends of the transconductance and the first load module and the second end of the second load module respectively receive a supply voltage, and the third ends of the transconductance and the first load module and the third end of the second load module are respectively coupled to the first end and the second end of the fourth bias module;
wherein the amplified signal is the same as the waveform of the input signal, and the amplitude of the amplified signal is greater than the amplitude of the input signal.
2. The cascode circuit according to claim 1, wherein said first amplification module comprises a first NMOS transistor and a second NMOS transistor; the second amplifying module comprises a third NMOS tube and a fourth NMOS tube; wherein:
the drain electrode of the second NMOS tube is coupled to the first end of the transconductance and the first load module, the source electrode of the second NMOS tube is coupled to the drain electrode of the first NMOS tube, the grid electrode of the second NMOS tube is coupled to the second end of the first bias module, and the grid electrode of the second NMOS tube is also coupled to the first end of the third bias module;
the source electrode of the first NMOS tube is grounded, the grid electrode of the first NMOS tube is coupled to the third end of the first bias module, and the grid electrode of the first NMOS tube is also coupled to the source electrode of the third NMOS tube through the third blocking capacitor;
the drain electrode of the third NMOS tube is coupled to the first end of the second load module, the source electrode of the third NMOS tube is also coupled to the drain electrode of the fourth NMOS tube, the grid electrode of the third NMOS tube is coupled to the first end of the second bias module, and the grid electrode of the third NMOS tube is also coupled to the second end of the third bias module;
the source electrode of the fourth NMOS tube is grounded, the grid electrode of the fourth NMOS tube is coupled to the second end of the first blocking capacitor through the second blocking capacitor, and the grid electrode of the fourth NMOS tube is also coupled to the second end of the second biasing module.
3. The cascode circuit according to claim 2, wherein said first bias module comprises a fifth NMOS transistor, a sixth NMOS transistor, and a first resistor; the second bias module comprises a seventh NMOS tube, an eighth NMOS tube and a second resistor; wherein:
the grid electrode of the fifth NMOS tube and the drain electrode of the sixth NMOS tube respectively receive a first bias current, the source electrode of the sixth NMOS tube is coupled to the drain electrode of the fifth NMOS tube, the grid electrode of the sixth NMOS tube is coupled to the grid electrode of the second NMOS tube, the source electrode of the fifth NMOS tube is coupled to the second end of the first blocking capacitor, and the grid electrode of the fifth NMOS tube is coupled to the grid electrode of the first NMOS tube through the first resistor;
the drain electrode of the seventh NMOS tube and the grid electrode of the eighth NMOS tube respectively receive a second bias current, the grid electrode of the seventh NMOS tube is coupled to the grid electrode of the third NMOS tube, the source electrode of the seventh NMOS tube is coupled to the drain electrode of the eighth NMOS tube, the grid electrode of the eighth NMOS tube is coupled to the grid electrode of the fourth NMOS tube through the second resistor, and the source electrode of the eighth NMOS tube is grounded.
4. A cascode circuit according to claim 3, wherein said third bias module comprises a third resistor; wherein:
the first end of the third resistor receives a first bias voltage, and the second end of the third resistor is coupled to the grid electrode of the second NMOS tube and the grid electrode of the third NMOS tube respectively.
5. The cascode circuit according to claim 2, wherein said transconductance and first load module comprises a first PMOS transistor, a second PMOS transistor, and a first self-bias resistor; wherein:
the source electrode of the first PMOS tube receives the power supply voltage, the grid electrode of the first PMOS tube is coupled to the drain electrode of the second PMOS tube through the first self-bias resistor, the drain electrode of the first PMOS tube is coupled to the source electrode of the second PMOS tube, the grid electrode of the second PMOS tube is coupled to the first end of the fourth bias module, and the drain electrode of the second PMOS tube is further coupled to the drain electrode of the second NMOS tube.
6. The cascode circuit according to claim 5, wherein said second load module comprises a third PMOS transistor, a fourth PMOS transistor, a second self-bias resistor, and a fourth dc blocking capacitor; wherein:
the source electrode of the third PMOS tube receives the power supply voltage, the grid electrode of the third PMOS tube is coupled to the second end of the first blocking capacitor through the fourth blocking capacitor, the grid electrode of the third PMOS tube is further coupled to the drain electrode of the fourth PMOS tube through the second self-bias resistor, the drain electrode of the third PMOS tube is coupled to the source electrode of the fourth PMOS tube, the grid electrode of the fourth PMOS tube is coupled to the second end of the fourth bias module, and the drain electrode of the fourth PMOS tube is coupled to the drain electrode of the third NMOS tube.
7. The cascode circuit according to claim 6, wherein said fourth bias module comprises a fourth resistor; wherein:
the first end of the fourth resistor receives a second bias voltage, and the second end of the fourth resistor is coupled to the grid electrode of the second PMOS tube and the grid electrode of the fourth PMOS tube respectively.
8. The cascode circuit according to claim 7, wherein a gain of a branch formed by said transconductance and first load block and said first amplifying block is equal to a gain of a branch formed by said second load block and said second amplifying block.
9. A radar apparatus comprising a cascode circuit according to any one of claims 1 to 8.
10. A radar system comprising the radar apparatus of claim 9.
11. An electronic device comprising a cascode circuit according to any one of claims 1 to 8.
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| CN202322414475.2U CN220798224U (en) | 2023-09-05 | 2023-09-05 | Cascade amplifying circuit, radar equipment, radar system and electronic equipment |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202322414475.2U CN220798224U (en) | 2023-09-05 | 2023-09-05 | Cascade amplifying circuit, radar equipment, radar system and electronic equipment |
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| CN220798224U true CN220798224U (en) | 2024-04-16 |
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