WO2021225031A1

WO2021225031A1 - Transconductance amplifier and receiving device

Info

Publication number: WO2021225031A1
Application number: PCT/JP2021/009750
Authority: WO
Inventors: 秀行高野
Original assignee: ソニーセミコンダクタソリューションズ株式会社
Priority date: 2020-05-08
Filing date: 2021-03-11
Publication date: 2021-11-11
Also published as: JPWO2021225031A1

Abstract

A transconductance amplifier, wherein the power consumption and noise are reduced.　The transconductance amplifier is provided with a main amplifier, an auxiliary amplifier, a feedback capacitance, a gate capacitance, a load capacitance, and an impedance matching circuit. The main amplifier converts the voltage of an input signal into a current and outputs the current. The auxiliary amplifier is connected in parallel with the main amplifier. The feedback capacitance causes the output of the auxiliary amplifier to be fed back, with the phase thereof inverted, to the input side. The gate capacitance grounds the input of the auxiliary amplifier to earth. The load capacitance grounds the output of the auxiliary amplifier to earth. The impedance matching circuit causes the signal source impedance of the input signal to be matched with the input impedance of the auxiliary amplifier.

Description

Transconductance amplifier and receiver

This technology relates to a transconductance amplifier. More specifically, the present invention relates to a transconductance amplifier that converts an input voltage into an electric current, and a receiving device including the transconductance amplifier.

Conventionally, a low noise amplifier (LNA: Low Noise Amplifier) has been used in a wireless signal receiver or the like to amplify a weak signal. On the other hand, with the recent progress in miniaturization of semiconductor processes, the power supply voltage is decreasing, and it is required to reduce the power supply voltage of the amplifier accordingly. In general, the dynamic range of an amplifier decreases as the power supply voltage decreases. Therefore, a technique for performing signal processing in a current mode using a transconductance amplifier is known (see, for example, Non-Patent Document 1).

In the above-mentioned conventional technology, the dynamic range at a low power supply voltage is improved by utilizing the fact that the signal processing in the current mode is not easily restricted by the power supply voltage. However, in this conventional technique, the input impedance becomes resistant due to the feedback from the feedback amplifier, and while the input can be matched over a wide band, the noise of the feedback amplifier is directly input to the input of the amplifier, so that the noise figure deteriorates. There's a problem. Further, when the design is made to satisfy the input matching condition, there is a problem that the power consumption of the feedback amplifier is remarkably increased.

This technology was created in view of this situation, and aims to reduce power consumption and noise in the transconductance amplifier.

This technology has been made to solve the above-mentioned problems, and the first aspect thereof is a main amplifier that converts the voltage of an input signal into a current and outputs it, and is connected in parallel with the main amplifier. The auxiliary amplifier, the feedback capacitance that inverts the phase of the output of the auxiliary amplifier and returns it to the input side, the gate capacitance that grounds the input of the auxiliary amplifier, the load capacitance that grounds the output of the auxiliary amplifier, and the above. It is a transconductance amplifier including an impedance matching circuit that matches the signal source impedance of an input signal with the input impedance of the auxiliary amplifier. This brings about the effect of reducing power consumption and noise by matching the impedance in the impedance matching circuit.

Further, in this first aspect, a common mode feedback circuit that feeds back the output of the auxiliary amplifier to the inputs of the main amplifier and the auxiliary amplifier may be further provided. This has the effect of determining the DC potential of the output terminal.

Further, in this first aspect, each of the main amplifier and the auxiliary amplifier may be provided with a thick film transistor that inputs the input signal to the gate. This has the effect of suppressing the effect of electrostatic discharge on the gate oxide film.

Further, in this first aspect, each of the main amplifier and the auxiliary amplifier may be provided with a thin film transistor having a cascode configuration in the output unit. This has the effect of reducing the parasitic capacitance of the output section and improving the high frequency characteristics. In addition, the higher output impedance has the effect of improving the accuracy of the current output.

Further, in this first aspect, a bias generation circuit for generating a bias voltage for the main amplifier and the auxiliary amplifier may be further provided. This has the effect of properly determining the bias voltage in each part of the main amplifier and the auxiliary amplifier.

Further, in this first aspect, the impedance matching circuit may be an LC circuit having a series inductor and a shunt capacitance. This has the effect of matching the impedance with the LC circuit.

Further, in this first aspect, the main amplifier may include a plurality of amplifiers connected in parallel. In this case, at least one of the plurality of amplifiers may be controlled to operate or not according to a predetermined control signal. This has the effect of combining the outputs of a plurality of amplifiers to make the gain variable as a whole. Further, in this case, the gain of each of the plurality of amplifiers may be a predetermined fixed value, and in particular, the gain may be set to be twice or half that of the other amplifiers.

The second aspect of the present technology is to convert the voltage of the received input signal into a current and output it, the auxiliary amplifier connected in parallel with the main amplifier, and the output phase of the auxiliary amplifier. Match the feedback capacitance that is inverted and fed back to the input side, the gate capacitance that grounds the input of the auxiliary amplifier, the load capacitance that grounds the output of the auxiliary amplifier, and the impedance of the input signal and the input of the auxiliary amplifier. A transconductance amplifier equipped with an impedance matching circuit, a current input mixer that multiplies the output current of the main amplifier by the output of the local oscillator to generate an intermediate frequency signal, and an interfering while amplifying the intermediate frequency signal to a predetermined level. An intermediate frequency processing unit that removes waves, an analog digital conversion unit that converts the amplified intermediate frequency signal from an analog value to a digital value, and a signal that performs predetermined signal processing on the intermediate frequency signal converted to the digital value. It is a receiving device including a processing unit. As a result, by using a transconductance amplifier whose impedance is matched in the impedance matching circuit, the power consumption and noise of the receiving device are reduced.

Further, in this second aspect, a signal of a global satellite positioning system (GNSS: Global Navigation Satellite System) may be received as the above input signal. Global satellite positioning systems require high gain, low noise, and low power consumption, but have a narrow signal band, which makes them useful as applications for the transconductance amplifier of the present technology.

Further, in the second aspect, a plurality of the transconductance amplifiers that receive signals of different frequency bands as the input signals may be provided. This brings about the effect of simultaneously receiving signals of different frequency bands according to the setting of the value of each part of the transconductance amplifier.

It is a figure which shows the block structure example of the transconductance amplifier 100 in embodiment of this technique. It is a figure which shows the circuit structure example of the transconductance amplifier 100 in embodiment of this technique. It is a figure which shows the circuit structure example of the main amplifier 110 in embodiment of this technique. It is a figure which shows the circuit structure example of the auxiliary amplifier 120 in embodiment of this technique. It is a figure which shows the example of the bias voltage generated by the bias generation circuit 150 in embodiment of this technique. It is a figure which shows an example of the DC operating point of the transconductance amplifier 100 in embodiment of this technique. It is a figure which shows the block structure example of the transconductance amplifier 100 in the 1st modification of embodiment of this technique. It is a figure which shows the relation example of the control signal and gain of the transconductance amplifier 100 in the 1st modification of embodiment of this technique. It is a figure which shows the block structure example of the transconductance amplifier 100 in the 2nd modification of embodiment of this technique. It is a figure which shows the block composition example of the receiver in the 3rd modification of embodiment of this technique. It is a figure which shows the block structure example of the transconductance amplifier 101 and 102 in the 4th modification of the Embodiment of this technique.

Hereinafter, embodiments for carrying out the present technology (hereinafter referred to as embodiments) will be described. The explanation will be given in the following order.
1. 1. Embodiment (transconductance amplifier)
2. Modification example

<1. Embodiment>
[Block configuration]
FIG. 1 is a diagram showing a block configuration example of the transconductance amplifier 100 according to the embodiment of the present technology.

The transconductance amplifier 100 includes a main amplifier 110, an auxiliary amplifier 120, a feedback capacitance 137, a gate capacitance 135, a load capacitance 136, a resistor 138, and an common mode feedback circuit 140. It is assumed that these are provided in the chip. An impedance matching circuit 180 is provided outside the chip.

The main amplifier (Gm) 110 is an amplifier that converts the voltage of the input signal into a current and outputs it as an output current Iout.

The auxiliary amplifier (Gmp) 120 is an amplifier that is branched into two from the input of the main amplifier 110 and connected in parallel. The gate width of the transistor of the auxiliary amplifier 120 is assumed to be, for example, about one tenth of that of the main amplifier 110. Therefore, the power consumption is about one tenth.

The feedback capacitance (Cf) 137 is a capacitance that inverts the phase of the output of the auxiliary amplifier 120 and returns (negative feedback) to the input side. The gate capacitance (Cg) 135 is a capacitance that grounds the input of the auxiliary amplifier 120. The load capacity (Cl) 136 is a capacity for grounding the output of the auxiliary amplifier 120. The resistor (Rhigh) 138 is a resistor that connects the outputs of the main amplifier 110 and the auxiliary amplifier 120. The resistance value of this resistor 138 is large enough to be negligible in calculation.

The common mode feedback circuit 140 is a common mode feedback (CMFB) circuit provided for determining the DC operating point of the outputs of the main amplifier 110 and the auxiliary amplifier 120. The capacitance (C6) 142 is a phase compensation capacitance for ensuring the stability of the common mode feedback loop. The input impedance of the common mode feedback circuit is assumed to be sufficiently high so that it can be ignored in calculation.

The impedance matching circuit 180 is a circuit that matches the antenna impedance Rs (the signal source impedance of the input signal) with the input impedance of the auxiliary amplifier 120. The impedance matching circuit 180 includes a series inductor (Lm) 181 and a shunt capacitance (Cm) 182. A capacitor (Cdc) 193 for cutting a direct current (DC) component is provided on the input side of the impedance matching circuit 180.

Voltage Vs is input to the transconductance amplifier 100 as an input signal. Further, here, assuming that the transconductance amplifier 100 is used in the receiving device, it is assumed that the antenna impedance Rs is, for example, 50Ω.

[Circuit configuration]
FIG. 2 is a diagram showing a circuit configuration example of the transconductance amplifier 100 according to the embodiment of the present technology.

The circuit configuration example shown here is basically the same as the block configuration described above. However, the bias generation circuit 150 and the electrostatic protection element 170 are not shown in the above-mentioned block configuration. The electrostatic protection element 170 is a circuit for protecting from a transient high voltage or high current due to electrostatic discharge (ESD: Electro-Static Discharge). The bias generation circuit 150 is a circuit that generates the bias voltage of the transistors of the main amplifier 110 and the auxiliary amplifier 120.

Further, the output of the auxiliary amplifier 120 is separated from the output of the main amplifier 110 in an alternating current (AC) by a high resistance (Rhigh) 138.

FIG. 3 is a diagram showing a circuit configuration example of the main amplifier 110 according to the embodiment of the present technology.

The main amplifier 110 has a configuration in which four transistors 111 to 114 are stacked in four stages.

Transistors

111 and 114 are input transistors that receive input signals at the gate. These

transistors

111 and 114 have a thick film (HV: high withstand voltage) transistor structure having a long gate length (for example, L = 150 nm) as a countermeasure against electrostatic discharge.

Transistors

112 and 113 are output transistors that output current. These

transistors

112 and 113 have a short gate length (for example, L = 40 nm) thin film (LV: low withstand voltage) in order to reduce the parasitic capacitance of the output section, further increase the output impedance, and improve the accuracy of current output. It has a cascode configuration with transistors.

The bias voltages Vb1, Vb2 and Vb3 of the

transistors

111, 112 and 113 are supplied from the bias generation circuit 150.

The common mode feedback circuit 140 includes an operational amplifier 141, and feeds back the output of the main amplifier 110 to the input side of the main amplifier 110 via the resistor Rg1. Thereby, the DC potential of the output terminal is determined.

FIG. 4 is a diagram showing a circuit configuration example of the auxiliary amplifier 120 according to the embodiment of the present technology.

The auxiliary amplifier 120 has a configuration in which four transistors 121 to 124 are stacked in four stages.

Transistors

121 and 124 are input transistors that receive input signals at the gate.

Transistors

122 and 123 are output transistors that output current. As an example, the gate width of the transistors 121 to 124 is approximately one tenth of that of the transistors 111 to 114 of the main amplifier 110. This sets the bias current to one tenth of the main amplifier 110.

The bias voltages Vb1, Vb2 and Vb3 of the

transistors

121, 122 and 123 are common to the main amplifier 110 and are supplied from the bias generation circuit 150. Further, the common mode feedback circuit 140 that determines the DC potential of the output terminal is also shared with the main amplifier 110.

On the other hand, unlike the main amplifier 110, the auxiliary amplifier 120 is loaded with a feedback capacity 137, a gate capacity 135, and a load capacity 136. The values of these capacitances may be variable.

FIG. 5 is a diagram showing an example of a bias voltage generated by the bias generation circuit 150 in the embodiment of the present technology.

This bias generation circuit 150 generates the optimum bias voltages Vb1, Vb2, Vb3 and Vref for an amplifier in which thick film transistors and thin film transistors coexist.

The bias voltage Vb1 is supplied to the gates of the

transistors

111 and 121. The bias voltage Vb2 is supplied to the gates of

transistors

112 and 122. The bias voltage Vb3 is supplied to the gates of

transistors

113 and 123. As will be described later, the bias voltage Vref is half the power supply voltage Vdd (Vdd / 2) and is supplied to the negative input terminal of the operational amplifier 141.

As described above, the main amplifier 110 and the auxiliary amplifier 120 are mixed with thick-film transistors and thin film transistors stacked in four stages, but are suitable for obtaining stable characteristics even when the process, power supply voltage, and temperature fluctuate. It is necessary to apply the bias voltage. Since the variation between the thick film transistor and the thin film transistor is generally uncorrelated, it is desirable to be able to generate a bias voltage that appropriately follows the variation even when it varies independently. This bias generation circuit 150 is an example of realizing it.

In order to reduce power consumption, the transconductance amplifier 100 operates all MOSFETs in the subthreshold region. The current equation in the subthreshold region of the MOSFET is expressed by an exponential function as follows.
Id = K ・ Is ・ exp ((Vgs-Vth) / (n ・ Vt))
However, K is the aspect ratio (W / L) of the transistor. W is the gate width. L is the gate length. Vgs is the gate-source voltage. Vth is the threshold voltage.

Is is also given by the following equation.
Is = μCox (n-1) Vt ²
Here, n is a subthreshold coefficient, and a typical value is about 1.7 to 1.8. μ is the mobility. Cox is the gate oxide capacity. Vt is a thermal voltage, which is about 26 mV at room temperature of 300 K.

By modifying the equation of Id, the gate-source voltage Vgs is expressed by the following equation.
Vgs = n · Vt · ln (Id / (K · Is)) + Vth
Therefore, the bias voltage Vb1 is given by the following equation.
Vb1 = Vgs_MH5
= N_HV ・ Vt ・ ln (I3 / (K_MH5 ・ Is_HV)) + Vth_HV
Here, the subscript HV indicates that it is a high withstand voltage transistor.

Next, the bias voltage Vb2 will be examined. The gate-source voltage Vgs_MH6 of the transistor 153 (MH6) is given by the following equation.
Vgs_MH6 = n_HV ・ Vt
・ Ln ((I1 + I2) / (K_MH6 ・ Is_HV)) + Vth_HV

Similarly, the gate-source voltage Vgs_MH7 of the transistor 155 (MH7) is
Vgs_MH7 = n_HV ・ Vt ・ ln (I2 / (K_MH7 ・ Is_HV))
+ Vth_HV

By taking the difference between the above two equations, the following equation is obtained.
Vgs_MH6-Vgs_MH7 = n_HV ・ Vt
・ Ln ((K_MH7 / K_MH6) (1+ (I1 / I2)))

Further, the gate-source voltage Vgs_ML6 of the transistor 154 (ML6) is given by the following equation.
Vgs_ML6 = n_LV ・ Vt
・ Ln (I1 / (K_ML6 ・ Is_LV)) + Vth_LV
Here, the subscript LV indicates that it is a thin film transistor.

Since the bias voltage Vb2 is the sum of the above two equations, it is given by the following equation.
Vb2 = Vgs_MH6-Vgs_MH7 + Vgs_ML6
= N_HV ・ Vt ・ ln ((K_MH7 / K_MH6) (1+ (I1 / I2)))
+ N_LV ・ Vt ・ ln (I1 / (K_ML6 ・ Is_LV)) + Vth_LV

Next, the bias voltage Vb3 will be examined. The gate-source voltage Vgs_MH9 of the transistor 167 (MH9) is given by the following equation.
Vgs_MH9 = n_HV ・ Vt ・ ln (I4 / (K_MH9 ・ Is_HV))
+ Vth_HV

Further, the gate-source voltage Vgs_MH8 of the transistor 157 (MH8) is given by the following equation.
Vgs_MH8 = n_HV ・ Vt
・ Ln ((I4 + I5) / (K_MH8 ・ Is_HV)) + Vth_HV

Further, the gate-source voltage Vgs_ML8 of the transistor 158 (ML8) is given by the following equation.
Vgs_ML8 = n_HV ・ Vt ・ ln (I5 / (K_ML8 ・ Is_LV))
+ Vth_LV

The bias voltage Vb3 is given by the following equation from the above three equations.
Vb3 = Vdd-Vgs_MH8 + Vgs_MH9-Vgs_ML8
= Vdd-n_HV · Vt
・ Ln ((K_MH8 / K_MH9) (I4 / (I4 + I5)))
-N_LV / Vt / ln (I5 / (K_ML8 / Is_LV)) + Vth_LV

Next, the bias voltage Vref will be examined. In the bias generation circuit 150, the potential Vn at the connection point between the source of the transistor 156 (ML7) and the drain of the transistor 154 (ML6), and the connection point between the drain of the transistor 158 (ML8) and the source of the transistor 168 (ML9). The value of the potential Vp of can be expressed by the following equations.
Vn = (Vgs_MH6-Vgs_MH7) + (Vgs_ML6-Vgs_ML7)
Vp = Vdd- (Vgs_MH8-Vgs_MH9)
-(Vgs_ML8-Vgs_ML9)

here,
(Vgs_MH6-Vgs_MH7) = (Vgs_MH8-Vgs_MH9) and
(Vgs_ML6-Vgs_ML7) = (Vgs_ML8-Vgs_ML9)
Consider the conditions that will be.

First, in order for (Vgs_MH6-Vgs_MH7) = (Vgs_MH8-Vgs_MH9) to hold, it is necessary to set the transistor size and current so as to satisfy the following conditions.
(K_MH7 / K_MH6) (K_MH8 / K_MH9) =
(I2 / (I1 + I2)) ((I4 + I5) / I4)

Further, in order for (Vgs_ML6-Vgs_ML7) = (Vgs_ML8-Vgs_ML9) to hold, it is necessary to set the transistor size so as to satisfy the following conditions.
K_ML7 / K_ML6 = K_ML9 / K_ML8

Here, when Rcm1 = Rcm2, the bias voltage Vref is
Vref = (Vp + Vn) / 2
Since it is represented by and Vp + Vn = Vdd, the bias voltage Vref is given by the following equation.
Vref = Vdd / 2

By applying the bias voltages Vb1, Vb2, Vb3 and Vref in this way, stable characteristics can be obtained even when the process, power supply voltage and temperature fluctuate.

[Input impedance]
Since the input impedance at the gate terminal of the MOS transistor is almost capacitive, the actual part of the input admittance of the main amplifier 110 is substantially zero. Therefore, first, the input admittance Yp of the auxiliary amplifier 120 is obtained.
Yp = (Gmp / (1+ (Cl / Cf)))
+ Jωo (1 / ((1 / Cf) + (1 / Cl)))
However, ωo is an angular frequency of the reception frequency fo.
ωo = 2πfo
Here, the real part is Gp and the imaginary part is Bp. That is,
Yp = Gp + jBp
And.

At this time, the value Lm of the series inductor 181 of the impedance matching circuit 180 and the value Cm of the shunt capacitance 182 are given by the following equations, respectively.
Lm = (Bp + (GpRs (Gp ² + Bp ² ) -Gp ² ) ^1/2 )
/ (Ωo (Gp ² + Bp ² ))
Cm = (GpRs (Gp ² + Bp ² ) -Gp ² ) ^1/2 / ωoGpRs

Here, as a numerical example,
fo = 1.6GHz
Gmp = 1mS
Cg = 0.85pF
Cf = Cl = 0.2pF
Then
Gp = 0.5mS
Bp = 9.5mS
Lm = 12nH
Cm = 5.6pF
Will be. At this time, the impedance Zin seen from the input of the impedance matching circuit 180 is
Zin = Rs = 50Ω
Therefore, the input impedance Zin can be matched with the antenna impedance Rs. In this example, the mutual conductance Gmp of the auxiliary amplifier 120 is set to 1 mS, and the power consumption can be reduced. That is, since the auxiliary amplifier 120 does not directly generate 50Ω, the power consumption is small.

On the other hand, when feedback is performed by a feedback amplifier (Gmf) as in the prior art, the input impedance is "1 / Gmf". In order to match this with 50Ω, there is no choice but to set Gmf to 20mS, and the power consumption increases.

Therefore, according to this embodiment, it can be seen that the power consumption can be significantly reduced as compared with the conventional technique.

[Noise figure]
When the input impedance is matched as described above, the noise figure NF (Noise Figure) of the impedance matching circuit 180 is given by the following equation. It is assumed that the Q value of Lm is sufficiently large and the loss is negligible.
NF = ₁₀ log 10 (1+ (γ / (1 + Cl / Cf)))
(1 + 4Gmp / Gm))
However, γ is the thermal noise coefficient of the MOSFET, which is about “2/3”.

Here, as a numerical example,
Gm = 10mS
Gmp = 1mS
Cf = Cl = 0.2pF
Is substituted into the above equation, and NF = 1.67 dB.

On the other hand, when feedback is performed by a feedback amplifier as in the prior art, the noise figure NF is
NF = ₁₀ log 10 (1 + γ (1 + 4 / GmRs))
Therefore, when the above-mentioned Gmf = 20 mS is used, NF = 8.45 dB.

That is, a part of the noise current of the auxiliary amplifier 120 of this embodiment goes out to the ground through the load capacitance 136. Also, peaking is applied by the impedance matching circuit 180. Therefore, the deterioration of the noise figure is small as compared with the conventional technique. Therefore, according to this embodiment, it can be seen that noise can be significantly reduced as compared with the prior art.

[Transconductance gain]
When the input impedance is matched as described above, the transconductance gain Gain is given by the following equation.
Gain = Iout / Vs
= (Gm / 2) ((1 + Cl / Cf) / RsGmp) ^1/2

Here, as a numerical example,
Rs = 50Ω
Gm = 10mS
Gmp = 1mS
Cf = Cl = 0.2pF
Is substituted into the above equation, Gain = 31.5 mA / V.

On the other hand, when feedback is performed by a feedback amplifier as in the prior art, the transconductance gain Gain is
Gain = Iout / Vs
= Gm / (1 + RsGmf)
= Gm / 2
Therefore, when the above-mentioned Gm = 10 mS is used, Gain = 5 mA / V.

Therefore, according to this embodiment, since peaking is applied by the impedance matching circuit 180, it can be seen that even if an amplifier having the same transconductance (Gm) is used, the gain can be significantly improved as compared with the conventional technique.

[DC operating point]
FIG. 6 is a diagram showing an example of a DC operating point of the transconductance amplifier 100 according to the embodiment of the present technology.

This example shows an example in which the power supply voltage Vdd is set to 0.65V and an appropriate DC voltage is set for each part. As described above, it is assumed that each transistor stacked in four stages operates in the sub-threshold region.

As described above, the transconductance amplifier 100 of the embodiment of the present technology includes an auxiliary amplifier 120 and an impedance matching circuit 180 which have been subjected to negative feedback by the feedback capacitance 137. As a result, the gain of the transconductance amplifier 100 can be improved, and power consumption and noise can be reduced.

<2. Modification example>
[First modification]
FIG. 7 is a diagram showing a block configuration example of the transconductance amplifier 100 in the first modification of the embodiment of the present technology.

The transconductance amplifier 100 in this first modification divides the transconductance of the main amplifier 110 into 1: 2: 7, and is provided with a gain variable function of 0 dB, -10 dB, and -20 dB. That is, the amplifier 11 has a mutual conductance of Gm, the amplifier 12 has a mutual conductance of 2 Gm, and the amplifier 13 has a mutual conductance of 7 Gm.

The output currents of the amplifiers 11 to 13 are added and output as the output current Iout. The presence or absence of operation of the

amplifiers

12 and 13 is controlled by the control signals G0 and G1, respectively.

FIG. 8 is a diagram showing an example of the relationship between the control signal and the gain of the transconductance amplifier 100 in the first modification of the embodiment of the present technology.

The control signals G0 and G1 are signals for controlling the presence / absence of operation of the

amplifiers

12 and 13, respectively. If both G0 and G1 are "0", the

amplifiers

12 and 13 do not operate, only the amplifier 11 operates, and the gain becomes Gm · Q. Q is given by the following equation.
Q = (1/2) ((1 + Cl / Cf) / RsGmp) ^1/2

If G1 is "0" and G0 is "1", the amplifier 13 does not operate and the gain is 3 Gm · Q. Similarly, if G1 is "1" and G0 is "0", the amplifier 12 does not operate and the gain is 8 Gm · Q. If both G0 and G1 are "1", all the amplifiers 11 to 13 operate to reach 10 Gm · Q. The output level is based on the case where the gain is 10 Gm · Q (0 dB).

As described above, according to the first modification of this embodiment, the gain of the main amplifier 110 can be variably controlled. Even in this case, since the input impedance matching is performed by the auxiliary amplifier 120, changing the gain of the main amplifier 110 does not affect the impedance matching.

[Second variant]
FIG. 9 is a diagram showing a block configuration example of the transconductance amplifier 100 in the second modification of the embodiment of the present technology.

The transconductance amplifier 100 in this second modification is obtained by dividing the mutual conductance of the main amplifier 110 by binary weighting, and has a finer gain resolution than the first modification described above.

In this second modification, the gain Gain is given by the following equation.
Gain = (G0 + 2G1 + 2 ² G2 + ... + 2 ^N GN) ・ Gm ・ Q
Here, G0 to GN are gain control signals based on binary numbers of (N + 1) bits, and control the presence or absence of the corresponding amplifier operation as in the first modification described above.
[G0 ... GN] = [000 ... 0] to [111 ... 1]

As described above, according to the second modification of this embodiment, the gain of the main amplifier 110 can be variably controlled with a finer resolution.

[Third variant]
FIG. 10 is a diagram showing an example of a block configuration of a receiver in a third modification of the embodiment of the present technology.

The receiver in this third modification shows an example of a GNSS receiver including the transconductance amplifier 100 of the above-described embodiment. In this GNSS receiver, a current input mixer 200, an intermediate frequency processing unit 300, an AD conversion unit 400, and a signal processing device 500 are connected to the subsequent stage of the transconductance amplifier 100.

When the GNSS receiver and the LTE (Long Term Evolution) transmitter are mounted together in the same housing, the signal (1720 MHz) from the LTE transmitter is close to the GPS transmission frequency (1575 MHz). Further, the transmission level from the LTE transmitter is about +25 dBm, which is higher than the GPS reception level of −130 dBm. Therefore, the signal from the LTE transmitter can be a source of interference. In this respect, it is rather desirable that the band of the signal to be received in the GNSS receiver is narrow. Under such circumstances, it is suitable to use the transconductance amplifier 100, which can secure a wide dynamic range in the current mode operation, for the GNSS receiver.

The current input mixer 200 multiplies the output current Iout of the transconductance amplifier 100 with the 4-phase oscillation frequency LO (Local Oscillator) to generate a low-frequency intermediate frequency (IF) signal. The intermediate frequency processing unit 300 includes an amplifier that amplifies the intermediate frequency signal to a predetermined level, and a filter that removes interfering waves. The AD conversion unit 400 converts the intermediate frequency signal processed by the intermediate frequency processing unit 300 into a digital signal.

The signal processing device 500 uses the control signal RFAGC (Radio Frequency Automatic Gain Control) or IFAGC (Intermediate Frequency Automatic Gain Control) according to the reception level of the digital intermediate frequency signal to obtain the gain Gm of the main amplifier 110 and the intermediate frequency processing unit 300. Controls the gain of the amplifier. That is, when the reception level is higher than a predetermined threshold value, the gain of the main amplifier 110 is made relatively small. On the other hand, when the reception level is lower than the predetermined threshold value, the gain of the main amplifier 110 is relatively increased. The control signal RFAGC in this case can be handled according to the control signal of the first or second modification described above.

As described above, according to the third modification of this embodiment, the GNSS receiver can be configured by using the transconductance amplifier 100 of the above-described embodiment. Thereby, for example, even when the GNSS receiver and the LTE transmitter are mixedly mounted in the same housing, the distortion of the GNSS signal due to the high output LTE transmission signal can be suppressed and good positioning accuracy can be obtained. .. Further, in this case, the gain of the main amplifier 110 can be variably controlled by using the control signal of the first or second modification described above.

[Fourth variant]
FIG. 11 is a diagram showing a block configuration example of the transconductance amplifiers 101 and 102 in the fourth modification of the embodiment of the present technology.

Here, an example of a dual band GNSS receiver including two transformer conductance amplifiers 100 in the above-described embodiment is shown. This receiver is a device that receives signals in the L1 (1.6 GHz) frequency band and the L5 (1.2 GHz) frequency band. The outputs of the transconductance amplifiers 101 and 102 are supplied to the current input mixers 201 and 202, respectively.

In this dual band GNSS receiver, different values optimized for each frequency band are set for the series inductor 181, the shunt capacity 182, the gate capacity 135, the feedback capacity 137, and the load capacity 136. In this example, in the L1 frequency band, Lm = 12nH, Cm = 5.6pF, Cg = 0.85pF, and Cf = Cl = 0.2pF are set. Further, in the L5 frequency band, Lm = 16nH, Cm = 7.5pF, Cg = 1.1pF, and Cf = Cl = 0.26pF are set. As a result of performing a Spice simulation with such a setting, sufficient gain is obtained in each of the L1 frequency band and the L5 frequency band, and good impedance matching characteristics with a voltage standing wave ratio VSWR = 1.5 are obtained. I have confirmed that it can be obtained.

As described above, according to the fourth modification of this embodiment, by appropriately setting the values of each part, sufficient gain and good impedance matching characteristics can be obtained in each of a plurality of frequency bands. ..

Note that the above-described embodiment shows an example for embodying the present technology, and the matters in the embodiment and the matters specifying the invention in the claims have a corresponding relationship with each other. Similarly, the matters specifying the invention within the scope of claims and the matters in the embodiment of the present technology having the same name have a corresponding relationship with each other. However, the present technology is not limited to the embodiment, and can be embodied by applying various modifications to the embodiment without departing from the gist thereof.

Further, the processing procedure described in the above-described embodiment may be regarded as a method having these series of procedures, or as a program for causing a computer to execute these series of procedures or as a recording medium for storing the program. You may catch it. As this recording medium, for example, a CD (Compact Disc), MD (MiniDisc), DVD (Digital Versatile Disc), memory card, Blu-ray Disc (Blu-ray (registered trademark) Disc) and the like can be used.

It should be noted that the effects described in the present specification are merely examples and are not limited, and other effects may be obtained.

The present technology can have the following configurations.
(1) A main amplifier that converts the voltage of the input signal into a current and outputs it.
An auxiliary amplifier connected in parallel with the main amplifier,
The feedback capacitance that inverts the phase of the output of the auxiliary amplifier and feeds it back to the input side,
The gate capacitance for grounding the input of the auxiliary amplifier and
The load capacity for grounding the output of the auxiliary amplifier and
A transconductance amplifier including an impedance matching circuit that matches the signal source impedance of the input signal with the input impedance of the auxiliary amplifier.
(2) The transconductance amplifier according to (1), further comprising an in-phase feedback circuit that feeds back the output of the auxiliary amplifier to the inputs of the main amplifier and the auxiliary amplifier.
(3) The transconductance amplifier according to (1) or (2) above, wherein each of the main amplifier and the auxiliary amplifier includes a thick film transistor that inputs the input signal to the gate.
(4) The transconductance amplifier according to any one of (1) to (3) above, wherein each of the main amplifier and the auxiliary amplifier includes a thin film transistor having a cascode configuration in an output unit.
(5) The transconductance amplifier according to any one of (1) to (4), further comprising a bias generation circuit for generating a bias voltage for the main amplifier and the auxiliary amplifier.
(6) The transconductance amplifier according to any one of (1) to (5) above, wherein the impedance matching circuit is an LC circuit including a series inductor and a shunt capacitance.
(7) The transconductance amplifier according to any one of (1) to (6) above, wherein the main amplifier includes a plurality of amplifiers connected in parallel.
(8) The transconductance amplifier according to (7), wherein at least one of the plurality of amplifiers is controlled to operate or not according to a predetermined control signal.
(9) The transconductance amplifier according to (7) or (8), wherein the gain of each of the plurality of amplifiers is a predetermined fixed value.
(10) The transconductance amplifier according to (7) or (8), wherein the gain of each of the plurality of amplifiers is twice or half that of the other amplifiers.
(11) The main amplifier that converts the voltage of the received input signal into a current and outputs it, the auxiliary amplifier connected in parallel with the main amplifier, and the output phase of the auxiliary amplifier are inverted and fed back to the input side. Transconductance including a feedback capacitance, a gate capacitance that grounds the input of the auxiliary amplifier, a load capacitance that grounds the output of the auxiliary amplifier, and an impedance matching circuit that matches the impedance of the input signal and the input of the auxiliary amplifier. With an amplifier
A current input mixer that generates an intermediate frequency signal by multiplying the output current of the main amplifier and the output of the local oscillator.
An intermediate frequency processing unit that amplifies the intermediate frequency signal to a predetermined level and removes interfering waves.
An analog-to-digital converter that converts the amplified intermediate frequency signal from an analog value to a digital value,
A receiving device including a signal processing unit that performs predetermined signal processing on an intermediate frequency signal converted into a digital value.
(12) The receiving device according to (11) above, which receives a signal of a global satellite positioning system as the input signal.
(13) The receiving device according to (11) or (12), further comprising the plurality of transconductance amplifiers that receive signals in different frequency bands as the input signals.

11, 12, 13

Amplifier

100, 101, 102 Transconductance Amplifier 110 Main Amplifier (Gm)
120 Auxiliary Amplifier (Gmp)
135 Gate capacity (Cg)
136 Load capacity (Cl)
137 Return capacity (Cf)
138 resistance (Rhigh)
140 Common Mode Feedback Circuit (CMFB)
141 Operational amplifier 150 Bias generation circuit 170 Static electricity protection element 180 Impedance matching circuit 181 Series inductor (Lm)
182 shunt capacity (Cm)
200, 201, 202 Current input mixer 300 Intermediate frequency processing unit 400 AD conversion unit 500 Signal processing device

Claims

The main amplifier that converts the voltage of the input signal into current and outputs it,
An auxiliary amplifier connected in parallel with the main amplifier,
The feedback capacitance that inverts the phase of the output of the auxiliary amplifier and feeds it back to the input side,
The gate capacitance for grounding the input of the auxiliary amplifier and
The load capacity for grounding the output of the auxiliary amplifier and
A transconductance amplifier including an impedance matching circuit that matches the signal source impedance of the input signal with the input impedance of the auxiliary amplifier.
The transconductance amplifier according to claim 1, further comprising an in-phase feedback circuit that feeds back the output of the auxiliary amplifier to the inputs of the main amplifier and the auxiliary amplifier.
The transconductance amplifier according to claim 1, wherein each of the main amplifier and the auxiliary amplifier includes a thick film transistor that inputs the input signal to the gate.
The transconductance amplifier according to claim 1, wherein each of the main amplifier and the auxiliary amplifier includes a thin film transistor having a cascode configuration in an output unit.
The transconductance amplifier according to claim 1, further comprising a bias generation circuit for generating a bias voltage for the main amplifier and the auxiliary amplifier.
The transconductance amplifier according to claim 1, wherein the impedance matching circuit is an LC circuit including a series inductor and a shunt capacitance.
The transconductance amplifier according to claim 1, wherein the main amplifier includes a plurality of amplifiers connected in parallel.
The transconductance amplifier according to claim 7, wherein at least one of the plurality of amplifiers is controlled to operate or not according to a predetermined control signal.
The transconductance amplifier according to claim 7, wherein the gain of each of the plurality of amplifiers is a predetermined fixed value.
The transconductance amplifier according to claim 7, wherein the gain of each of the plurality of amplifiers is twice or half that of the other amplifiers.
A main amplifier that converts the voltage of the received input signal into a current and outputs it, an auxiliary amplifier connected in parallel with the main amplifier, and a feedback capacitance that inverts the phase of the output of the auxiliary amplifier and returns it to the input side. A transmission amplifier including a gate capacitance for grounding the input of the auxiliary amplifier, a load capacitance for grounding the output of the auxiliary amplifier, and an impedance matching circuit for matching the impedance of the input signal with the input of the auxiliary amplifier.
A current input mixer that generates an intermediate frequency signal by multiplying the output current of the main amplifier and the output of the local oscillator.
An intermediate frequency processing unit that amplifies the intermediate frequency signal to a predetermined level and removes interfering waves.
An analog-to-digital converter that converts the amplified intermediate frequency signal from an analog value to a digital value,
A receiving device including a signal processing unit that performs predetermined signal processing on the intermediate frequency signal converted into the digital value.
The receiving device according to claim 11, which receives a signal of a global satellite positioning system as the input signal.
The receiving device according to claim 11, further comprising the plurality of transconductance amplifiers that receive signals in different frequency bands as the input signals.