CN112557876A - Device for calibrating chip simulation parameters and test method thereof - Google Patents
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Abstract
The invention discloses a device and a method for calibrating chip simulation parameters, and the device comprises a tester for calibrating a chip to be calibrated, wherein the tester comprises a test unit for acquiring the simulation parameters of the chip to be calibrated, a data processing unit and a communication port A, and the data processing unit is connected with the test unit and the communication port A. The invention calculates the difference value between the analog quantities corresponding to the adjacent calibration registers of the parameter to be calibrated through two measurement results, thereby confirming the pre-estimated value of the calibration register corresponding to the standard value of the parameter to be calibrated, greatly reducing the range of the calibration test interval, namely reducing the test time; meanwhile, in order to avoid the measurement error from causing the calculation deviation of the calibration register estimated value corresponding to the standard value of the parameter to be calibrated, the traversal of the calibration test interval is flexibly selected, the correct chip to be calibrated can be calibrated, the parameter to be calibrated of the chip is calibrated to be closest to the standard value, and the calibration consistency of the chip to be calibrated is ensured.
Description
Technical Field
The invention relates to a device for calibrating chip simulation parameters and a test method thereof, belonging to the technical field of chip mass production test.
Background
Along with the improvement of the integration level of the chip and the limitation of the chip manufacturing process, a certain deviation is easy to exist between the actual value of the chip simulation parameter and the design standard value, and various performance indexes of the chip are influenced, so that the design of the deviation is avoided by calibrating the simulation parameters of more and more chips.
At present, two methods are commonly adopted for calibrating simulation parameters of a chip: one is that a standard parameter value is input externally, and the inside of the chip is automatically calibrated through a high-precision comparison circuit, although the test mode does not need to be measured externally, the performance dependence on the comparison circuit inside the chip is high, error information is not convenient to obtain after errors occur, and early debugging is difficult; the other is to send the simulation parameters out of the test port for measurement, and adjust the calibration value according to the measurement result until the measurement result meets the specification of the parameters.
Disclosure of Invention
Aiming at the problems in the prior art, the invention provides a device for calibrating the simulation parameters of the chip and a test method thereof, which can reduce the measurement times in the mass production test, reduce the test time and ensure the optimal simulation parameter performance of the calibrated chip.
In order to achieve the purpose, the invention adopts the following technical scheme: a device for calibrating chip simulation parameters comprises a test machine for calibrating a chip to be calibrated, wherein the test machine comprises a test unit for acquiring simulation parameters of the chip to be calibrated, a data processing unit and a communication port A, and the data processing unit is connected with the test unit and the communication port A;
the chip to be calibrated at least comprises a calibration register, a calibration control unit, a test output port and a communication port B, wherein the communication port B is connected with the calibration register, the calibration register is connected with the calibration control unit, and the calibration control unit is connected with the test output port;
preferably, the test unit is connected to a test output port, and the communication port a is connected to the communication port B.
Preferably, the analog parameters of the chip to be calibrated include voltage, current and frequency.
Preferably, the communication port A and the communication port B communicate with each other through an I2C or SPI communication protocol.
A test method of a device for calibrating chip simulation parameters comprises the following steps: the test machine respectively inputs two different initial values to the calibration registers of the chip to be calibrated, and then obtains the difference value of the simulation parameters corresponding to the adjacent calibration registers by processing the measured output values of the two simulation parameters;
the test machine calculates a theoretical value of the calibration register corresponding to the standard value of the simulation parameter according to the difference value, the first input calibration register value and the standard value of the simulation parameter, and inputs the theoretical value and a preset traversal range to the chip to be calibrated;
the test machine measures and records the simulation parameter output of the chip calibration register to be calibrated in a traversal range preset by a theoretical value, finds the simulation parameter test value closest to the simulation parameter standard value and records the corresponding calibration register value, then judges whether the simulation parameter test value is in the test range, if the simulation parameter test value is in the test range, the calibration register value is correct, the recorded calibration register value is input to the calibration register of the chip to be calibrated through the communication port, the calibration is completed, and if the calibration register value is not in the test range, the calibration fails.
If the calibration standard value of the simulation parameter is AsThe analog parameter may be voltage, current or frequency, the calibration bit is m bits, and the most accurate of the register is calibratedLarge value of Rmax＝2mThen, the whole testing method comprises the following steps:
step one, a tester inputs a value R to a calibration register of the chip to be calibrated through a communication port1，R1Has a range of (0, R)max) Measuring the analog parameter value A corresponding to the calibration register value1；
Step two, the tester inputs a value R to a calibration register of the chip to be calibrated through a communication port2，R2Has a range of (0, R)max)，R1≠R2Measuring the analog parameter value A corresponding to the calibration register value2；
Thirdly, the data processing unit of the testing machine calculates the difference A between the simulation parameters corresponding to the adjacent calibration registers0，A0＝(A2-A1)/(R2-R1)；
Step four, the data processing unit of the testing machine calculates the estimated value R of the calibration register corresponding to the calibration standard value of the simulation parameter, wherein R is R1+(As-A1)/A0；
Step five, assuming the offset n of the pre-estimated value of the calibration register, and determining the distribution interval of the calibration register traversing the calibration test to be [ (R-n), (R + n) ];
inputting the estimated value R and the offset n of the calibration register to the chip to be calibrated through a communication port by the tester, and measuring the simulation parameters corresponding to the calibration registers in the interval determined in the fifth step corresponding to the chip to be calibrated by the test unit of the tester;
step seven, the data processing unit of the testing machine compares each simulation parameter measured in the step six with a standard simulation parameter value respectively, selects a simulation parameter measured value closest to the standard simulation parameter value, and records a corresponding calibration register value;
and step eight, judging whether the simulation parameter measured value closest to the standard simulation parameter value selected in the step seven meets the test spec by the test machine data processing unit, if so, calibrating correctly, then inputting the corresponding calibration register value recorded in the step seven into the calibration register of the chip to be calibrated through the communication port, completing calibration, and otherwise, failing calibration.
Compared with the prior art, the invention adopts the test machine comprising the test unit for obtaining the simulation parameters of the chip to be calibrated, the data processing unit and the communication port A to test the simulation parameters of the chip to be calibrated, two different initial values are respectively input to the calibration register of the chip to be calibrated through the communication port A, then the output values of the two simulation parameters are measured through the test unit, then the data processing unit is utilized to process the output values, corresponding judgment is made, and the test of the simulation parameters of the chip to be calibrated, such as voltage, current or frequency, is realized; the measurement times in the mass production test are reduced, the test time is shortened, and the optimal performance of the simulation parameters of the calibrated chip is ensured. Meanwhile, the test method calculates the difference value between the analog quantities corresponding to the adjacent calibration registers of the parameter to be calibrated through two measurement results, so that the estimated value of the calibration register corresponding to the standard value of the parameter to be calibrated is confirmed, the range of a calibration test interval is greatly reduced, and the test time is shortened; meanwhile, in order to avoid the measurement error from causing the calculation deviation of the calibration register estimated value corresponding to the standard value of the parameter to be calibrated, the traversal of the calibration test interval is flexibly selected, the correct chip to be calibrated can be calibrated, the parameter to be calibrated of the chip is calibrated to be closest to the standard value, and the calibration consistency of the chip to be calibrated is ensured. When the technology is applied to mass production test, the chips at different stations have the same calibration times for the same parameter to be calibrated, synchronous processing can be realized, the processing logic of a test program is simplified, and the convenience of mass production test development is improved.
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FIG. 1 is a schematic structural view of the present invention;
FIG. 2 is a flow chart of the testing method of the present invention.
Detailed Description
The technical solutions in the implementation of the present invention will be made clear and fully described below with reference to the accompanying drawings, and the described embodiments are only a part of the embodiments of the present invention, but not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.
The device for calibrating the simulation parameters of the chip, as shown in fig. 1, comprises a testing machine for calibrating the chip to be calibrated, wherein the testing machine comprises a testing unit for obtaining the simulation parameters of the chip to be calibrated, a data processing unit and a communication port A, and the data processing unit is connected with the testing unit and the communication port A;
the chip to be calibrated at least comprises a calibration register, a calibration control unit, a test output port and a communication port B, wherein the communication port B is connected with the calibration register, the calibration register is connected with the calibration control unit, and the calibration control unit is connected with the test output port;
the test unit is connected with the test output port, and the communication port A is connected with the communication port B.
Preferably, the analog parameters of the chip to be calibrated include voltage, current and frequency.
Preferably, the communication port A and the communication port B communicate with each other through an I2C or SPI communication protocol. The I2C or SPI communication protocol is a conventional communication protocol, and the two communication control modules are built in a common chip, so that ports adopting the two communication protocols do not need to be correspondingly improved, and the application range is wider.
The invention adopts a testing machine comprising a testing unit for obtaining analog parameters of a chip to be calibrated, a data processing unit and a communication port A to test the analog parameters of the chip to be calibrated, two different initial values are respectively input to a calibration register of the chip to be calibrated through the communication port A, then the output values of the two analog parameters are measured through the testing unit, then the data processing unit is utilized to process the output values, corresponding judgment is made, and the test of the analog parameters of the chip to be calibrated, such as voltage, current or frequency, is realized; the measurement times in the mass production test are reduced, the test time is shortened, and the optimal performance of the simulation parameters of the calibrated chip is ensured.
A test method of a device for calibrating chip simulation parameters comprises the following steps: the test machine respectively inputs two different initial values to the calibration registers of the chip to be calibrated, and then obtains the difference value of the simulation parameters corresponding to the adjacent calibration registers by processing the measured output values of the two simulation parameters; the two different initial value values are both smaller than the maximum value of the calibration register, and the difference between the two values is a little larger, so that the error caused by measurement can be reduced for the parameter to be calibrated with smaller difference value of the analog parameter corresponding to the adjacent calibration register;
the test machine calculates a theoretical value of the calibration register corresponding to the standard value of the simulation parameter according to the difference value, the first input calibration register value and the standard value of the simulation parameter, and inputs the theoretical value and a preset traversal range to the chip to be calibrated;
the test machine measures and records the simulation parameter output of the chip calibration register to be calibrated in a traversal range preset by a theoretical value, finds the simulation parameter test value closest to the simulation parameter standard value and records the corresponding calibration register value, then judges whether the simulation parameter test value is in the test range, if the simulation parameter test value is in the test range, the calibration register value is correct, the recorded calibration register value is input to the calibration register of the chip to be calibrated through the communication port, the calibration is completed, and if the calibration register value is not in the test range, the calibration fails.
Specifically, if the calibration standard value of the simulation parameter is AsThe analog parameter may be voltage, current or frequency, the calibration bit is m bits, and the maximum value of the calibration register is Rmax＝2mThen, the whole testing method comprises the following steps:
step one, a tester inputs a value R to a calibration register of the chip to be calibrated through a communication port1，R1Has a range of (0, R)max) Measuring the analog parameter value A corresponding to the calibration register value1；
Step two, the tester inputs a value R to a calibration register of the chip to be calibrated through a communication port2，R2Has a range of (0, R)max)，R1≠R2Measuring calibration registersValue-corresponding simulation parameter value A2；
Thirdly, the data processing unit of the testing machine calculates the difference A between the simulation parameters corresponding to the adjacent calibration registers0，A0＝(A2-A1)/(R2-R1)；
Step four, the data processing unit of the testing machine calculates the estimated value R of the calibration register corresponding to the calibration standard value of the simulation parameter, wherein R is R1+(As-A1)/A0；
Step five, assuming the offset n of the pre-estimated value of the calibration register, and determining the distribution interval of the calibration register traversing the calibration test to be [ (R-n), (R + n) ];
inputting the estimated value R and the offset n of the calibration register to the chip to be calibrated through a communication port by the tester, and measuring the simulation parameters corresponding to the calibration registers in the interval determined in the fifth step corresponding to the chip to be calibrated by the test unit of the tester;
step seven, the data processing unit of the testing machine compares each simulation parameter measured in the step six with a standard simulation parameter value respectively, selects a simulation parameter measured value closest to the standard simulation parameter value, and records a corresponding calibration register value;
and step eight, judging whether the simulation parameter measured value closest to the standard simulation parameter value selected in the step seven meets the test spec by the test machine data processing unit, if so, calibrating correctly, then inputting the corresponding calibration register value recorded in the step seven into the calibration register of the chip to be calibrated through the communication port, completing calibration, and otherwise, failing calibration.
Example (b):
the analog parameter of the chip to be calibrated is voltage, and the standard calibration value is VsThe calibration bit is 8 bits, and the maximum value of the calibration register is Rmax＝28＝256。
A method for testing a device for calibrating chip simulation parameters, as shown in fig. 2, includes the following steps:
step one, a tester sends a signal to the calibration of the chip to be calibrated through a communication portRegister input value R1Let R1To calibrate 1/4 the maximum value of the register, i.e.
Measuring analog voltage value V corresponding to calibration register value1；
Step two, the tester inputs a value R to a calibration register of the chip to be calibrated through a communication port2Let R2To calibrate 3/4 the maximum value of the register, i.e.
Measuring analog voltage value V corresponding to calibration register value2；
Thirdly, the data processing unit of the testing machine calculates the difference V between the simulation parameters corresponding to the adjacent calibration registers0，V0＝(V2-V1)/(R2-R1)；
Step four, the data processing unit of the testing machine calculates the estimated value R of the calibration register corresponding to the voltage calibration standard value, namely, calculates the theoretical calibration register value corresponding to the standard value, where R is R1+(Vs-V1)/V0；
Step five, assuming that the offset n of the pre-estimated value of the calibration register is 2, determining the distribution interval of the calibration register traversing the calibration test to be [ (R-2), (R +2) ];
step six, the tester inputs the estimated value R and the offset n of the calibration register to the chip to be calibrated through a communication port, and then a test unit of the tester measures the voltage corresponding to each calibration register in the interval determined in the step five corresponding to the chip to be calibrated (namely measures the simulation parameter value corresponding to each calibration register value in the distribution interval);
step seven, the data processing unit of the testing machine compares each voltage measured in the step six with a standard voltage value respectively, selects a voltage measurement value closest to the standard voltage value, and records a corresponding calibration register value;
and step eight, judging whether the voltage measurement value closest to the standard voltage value selected in the step seven meets the test spec by the data processing unit of the testing machine, if so, calibrating correctly, then inputting the corresponding calibration register value recorded in the step seven into the calibration register of the chip to be calibrated through the communication port, completing calibration, and otherwise, failing calibration.
Wherein two input values R1、R2All values of (1) are (0, R)max) The specific value does not have a strict proportional relationship requirement, and the above embodiment is only an example as long as R is1≠R2And the difference between the two is a little larger, so that the error brought by measurement can be reduced for the parameter to be calibrated with smaller difference value of the simulation parameters corresponding to the adjacent calibration registers.
For the analog parameters such as current or frequency of the chip to be calibrated, the above method can also be used for testing, as long as each analog voltage value is replaced by an analog current value or an analog frequency value, and the whole testing process is the same, so that the details are not repeated herein.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should make the description as a whole, and the embodiments may be appropriately combined to form other embodiments understood by those skilled in the art.
Claims (6)
1. A device for calibrating chip simulation parameters is characterized by comprising a tester for calibrating a chip to be calibrated, wherein the tester comprises a test unit for acquiring simulation parameters of the chip to be calibrated, a data processing unit and a communication port A, and the data processing unit is connected with the test unit and the communication port A;
the chip to be calibrated at least comprises a calibration register, a calibration control unit, a test output port and a communication port B, wherein the communication port B is connected with the calibration register, the calibration register is connected with the calibration control unit, and the calibration control unit is connected with the test output port;
the test unit is connected with the test output port, and the communication port A is connected with the communication port B.
2. The apparatus of claim 1, wherein the analog parameters of the chip to be calibrated include voltage, current and frequency.
3. The device of claim 1, wherein the communication port a and the communication port B communicate with each other through I2C or SPI communication protocol.
4. A method for testing the apparatus for calibrating simulation parameters of a chip according to claim 1, comprising the steps of:
the test machine respectively inputs two different initial values to the calibration registers of the chip to be calibrated, and then obtains the difference value between the simulation parameters corresponding to the adjacent calibration registers by processing the measured output values of the two simulation parameters;
the test machine calculates a theoretical value of the calibration register corresponding to the standard value of the simulation parameter according to the difference value, the first input calibration register value and the standard value of the simulation parameter, and inputs the theoretical value and a preset traversal range to the chip to be calibrated;
the test machine measures and records the simulation parameter output of the chip calibration register to be calibrated in a traversal range preset by a theoretical value, finds the simulation parameter test value closest to the simulation parameter standard value and records the corresponding calibration register value, then judges whether the simulation parameter test value is in the test range, if the simulation parameter test value is in the test range, the calibration register value is correct, the recorded calibration register value is input to the calibration register of the chip to be calibrated through the communication port, the calibration is completed, and if the calibration register value is not in the test range, the calibration fails.
5. The method as claimed in claim 4, wherein if the calibration standard value of the simulation parameter is AsThe calibration bit is m bits, and the maximum value of the calibration register is Rmax＝2mThen, the whole testing method comprises the following steps:
step one, a tester inputs a value R to a calibration register of the chip to be calibrated through a communication port1，R1Has a range of (0, R)max) Measuring the analog parameter value A corresponding to the calibration register value1；
Step two, the tester inputs a value R to a calibration register of the chip to be calibrated through a communication port2，R2Has a range of (0, R)max)，R1≠R2Measuring the analog parameter value A corresponding to the calibration register value2；
Thirdly, the data processing unit of the testing machine calculates the difference A between the simulation parameters corresponding to the adjacent calibration registers0，A0＝(A2-A1)/(R2-R1)；
Step four, the data processing unit of the testing machine calculates the estimated value R of the calibration register corresponding to the calibration standard value of the simulation parameter, wherein R is R1+(As-A1)/A0；
Step five, assuming the offset n of the pre-estimated value of the calibration register, and determining the distribution interval of the calibration register traversing the calibration test to be [ (R-n), (R + n) ];
inputting the estimated value R and the offset n of the calibration register to the chip to be calibrated through a communication port by the tester, and measuring the simulation parameters corresponding to the calibration registers in the interval determined in the fifth step corresponding to the chip to be calibrated by the test unit of the tester;
step seven, the data processing unit of the testing machine compares each simulation parameter measured in the step six with a standard simulation parameter value respectively, selects a simulation parameter measured value closest to the standard simulation parameter value, and records a corresponding calibration register value;
and step eight, judging whether the simulation parameter measured value closest to the standard simulation parameter value selected in the step seven meets the test spec by the test machine data processing unit, if so, calibrating correctly, then inputting the corresponding calibration register value recorded in the step seven into the calibration register of the chip to be calibrated through the communication port, completing calibration, and otherwise, failing calibration.
6. The method for testing the device for calibrating the simulation parameters of the chip according to claim 4 or 5, wherein the simulation parameters of the chip to be calibrated are voltage, current or frequency.
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