CN105811982A - ADC chip reference voltage testing and calibration method - Google Patents
ADC chip reference voltage testing and calibration method Download PDFInfo
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- CN105811982A CN105811982A CN201610143948.1A CN201610143948A CN105811982A CN 105811982 A CN105811982 A CN 105811982A CN 201610143948 A CN201610143948 A CN 201610143948A CN 105811982 A CN105811982 A CN 105811982A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/10—Calibration or testing
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Abstract
The invention discloses an ADC chip reference voltage testing and calibration method. A testing circuit is adopted for providing an accurate standard reference voltage signal Vstd, the signal is input into a comparator in a chip IC, the comparator compares a voltage Vref to be calibrated of an ADC with the standard reference voltage signal Vstd and inputs a voltage comparison result into a calibration value generation module, the calibration value generation module obtains a voltage calibration parameter trim_para according to the magnitude of the difference between the Vref and the Vstd, and a reference voltage generation circuit adjusts an output reference voltage value according to the voltage calibration parameter trim_para. According to the invention, an external testing device does not need a voltage measuring instrument or a voltage comparator; in addition, in the testing process, a testing communication pin is not needed for wiring the voltage correction parameter into the IC, and instead, the IC realize the internal self-calibration of the reference voltage, so that the testing time is relatively saved.
Description
Technical field
The present invention relates to a kind of calibration steps, specifically a kind of ADC chip reference voltage detection calibration method.
Background technology
In integrated circuit (IntegratedCircuit is called for short IC) industry, IC testing cost accounts for a considerable part for IC total production cost, and testing expense ratio shared by circuit and system total cost constantly rises.Testing cost was directly proportional to the time used by test.Producing in design at IC, the testing cost how reducing IC becomes an important topic now.Due to the deviation in chip manufacturing, in the every a piece of ADC chip on wafer, between reference voltage and required standard voltage value, all there is certain deviation.And only when the reference voltage precision of ADC is sufficiently high, the precision of ADC just can be guaranteed.So in the production test of high-precision adc chip, the reference voltage calibration of ADC is an in demand link in its IC test.
At present, detection calibration method in the reference voltage of ADC chip is generally: by the test pin of IC, reference voltage to be corrected is exported, external voltage comparator is utilized to obtain the comparative result of reference voltage level and standard voltage value by external test facility, and comparative result, calculate correction parameter values, then, correction parameter values is written in IC by test equipment by the test communications pins of extra IC.The correction parameter values that reference voltage calibration circuit within IC writes according to outside, carries out the calibration of 1 reference voltage.According to same step, carry out the calibration of 2 reference voltages ... according to same step, carry out the calibration of n reference voltage.The limitation of the method is in that: one, need external test facility with voltage comparator resource；Two since it is desired that will correct parameter read-in in IC by testing communications pins, so it is relatively long to test the required time；Three, IC volume production carry out high-volume test time, in order to improve testing efficiency, test be all disposable as far as possible, test more IC concurrently.But owing to the test resource on test equipment is limited, it is contemplated that the reason of above-mentioned first and second point, test equipment is once tested the number of supported IC and is just restricted, so test is relatively inefficient.
Summary of the invention
It is an object of the invention to provide a kind of ADC chip reference voltage detection calibration method, with the problem solving to propose in above-mentioned background technology.
For achieving the above object, the present invention provides following technical scheme:
nullA kind of ADC chip reference voltage detection calibration method，Test circuit is adopted to provide a canonical reference voltage signal Vstd accurately，This signal is input to the comparator within chip IC，Voltage Vref to be calibrated for ADC and canonical reference voltage Vstd is compared by comparator，And voltage comparative result is input to calibration value generation module，The function of calibration value generation module is according to the inclined extent of Vref and Vstd，Obtain voltage calibration parameter trim_para，The reference voltage level of its output is adjusted by generating circuit from reference voltage according to voltage calibration parameter trim_para，Making the voltage Vref to be calibrated bit wide calibrating parameter trim_para is 16 bits，It range for 0x0000～0xffff，The value of calibration parameter and the adjusted value Δ V direct proportionality of reference voltage，When starting to calibrate，Trim_para=0x8000，Comparison output result according to voltage comparator，Reference voltage can to just、Negative both direction adjustment，0x0000 correspondence negative value adjusts maximum-Δ Vmax，0xffff correspondence positive voltage value adjusts maximum Δ Vmax，The detection calibration of reference voltage is the process of an iteration，2 conventional point-scores are adopted to adjust calibration parameter value，Described 2 point-scores，Refer to when starting to calibrate，Trim_para=0x8000，During each iterative calibration，New trim_para value is obtained by following logical operations: set iterations sequence number as i，During ith iteration test, calibration parameter value is pi；The higher limit of trim_para value is pa, namely during trim_para=pa, voltage ratio relatively obtains Vref more than Vstd, if the lower limit of trim_para value is pb, namely during trim_para=pb, voltage ratio relatively obtains Vref less than Vstd, and in the process of iterative calibration, the value of pi, pa, pb relatively exports result and adjusts according to voltage ratio.
As the present invention further scheme: through the 1st iterative calibration, namely can determine that the highest-order bit of trim_para is 1 or is 0, through the 2nd iterative calibration, namely can determine that the second highest bit of trim_para is 1 or is 0, at most through 16 iterative calibration, namely can determine that last calibration parameter value.
Compared with prior art, the invention has the beneficial effects as follows: one, do not need external test facility with voltage-measuring equipment or voltage comparator resource；Two, need not by testing communications pins by voltage correction parameter read-in to IC in test process, but the inside self calibration being realized reference voltage by IC, relatively save the testing time；Three, considering the reason of above-mentioned first and second advantage, the test resource on test equipment is required relatively low by this scheme, and the number that test equipment once tests supported IC is more, improves the efficiency of test, saves testing cost.
Accompanying drawing explanation
Fig. 1 is the theory diagram of ADC chip reference voltage detection calibration method.
Detailed description of the invention
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, it is clear that described embodiment is only a part of embodiment of the present invention, rather than whole embodiments.Based on the embodiment in the present invention, the every other embodiment that those of ordinary skill in the art obtain under not making creative work premise, broadly fall into the scope of protection of the invention.
nullRefer to Fig. 1，In the embodiment of the present invention，A kind of ADC chip reference voltage detection calibration method，Test circuit is adopted to provide a canonical reference voltage signal Vstd accurately，This signal is input to the comparator within chip IC，Voltage Vref to be calibrated for ADC and canonical reference voltage Vstd is compared by comparator，And voltage comparative result is input to calibration value generation module，The function of calibration value generation module is according to the inclined extent of Vref and Vstd，Obtain voltage calibration parameter trim_para，The reference voltage level of its output is adjusted by generating circuit from reference voltage according to voltage calibration parameter trim_para，Making the voltage Vref to be calibrated bit wide calibrating parameter trim_para is 16 bits，It range for 0x0000～0xffff，The value of calibration parameter and the adjusted value Δ V direct proportionality of reference voltage，When starting to calibrate，Trim_para=0x8000，Comparison output result according to voltage comparator，Reference voltage can to just、Negative both direction adjustment，0x0000 correspondence negative value adjusts maximum-Δ Vmax，0xffff correspondence positive voltage value adjusts maximum Δ Vmax，The detection calibration of reference voltage is the process of an iteration，2 conventional point-scores are adopted to adjust calibration parameter value，Described 2 point-scores，Refer to when starting to calibrate，Trim_para=0x8000，During each iterative calibration，New trim_para value is obtained by following logical operations: set iterations sequence number as i，During ith iteration test, calibration parameter value is pi；The higher limit of trim_para value is pa, namely during trim_para=pa, voltage ratio relatively obtains Vref more than Vstd, if the lower limit of trim_para value is pb, namely during trim_para=pb, voltage ratio relatively obtains Vref less than Vstd, and in the process of iterative calibration, the value of pi, pa, pb relatively exports result and adjusts according to voltage ratio.
It is illustrated below:
When starting to calibrate, pa=0xffff, pb=0x0000, p1=0x8000.
During ith iteration calibration, if voltage comparative result obtains Vref less than Vstd,
Pa value is constant, pb=pi-1, pi=(pa+pb)/2, i=i+1；
If voltage comparative result obtains Vref more than Vstd,
Pa=pi-1, pb value is constant, pi=(pa+pb)/2, i=i+1.
According to above description it can be seen that through the 1st iterative calibration, namely can determine that the highest-order bit of trim_para is 1 or is 0.Through the 2nd iterative calibration, namely can determine that the second highest bit of trim_para is 1 or is 0.At most through 16 iterative calibration, namely can determine that last calibration parameter value.
It is obvious to a person skilled in the art that the invention is not restricted to the details of above-mentioned one exemplary embodiment, and when without departing substantially from the spirit of the present invention or basic feature, it is possible to realize the present invention in other specific forms.Therefore, no matter from which point, embodiment all should be regarded as exemplary, and be nonrestrictive, the scope of the invention rather than described above limits, it is intended that all changes in the implication of the equivalency dropping on claim and scope included in the present invention.Any accompanying drawing labelling in claim should be considered as the claim that restriction is involved.
In addition, it is to be understood that, although this specification is been described by according to embodiment, but not each embodiment only comprises an independent technical scheme, this narrating mode of description is only for clarity sake, description should be made as a whole by those skilled in the art, and the technical scheme in each embodiment through appropriately combined, can also form other embodiments that it will be appreciated by those skilled in the art that.
Claims (2)
- null1. an ADC chip reference voltage detection calibration method，It is characterized in that，Test circuit is adopted to provide a canonical reference voltage signal Vstd accurately，This signal is input to the comparator within chip IC，Voltage Vref to be calibrated for ADC and canonical reference voltage Vstd is compared by comparator，And voltage comparative result is input to calibration value generation module，The function of calibration value generation module is according to the inclined extent of Vref and Vstd，Obtain voltage calibration parameter trim_para，The reference voltage level of its output is adjusted by generating circuit from reference voltage according to voltage calibration parameter trim_para，Making the voltage Vref to be calibrated bit wide calibrating parameter trim_para is 16 bits，It range for 0x0000 ~ 0xffff，The value of calibration parameter and the adjusted value Δ V direct proportionality of reference voltage，When starting to calibrate，trim_para=0x8000，Comparison output result according to voltage comparator，Reference voltage can to just、Negative both direction adjustment，0x0000 correspondence negative value adjusts maximum-Δ Vmax，0xffff correspondence positive voltage value adjusts maximum Δ Vmax，The detection calibration of reference voltage is the process of an iteration，2 conventional point-scores are adopted to adjust calibration parameter value，Described 2 point-scores，Refer to when starting to calibrate，trim_para=0x8000，During each iterative calibration，New trim_para value is obtained by following logical operations: set iterations sequence number as i，During ith iteration test, calibration parameter value is pi；The higher limit of trim_para value is pa, namely during trim_para=pa, voltage ratio relatively obtains Vref more than Vstd, if the lower limit of trim_para value is pb, namely during trim_para=pb, voltage ratio relatively obtains Vref less than Vstd, and in the process of iterative calibration, the value of pi, pa, pb relatively exports result and adjusts according to voltage ratio.
- 2. ADC chip reference voltage detection calibration method according to claim 1, it is characterized in that, through the 1st iterative calibration, namely can determine that the highest-order bit of trim_para is 1 or is 0, through the 2nd iterative calibration, namely can determine that the second highest bit of trim_para is 1 or is 0, at most through 16 iterative calibration, namely can determine that last calibration parameter value.
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106374923A (en) * | 2016-08-18 | 2017-02-01 | 芯海科技（深圳）股份有限公司 | High-precision ADC reference voltage calibration system and calibration method |
| WO2019137001A1 (en) * | 2018-01-14 | 2019-07-18 | Shenzhen GOODIX Technology Co., Ltd. | Data converters systematic error calibration using on chip generated precise reference signal |
| CN110208687A (en) * | 2019-05-27 | 2019-09-06 | 宁波芯路通讯科技有限公司 | A kind of debugging system and method for analog circuit parameters calibration |
| CN110231510A (en) * | 2018-03-05 | 2019-09-13 | 无锡华润矽科微电子有限公司 | Improve the calibration system and method for chip interior reference voltage value precision |
| CN111277266A (en) * | 2020-02-20 | 2020-06-12 | 北京华益精点生物技术有限公司 | Correction method and device for signal acquisition value based on glucometer |
| CN111766435A (en) * | 2019-04-02 | 2020-10-13 | 全球能源互联网研究院有限公司 | Active calibration high-voltage measuring device and method |
| CN112578843A (en) * | 2019-09-29 | 2021-03-30 | 圣邦微电子（北京）股份有限公司 | Voltage trimming method and system based on integrated circuit |
| CN113701714A (en) * | 2021-09-23 | 2021-11-26 | 深圳市微特精密科技股份有限公司 | Method and device for identifying flattening calibration of DUT (device under test) by infrared reflection sensor |
| CN114448435A (en) * | 2022-01-29 | 2022-05-06 | 中国科学院微电子研究所 | Comparator threshold error calibration method, device, equipment and medium |
| CN115542132A (en) * | 2022-11-28 | 2022-12-30 | 深圳市鹏芯数据技术有限公司 | SOC (system on chip) built-in test circuit, SOC and test method |
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| WO2019137001A1 (en) * | 2018-01-14 | 2019-07-18 | Shenzhen GOODIX Technology Co., Ltd. | Data converters systematic error calibration using on chip generated precise reference signal |
| CN110231510A (en) * | 2018-03-05 | 2019-09-13 | 无锡华润矽科微电子有限公司 | Improve the calibration system and method for chip interior reference voltage value precision |
| CN111766435A (en) * | 2019-04-02 | 2020-10-13 | 全球能源互联网研究院有限公司 | Active calibration high-voltage measuring device and method |
| CN110208687A (en) * | 2019-05-27 | 2019-09-06 | 宁波芯路通讯科技有限公司 | A kind of debugging system and method for analog circuit parameters calibration |
| CN112578843A (en) * | 2019-09-29 | 2021-03-30 | 圣邦微电子（北京）股份有限公司 | Voltage trimming method and system based on integrated circuit |
| CN111277266A (en) * | 2020-02-20 | 2020-06-12 | 北京华益精点生物技术有限公司 | Correction method and device for signal acquisition value based on glucometer |
| CN111277266B (en) * | 2020-02-20 | 2022-02-01 | 北京华益精点生物技术有限公司 | Correction method and device for signal acquisition value based on glucometer |
| CN113701714A (en) * | 2021-09-23 | 2021-11-26 | 深圳市微特精密科技股份有限公司 | Method and device for identifying flattening calibration of DUT (device under test) by infrared reflection sensor |
| CN113701714B (en) * | 2021-09-23 | 2024-06-07 | 深圳市微特精密科技股份有限公司 | Method and device for identifying DUT (device under test) leveling calibration by infrared reflection sensor |
| CN114448435A (en) * | 2022-01-29 | 2022-05-06 | 中国科学院微电子研究所 | Comparator threshold error calibration method, device, equipment and medium |
| CN115542132A (en) * | 2022-11-28 | 2022-12-30 | 深圳市鹏芯数据技术有限公司 | SOC (system on chip) built-in test circuit, SOC and test method |
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Application publication date: 20160727 |