CN106324479B - chip calibration method, circuit and chip - Google Patents
chip calibration method, circuit and chip Download PDFInfo
- Publication number
- CN106324479B CN106324479B CN201610655888.1A CN201610655888A CN106324479B CN 106324479 B CN106324479 B CN 106324479B CN 201610655888 A CN201610655888 A CN 201610655888A CN 106324479 B CN106324479 B CN 106324479B
- Authority
- CN
- China
- Prior art keywords
- chip
- calibrated
- signal
- difference value
- digital signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
A chip calibration method, circuit and chip, the method includes receiving a reference analog signal, converting the reference analog signal into a class digital signal by an analog-to-digital converter, receiving a signal to be calibrated, converting the signal to be calibrated into a second class digital signal by the analog-to-digital converter, the signal to be calibrated coming from a signal generator of the chip to be calibrated, calculating the difference between the class digital signal and the second class digital signal, and completing calibration according to the difference between the class digital signal and the second class digital signal and a preset difference range, wherein the reference voltage of the analog-to-digital converter is provided by a voltage source outside the chip to be calibrated.
Description
Technical Field
The invention relates to the field of integrated circuit chip design, in particular to a chip calibration method, circuit and chip.
Background
In modern chip production, due to design, process, packaging and other reasons, a small amount of defective products are inevitably generated during mass production of chips, and in order to control the packaging test cost and ensure the quality of the produced chips, the chips are usually required to be tested, such as a middle test (on-wafer test) and a finished test (finished product test). The chip test comprises the calibration of the chip, and whether the chip is good or not can be judged according to the calibration result.
However, in the conventional chip calibration method, the reference voltage of the analog-to-digital converter is usually provided by the chip to be calibrated, the output voltage of the chip to be tested needs to be repeatedly measured, and the next steps of measurement are performed after the output of the chip to be tested is stable.
Disclosure of Invention
The invention aims to improve the calibration efficiency of the chip and reduce the calibration cost.
In order to solve the above technical problem, an embodiment of the present invention provides chip calibration methods, including receiving a reference analog signal, converting the reference analog signal into a -class digital signal by using an analog-to-digital converter, receiving a signal to be calibrated, converting the signal to be calibrated into a second-class digital signal by using the analog-to-digital converter, where the signal to be calibrated is from a signal generator of a chip to be calibrated, calculating a difference between the -class digital signal and the second-class digital signal, and completing calibration according to the difference between the -class digital signal and the second-class digital signal and a preset difference range, where a reference voltage of the analog-to-digital converter is provided by a voltage source outside the chip to be calibrated.
Optionally, the completing the calibration according to the difference between the -th class digital signal and the second class digital signal and a preset difference range includes, if the difference between the -th class digital signal and the second class digital signal is outside the preset difference range, performing a step of updating a configuration of a signal generator of the chip to be calibrated so that the chip to be calibrated updates the signal to be calibrated, and re-comparing the difference between the -th class digital signal and the second class digital signal with the preset difference range until the difference falls within the preset difference range, or confirming that the difference cannot fall within the preset difference range.
Optionally, the chip calibration method further includes storing a configuration of a signal generator of the chip to be calibrated.
Optionally, the configuration of the signal generator for updating the chip to be calibrated is performed according to any methods, namely a bisection method and a successive comparison method.
Optionally, the completing the calibration according to the difference between the -th class digital signal and the second class digital signal and a preset difference range further includes generating a calibration result, where the calibration result is used to indicate that the difference falls within the preset difference range, or confirm that the difference cannot fall within the preset difference range.
The embodiment of the invention also provides chip calibration circuits, which comprise an analog-to-digital converter and a calibrator, wherein the analog-to-digital converter is suitable for receiving a reference analog signal, converting the reference analog signal into a -class digital signal, receiving a signal to be calibrated, and converting the signal to be calibrated into a second-class digital signal, the signal to be calibrated comes from a signal generator of a chip to be calibrated, the calibrator is suitable for calculating the difference value between the -class digital signal and the second-class digital signal, and completing calibration according to the difference value between the -class digital signal and the second-class digital signal and a preset difference value range, and the reference voltage of the analog-to-digital converter is provided by a voltage source outside the chip to be calibrated.
Optionally, the calibrator includes a determining unit adapted to determine whether a difference between the -th class digital signal and the second class digital signal is within a preset difference range, and a configuration updating unit adapted to update a configuration of a signal generator of the chip to be calibrated, so that the chip to be calibrated updates the signal to be calibrated, and trigger the determining unit to re-compare the difference between the -th class digital signal and the second class digital signal with the preset difference range until the difference falls within the preset difference range, or confirm that the difference cannot fall within the preset difference range.
Optionally, the configuration of the signal generator of the chip to be calibrated is stored in the non-volatile memory.
Optionally, the configuration updating unit is adapted to update the configuration of the signal generator of the chip to be calibrated according to any methods, namely a bisection method and a successive comparison method.
Optionally, the calibrator further includes a calibration result generating unit adapted to generate a calibration result, where the calibration result is used to indicate that the difference value falls within the preset difference value range, or confirm that the difference value cannot fall within the preset difference value range.
The embodiment of the invention also provides chips comprising the chip calibration circuit.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
the analog-to-digital converter converts a reference analog signal into a type digital signal, converts a signal to be calibrated into a second type digital signal, and calculates the difference between the type digital signal and the second type digital signal, thereby removing errors introduced by the analog-to-digital converter.
Drawings
FIG. 1 is a flow chart of a chip calibration method according to an embodiment of the invention;
FIG. 2 is a flow chart of another chip calibration method in an embodiment of the invention;
fig. 3 is a schematic structural diagram of an chip calibration circuit according to an embodiment of the present invention.
Detailed Description
As described above, the efficiency of the conventional chip calibration needs to be improved, and the calibration cost needs to be reduced.
, the reference voltage of the analog-to-digital converter is provided by the chip to be calibrated when the chip is calibrated by the prior chip calibration method, therefore, the output voltage of the chip to be tested needs to be repeatedly measured, and after the output of the chip to be tested is stable, the next steps of measurement are carried out, which causes the error of the analog-to-digital converter and the reference voltage thereof.
In addition , in the prior art, in order to avoid errors of the analog-to-digital converter and the reference voltage introduced during the calibration of the chip, the analog-to-digital converter and the reference voltage need to be calibrated first, and after the analog-to-digital converter is calibrated, the signal to be calibrated is read and calibrated for the signal to be calibrated.
In the embodiment of the invention, the reference analog signal is converted into the -th type digital signal by the analog-to-digital converter , the signal to be calibrated is converted into the second type digital signal, and the difference value between the -th type digital signal and the second type digital signal is calculated, so that errors introduced by the analog-to-digital converter can be removed, the analog-to-digital converter does not need to be calibrated, the cost of chip calibration can be reduced, and the efficiency of chip calibration is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 1 is a flowchart of an chip calibration method according to an embodiment of the present invention.
In step S11, a reference analog signal is received and converted into a digital signal of class using an analog-to-digital converter.
In a specific implementation, the value of the reference analog signal may be a target value of a signal that needs to be generated by a signal generator of the chip to be calibrated, and the target value may be a target value of a voltage signal generated by the signal generator or a target value of a current signal generated by the signal generator. The target value may be determined according to the calibration requirements of the chip to be calibrated. The reference analog signal may be generated by a source of higher precision, such as a tester.
The reference voltage of the analog-to-digital converter is provided by a voltage source outside the chip to be calibrated, for example, the voltage source can be provided by a testing machine, the voltage source is provided by the testing machine directly to the chip to be calibrated, so that the reference voltage does not need to be repeatedly calibrated, and step can improve the efficiency of chip calibration.
In step S12, a signal to be calibrated is received, and the signal to be calibrated is converted into a second type of digital signal by the analog-to-digital converter, where the signal to be calibrated comes from a signal generator of the chip to be calibrated.
The signal to be calibrated may be a signal generated by the signal generator according to the configuration, may be a signal to be calibrated generated in a preset gear, and may also be a signal to be calibrated generated after the configuration of the signal generator is updated.
In a specific implementation, the order of receiving the reference analog signal and receiving the signal to be calibrated is not limited, and may be set according to actual needs, so that the reference analog signal or the signal to be calibrated may be received and converted by the analog-to-digital converter in a time-division multiplexing manner.
In step S13, a difference between the type digital signal and the second type digital signal is calculated, and calibration is performed according to the difference between the type digital signal and the second type digital signal and a preset difference range.
For example, the specification of the chip to be calibrated requires a signal error of less than 10mv, the adc has a 10-Bit accuracy and a 5v reference voltage, and the limit value of can be set to 1 Least Significant Bit (LSB), i.e., about 5 mv.
In a specific implementation, the difference between the th class digital signal and the second class digital signal may reflect a deviation between a value of a signal generated by a signal generator in a chip to be calibrated and a target value, if the deviation is within a preset difference range, it indicates that the chip to be calibrated meets a calibration requirement, calibration may be completed, and a calibration result may be generated, and if the deviation is not within the preset difference range, calibration may be continued.
In an embodiment of the invention , if a difference between the type digital signal and the second type digital signal is outside a preset difference range, the following steps may be performed:
updating the configuration of the signal generator of the chip to be calibrated, so that the chip to be calibrated updates the signal to be calibrated, and re-compares the difference value between the th class digital signal and the second class digital signal with the preset difference value range until the difference value falls into the preset difference value range, or confirms that the difference value cannot fall into the preset difference value range.
Referring now to fig. 2, a method for calibrating a chip in an embodiment of the present invention is described.
In step S21, a reference analog signal is received and converted into a digital signal of class using an analog-to-digital converter.
In step S22, a signal to be calibrated is received, and the signal to be calibrated is converted into a second type of digital signal by the analog-to-digital converter, where the signal to be calibrated comes from a signal generator of the chip to be calibrated.
Specific implementation of steps S21 and S22 can refer to steps S11 and S12 in fig. 1, and will not be described herein.
In step S23, it is determined whether the difference between the -type digital signal and the second-type digital signal is within a predetermined difference range, if the difference between the -type digital signal and the second-type digital signal is not within the predetermined difference range, step S24 may be performed, otherwise, step S26 may be performed.
In step S24, it is confirmed that the difference value cannot fall within a preset difference value range. If yes, go to step S26, otherwise go to step S25.
In step S25, the configuration of the signal generator of the chip to be calibrated is updated.
For example, all the gears of the signal generator can be simply traversed, or the signal generator can be configured according to a preset algorithm to more quickly approach the gear corresponding to the target value, and the algorithm can also combine the type digital signal and the difference value of the second type digital signal to configure the signal generator.
When the gear and the output of the signal generator in the chip to be calibrated meet the monotonicity relationship, the configuration of the signal generator can be updated according to the dichotomy. For example, the signal to be calibrated may be an analog signal corresponding to an 8-bit digital signal, i.e. the signal generator may have 256 steps.
In non-limiting examples, the value of the reference analog signal, i.e. the target value of the signal that the signal generator needs to generate, is the voltage value of the voltage signal, and the signal generator in the chip to be calibrated can generate the voltage signal meeting the requirement of the target value when the shift position is 200. at this time, when the signal generator is calibrated according to the dichotomy, the input configuration values can be changed gradually according to the sequence of 128, 192, 224, 208, and 200, so as to update the signal to be calibrated gradually, so that the value of the signal to be calibrated gradually approaches the target value.
In another non-limiting examples, the signal generator of the chip to be calibrated has 200 configurable shift positions, and in order to select a suitable shift position to generate the second type of digital signal with the difference value from the type of digital signal within the preset difference range, the shift position of the signal generator can also be continuously adjusted, and the shift position of the signal generator is updated by using a successive comparison method.
For example, when the gear 50 is the gear , the difference value of the digital signal of the type and the corresponding digital signal of the type II is positive, and when the gear 51 is the gear , the difference value of the digital signal of the type and the corresponding digital signal of the type II is negative, the gear 50 and the gear 51 can be selected according to the difference value and the preset difference value range to update the configuration of the signal generator of the chip to be calibrated.
It is understood that the configuration method of the signal generator of the chip to be calibrated is not limited to the specific examples described above, and those skilled in the art can select an appropriate method to update the configuration of the signal generator of the chip to be calibrated as required.
After updating the configuration of the signal generator, step S22 may be executed again to re-compare the difference between the th class digital signal and the second class digital signal with the preset difference range.
In a specific implementation, it is determined that the difference (i.e., the difference between the -th-class digital signal and the second-class digital signal) cannot fall within a preset difference range, that the difference still cannot fall within the preset difference range after all gears of the signal generator have been traversed, or that the configuration of the signal generator has been completed according to a preset algorithm, and that the difference still cannot fall within the preset range.
In step S26, a calibration result is generated. The calibration result may be used to indicate that the difference value falls within the preset difference value range, or confirm that the difference value cannot fall within the preset difference value range.
The calibration result can indicate whether the chip to be calibrated is good or not, and when the difference value falls into the preset difference value range, the chip to be calibrated is good; and when the difference value cannot fall into the preset difference value range, the chip to be calibrated is a defective product. In implementations, the calibration result may be a digital signal.
The chip calibration method in the embodiment of the present invention may further include: storing the configuration of the signal generator of the chip to be calibrated, for example, in a non-volatile memory, which may be located in the chip to be calibrated; storing the configuration of the signal generator with the difference value falling into the preset difference value range, so that the signal generator can work according to the configuration when the signal generator needs to output the calibrated signal value in a working scene; the configuration of the signal generator and the corresponding difference result may also be stored when the difference does not fall within a preset difference range, for data analysis.
In the embodiment of the invention, the reference analog signal is converted into the -th class digital signal by the analog-to-digital converter , the signal to be calibrated is converted into the second class digital signal, and the difference between the -th class digital signal and the second class digital signal is calculated, so that the error introduced by the analog-to-digital converter can be removed, the reference voltage of the analog-to-digital converter does not need to be calibrated, the cost of chip calibration can be reduced, and the efficiency of chip calibration can be improved.
The embodiment of the invention also provides an chip calibration circuit, and a structural schematic diagram of the circuit can be seen in fig. 3.
The chip calibration circuit 30 may include an analog-to-digital converter 31 and a calibrator 32, wherein:
the analog-to-digital converter 31 is adapted to receive a reference analog signal and convert the reference analog signal into a digital signal of class , and is adapted to receive a signal to be calibrated and convert the signal to be calibrated into a digital signal of a second class.
Wherein, the reference voltage of the analog-to-digital converter is provided by a voltage source outside the chip to be calibrated. The reference analog signal may be derived from the tester 35, and the signal to be calibrated may be derived from the signal generator 34 of the chip to be calibrated. Tester 35 may also provide power to the chips to be tested.
The reference analog signal may be directly provided by the tester 35, or may be obtained by providing a digital signal from the tester 35 and performing digital-to-analog conversion.
The calibrator 32 is adapted to calculate a difference between the th class digital signal and the second class digital signal, and perform calibration according to the difference between the th class digital signal and the second class digital signal and a preset difference range.
In a specific implementation, calibrator 32 may include:
the judging unit 321 is adapted to judge whether a difference value between the th class digital signal and the second class digital signal is within a preset difference value range.
The configuration updating unit 322 is adapted to update the configuration of the signal generator 34 of the chip to be calibrated, so that the chip to be calibrated updates the signal to be calibrated, and trigger the determining unit 321 to re-compare the difference between the th class digital signal and the second class digital signal with the preset difference range until the difference falls within the preset difference range, or confirm that the difference cannot fall within the preset difference range.
In the embodiment of the invention, the configuration updating unit 322 can update the configuration of the signal generator 34 of the chip to be calibrated according to any methods, i.e., dichotomy and successive comparison.
In a specific implementation, the configuration of the signal generator of the chip to be calibrated may be stored in the non-volatile memory 33.
In a specific implementation, the calibrator further includes a calibration result generating unit (not shown) adapted to generate a calibration result, where the calibration result is used to indicate that the difference value falls within the preset difference value range, or confirm that the difference value cannot fall within the preset difference value range.
The tester 35 can obtain the calibration result through the calibration result generating unit to determine whether the chip to be calibrated is good, and then complete the testing process. In a specific implementation, the tester 35 may also obtain configuration information of a signal generator in the chip to be calibrated.
In the prior art, a tester is usually required to directly measure high-precision analog voltage signals, and the test precision of a chip is deteriorated due to various interferences and noises in a test environment; the embodiment of the invention does not need a tester to directly measure the high-precision analog voltage signal, can effectively reduce the influence of various interferences and noises on the test precision, and improves the test precision. In addition, since the calibration result may be a digital signal, interference is small during transmission, so that the testing machine 35 can complete the testing process more accurately.
The embodiment of the invention also provides chips which can comprise the chip calibration circuit, and the chip comprises the chip calibration circuit, so that a signal to be calibrated does not need to pass through a transmission path outside the chip, thereby avoiding interference in a test environment, and further steps can improve the precision of chip calibration.
The simulation peripheral calibration of the existing chip needs to rely on a tester to provide a high-precision signal generating unit and a high-precision measuring unit, and a high-performance mixed signal tester needs to be configured to achieve the purpose of measuring and calibrating the simulation peripheral of the chip. Meanwhile, because the processing of the signal needs to rely on the tester and the chip to be tested to perform data communication and flow processing through a machine testing mode, the execution efficiency is low, the requirement on the stability of the tester is high, the calibration process time is long, and the testing cost is high.
The chip in the embodiment of the invention comprises the chip calibration circuit, so that the self calibration of the chip can be completed, a high-precision signal generation unit and a high-precision measurement unit do not need to be configured on a testing machine, and the testing requirement on the testing machine is reduced. Because the test calibration algorithm is completed by the chip, the calibration process automatically runs in the chip, the test efficiency and stability are improved, and the test cost is reduced.
In addition, because the dependency on the configuration of the testing machine is reduced, the development work of the test can be quickly and seamlessly transplanted in a plurality of testing platforms, and great economic benefit can be generated for mass production test.
The specific implementation and beneficial effects of the chip calibration circuit, the chip and the tester in the embodiment of the invention can also refer to the description of the chip calibration method, and are not described herein again.
Those skilled in the art will appreciate that all or part of the steps in the methods of the above embodiments may be implemented by associated hardware instructed by a program, which may be stored in a computer readable storage medium, which may include ROM, RAM, magnetic or optical disk, etc.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (11)
1, chip calibration method, comprising:
receiving a reference analog signal, and converting the reference analog signal into an -class digital signal by using an analog-to-digital converter, wherein the analog-to-digital converter is integrated in a chip, and the value of the reference analog signal is the target value of a signal which needs to be generated by a signal generator of the chip to be calibrated;
receiving a signal to be calibrated, and converting the signal to be calibrated into a second type of digital signal by using the analog-to-digital converter, wherein the signal to be calibrated comes from a signal generator of a chip to be calibrated;
calculating the difference value between the -th class digital signal and the second class digital signal, completing calibration according to the difference value between the -th class digital signal and the second class digital signal and a preset difference value range, and generating a calibration result indicating whether the chip to be calibrated is good;
wherein, the reference voltage of the analog-to-digital converter is provided by a voltage source outside the chip to be calibrated.
2. The method of claim 1, wherein the calibrating according to the difference between the -th class digital signal and the second class digital signal and a predetermined difference range comprises performing the following steps if the difference between the -th class digital signal and the second class digital signal is outside the predetermined difference range:
updating the configuration of the signal generator of the chip to be calibrated, so that the chip to be calibrated updates the signal to be calibrated, and re-compares the difference value between the th class digital signal and the second class digital signal with the preset difference value range until the difference value falls into the preset difference value range, or confirms that the difference value cannot fall into the preset difference value range.
3. The chip calibration method according to claim 2, further comprising storing a configuration of a signal generator of the chip to be calibrated.
4. The method for calibrating a chip according to claim 2, wherein the updating of the configuration of the signal generator of the chip to be calibrated is performed according to any methods selected from the group consisting of dichotomy and successive comparison.
5. The method for calibrating the chip according to claim 2, wherein when the difference value falls within the preset difference value range, the calibration result indicates that the chip to be calibrated is good; and when the difference value cannot fall into the preset difference value range, the calibration result indicates that the chip to be calibrated is a defective product.
The chip calibration circuit of , comprising:
the analog-to-digital converter is integrated in a chip, and the value of the reference analog signal is a target value of a signal required to be generated by a signal generator of the chip to be calibrated;
the calibrator is suitable for calculating the difference value between the th class digital signal and the second class digital signal, completing calibration according to the difference value between the th class digital signal and the second class digital signal and a preset difference value range, and generating a calibration result indicating whether the chip to be calibrated is good;
wherein, the reference voltage of the analog-to-digital converter is provided by a voltage source outside the chip to be calibrated.
7. The chip calibration circuit of claim 6, wherein the calibrator comprises:
the judging unit is suitable for judging whether the difference value of the th class digital signal and the second class digital signal is within a preset difference value range or not;
and the configuration updating unit is suitable for updating the configuration of the signal generator of the chip to be calibrated so that the chip to be calibrated updates the signal to be calibrated, and triggers the judging unit to re-compare the difference value between the th class digital signal and the second class digital signal with the preset difference value range until the difference value falls into the preset difference value range, or confirms that the difference value cannot fall into the preset difference value range.
8. The chip calibration circuit according to claim 7, wherein the configuration of the signal generator of the chip to be calibrated is stored in a non-volatile memory.
9. The chip calibration circuit of claim 7, wherein the configuration updating unit is adapted to update the configuration of the signal generator of the chip to be calibrated according to any methods selected from the group consisting of bisection method and successive comparison method.
10. The chip calibration circuit according to claim 7, wherein the calibrator further comprises a calibration result generating unit adapted to generate a calibration result; when the difference value falls into the preset difference value range, the calibration result indicates that the chip to be calibrated is good; and when the difference value cannot fall into the preset difference value range, the calibration result indicates that the chip to be calibrated is a defective product.
11, chips, characterized in that it comprises a chip calibration circuit according to any of claims 6-10 and .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610655888.1A CN106324479B (en) | 2016-08-11 | 2016-08-11 | chip calibration method, circuit and chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610655888.1A CN106324479B (en) | 2016-08-11 | 2016-08-11 | chip calibration method, circuit and chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106324479A CN106324479A (en) | 2017-01-11 |
| CN106324479B true CN106324479B (en) | 2020-01-31 |
Family
ID=57740206
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610655888.1A Active CN106324479B (en) | 2016-08-11 | 2016-08-11 | chip calibration method, circuit and chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106324479B (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107835019B (en) * | 2017-08-31 | 2021-06-08 | 北京时代民芯科技有限公司 | Factory calibration system and calibration method of high-precision digital-to-analog converter |
| CN107656235A (en) * | 2017-10-31 | 2018-02-02 | 国网冀北电力有限公司电力科学研究院 | A kind of measurement apparatus and method of computation chip reference voltage |
| CN109375127B (en) * | 2018-09-30 | 2020-11-06 | 中国船舶重工集团公司第七0九研究所 | Automatic calibration device and method for integrated circuit test system based on analog-to-digital converter |
| CN109752593A (en) * | 2019-01-18 | 2019-05-14 | 钜泉光电科技(上海)股份有限公司 | Detection system and electric energy computation chip and its equipment |
| CN110286707B (en) * | 2019-05-28 | 2020-10-27 | 成都锐成芯微科技股份有限公司 | Automatic calibration method and calibration circuit for chip core voltage |
| CN112485499A (en) * | 2020-12-29 | 2021-03-12 | 深圳市芯天下技术有限公司 | Test method and device for automatic calibration of reference current, storage medium and terminal |
| CN112578270A (en) * | 2020-12-29 | 2021-03-30 | 深圳市芯天下技术有限公司 | Test method and device for automatic calibration of reference voltage, storage medium and terminal |
| CN116068478B (en) * | 2023-03-07 | 2023-08-15 | 紫光同芯微电子有限公司 | Chip downloading calibration system and using method |
| CN116846393B (en) * | 2023-09-01 | 2023-11-28 | 北京数字光芯集成电路设计有限公司 | Digital-to-analog converter calibration method and device and display equipment |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1866039A (en) * | 2005-05-19 | 2006-11-22 | 台朔光电股份有限公司 | Apparatus and method for testing drive integrated circuit of display panel |
| CN2860345Y (en) * | 2005-08-02 | 2007-01-24 | 深圳迈瑞生物医疗电子股份有限公司 | Gain calibration device and invasive blood pressure measuring device comprising same |
| TWI365366B (en) * | 2008-04-03 | 2012-06-01 | Sunplus Mmedia Inc | Usb chip with self-calibration circuit and calibration method thereof |
| CN101556321A (en) * | 2009-05-27 | 2009-10-14 | 深圳市科陆电子科技股份有限公司 | Auto-calibration method for split-core type current mutual inductor of three-phase electric energy meter on-site calibrator |
| CN103116124B (en) * | 2011-11-17 | 2016-05-18 | 国民技术股份有限公司 | Can self calibration chip, crystal oscillator calibration test system and the calibration steps of inner crystal oscillator |
| TWI517552B (en) * | 2013-01-31 | 2016-01-11 | 新唐科技股份有限公司 | Circuit and method for calibrating oscillator and corresponding integrated circuit |
-
2016
- 2016-08-11 CN CN201610655888.1A patent/CN106324479B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN106324479A (en) | 2017-01-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106324479B (en) | chip calibration method, circuit and chip | |
| CN107181489B (en) | Analog-to-digital conversion calibration method and device | |
| CN106374923B (en) | High-precision ADC reference voltage calibration system and calibration method | |
| US6456102B1 (en) | External test ancillary device to be used for testing semiconductor device, and method of testing semiconductor device using the device | |
| CN110568397B (en) | Electric energy meter correction method and system based on MCU software | |
| CN110061742B (en) | Analog-to-digital converter calibration system | |
| KR20180137945A (en) | Processor-based measurement method for testing device under test and measurement apparatus using the same | |
| CN106053957A (en) | Test fixture line loss test method and test fixture line loss test system | |
| CN105811982A (en) | ADC chip reference voltage testing and calibration method | |
| US20190334538A1 (en) | Error compensation correction device for pipeline analog-to-digital converter | |
| US20020107654A1 (en) | Apparatus for testing semiconductor integrated circuit | |
| CN100479328C (en) | System and method for digital compensation of digital to analog and analog to digital converters | |
| CN114002588B (en) | High-precision semiconductor chip trimming test method | |
| KR101018702B1 (en) | Partial Discharge Corrector With Self Correction And Tracing Management | |
| TW201713043A (en) | Chip having self-calibration mechanism and calibration method thereof | |
| CN115856745A (en) | Test device, calibration method, calibration device, chip test method, and storage medium | |
| CN113702896B (en) | System and method for measuring direct-current electric energy standard meter error based on voltage reference | |
| JP2011125005A (en) | Signal generator and test device | |
| CN112152623B (en) | System and method for testing analog-to-digital converter | |
| JP6486237B2 (en) | AD converter | |
| CN117665686B (en) | ATE (automatic test equipment) equipment-based dynamic load calibration method and system, equipment and medium | |
| CN113364461A (en) | Analog-to-digital conversion calibration method and system for chip to be tested | |
| CN113030821A (en) | Electric quantity calibration method and device | |
| CN116505947B (en) | Analog-to-digital converter calibration method, device, storage medium and chip | |
| JP2001345699A (en) | Testing circuit of analog-to-digital converter and its testing method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |