CN112578270A - Test method and device for automatic calibration of reference voltage, storage medium and terminal - Google Patents
Test method and device for automatic calibration of reference voltage, storage medium and terminal Download PDFInfo
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- CN112578270A CN112578270A CN202011594557.4A CN202011594557A CN112578270A CN 112578270 A CN112578270 A CN 112578270A CN 202011594557 A CN202011594557 A CN 202011594557A CN 112578270 A CN112578270 A CN 112578270A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/282—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere
- G01R31/2831—Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
- G01R31/2834—Automated test systems [ATE]; using microprocessors or computers
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Abstract
The invention discloses a test method, a device, a storage medium and a terminal for automatically calibrating a reference voltage, wherein a target reference voltage is sent, the reference voltage of a chip is compared with the target reference voltage through a comparator, and if the reference voltage is greater than the target reference voltage, the reference voltage is reduced until the difference value of the reference voltage and the target reference voltage falls into an error range; if the reference voltage is smaller than the target reference voltage, increasing the reference voltage until the difference value of the reference voltage and the target reference voltage falls into an error range; the traditional method for directly measuring the reference voltage of the chip is changed into the method for comparing the reference voltage with the set target reference voltage, the reference voltage is calibrated through the difference value of the reference voltage and the target reference voltage, the target reference voltage is generated through a low-order testing machine, a high-order testing machine is not needed in the whole process, and the testing cost is greatly reduced; and the whole process only involves the magnitude comparison of voltage values, and the test procedure is simple and has strong operability.
Description
Technical Field
The invention relates to the technical field of chip testing, in particular to a testing method and device for automatic calibration of reference voltage, a storage medium and a terminal.
Background
In a wafer testing link, the reference voltage of the chip needs to be measured, and then whether the reference voltage calibration of the chip passes or not is judged according to the measured voltage. In the prior art, a higher-order tester (i.e., a tester equipped with a measuring unit for measuring high-precision voltages) is generally used to measure the reference voltage of the chip, and then whether the calibration of the reference voltage of the chip passes or not is determined according to the measured voltage.
Therefore, the prior art still needs to be improved and developed.
Disclosure of Invention
The invention aims to provide a test method, a test device, a storage medium and a terminal for automatic calibration of reference voltage, and aims to solve the problems of high test cost and complex test procedure of a chip caused by the fact that a high-order test machine is adopted to measure the reference voltage of the chip in the prior art.
The technical scheme of the invention is as follows: a test method for automatic calibration of reference voltage specifically comprises the following steps:
starting an automatic calibration test of the chip reference voltage;
receiving a target reference voltage;
judging whether the difference value between the reference voltage of the chip and the target reference voltage is within an error range,
if so, the calibration of the chip reference voltage is passed, and a calibration result is output;
otherwise, changing the reference voltage setting parameter in the chip to change the reference voltage of the chip, and judging whether the difference value between the reference voltage of the chip and the target reference voltage is in the error range again.
The test method for the automatic calibration of the reference voltage comprises the steps of starting the automatic calibration test of the reference voltage of the chip, and enabling the automatic calibration test of the reference voltage of the chip to be started through receiving the test.
The test method for the automatic calibration of the reference voltage comprises the step of generating the target reference voltage by a low-order test machine.
The method for testing the automatic calibration of the reference voltage, wherein if not, the reference voltage setting parameters in the chip are changed to change the reference voltage of the chip, and the difference value between the reference voltage of the chip and the target reference voltage is judged again to be in the error range, specifically comprising the following steps:
s 51: judging whether the difference value between the reference voltage of the chip and the target reference voltage is a positive value or a negative value, if the difference value is the positive value, jumping to s52, and if the difference value is the negative value, jumping to s 53;
s 52: reducing the reference voltage of the chip by a set voltage value, and then jumping to judge whether the difference value between the reference voltage of the chip and the target reference voltage is within an error range;
s 53: and increasing the reference voltage of the chip by a set voltage value, and then jumping to judge whether the difference value between the reference voltage of the chip and the target reference voltage is within an error range.
A test apparatus for automatic reference voltage calibration, comprising:
the starting module starts the chip reference voltage automatic calibration test;
a voltage receiving module that receives a target reference voltage;
the judgment module is used for judging whether the difference value between the reference voltage of the chip and the target reference voltage is within an error range;
the calibration result output module outputs a calibration result after the calibration of the chip reference voltage is passed;
and the parameter setting module is used for changing the reference voltage setting parameters in the chip so as to change the reference voltage of the chip.
The test device for the automatic calibration of the reference voltage is characterized in that the parameter setting module is realized by adopting a reference voltage control module Verf block in a chip.
The test device for the automatic calibration of the reference voltage is characterized in that an initial value of a reference voltage setting parameter in the reference voltage control module Verf block is a default reference voltage setting parameter in a chip.
The test device for automatically calibrating the reference voltage is characterized in that the judgment module is realized by adopting a voltage comparator.
A storage medium having stored therein a computer program which, when run on a computer, causes the computer to perform any of the methods described above.
A terminal comprising a processor and a memory, the memory having stored therein a computer program, the processor being configured to execute the method of any of the preceding 1 to 4 by calling the computer program stored in the memory.
The invention has the beneficial effects that: the invention provides a test method, a device, a storage medium and a terminal for automatically calibrating a reference voltage, wherein a target reference voltage is sent, the reference voltage of a chip is compared with the target reference voltage through a comparator, and if the reference voltage of the chip is greater than the target reference voltage, the reference voltage of the chip is reduced until the difference value of the reference voltage of the chip and the target reference voltage falls into an error range; if the reference voltage of the chip is smaller than the target reference voltage, increasing the reference voltage of the chip until the difference value between the reference voltage of the chip and the target reference voltage falls into an error range; the traditional method of directly measuring the reference voltage of the chip is changed into the method of comparing the reference voltage of the chip with the set target reference voltage, the reference voltage of the chip is calibrated through the difference value of the reference voltage and the target reference voltage, the target reference voltage is generated through a low-order testing machine, a high-order testing machine is not needed in the whole process, and the testing cost is greatly reduced; and the whole process only involves the magnitude comparison of voltage values, and the test procedure is simple and has strong operability.
Drawings
FIG. 1 is a flow chart of the steps of the test method for automatic calibration of reference voltage in the present invention.
FIG. 2 is a schematic diagram of a test apparatus for automatic calibration of reference voltage in the present invention.
Fig. 3 is a schematic diagram of a terminal in the present invention.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.
As shown in fig. 1, a test method for automatic calibration of reference voltage specifically includes the following steps:
s1: starting an automatic calibration test of the chip reference voltage;
s2: receiving a target reference voltage;
s3: judging whether the difference value of the reference voltage of the chip and the target reference voltage is within an error range, if so, skipping to S4, otherwise, skipping to S5;
s4: the calibration of the chip reference voltage is passed, and a calibration result is output;
s5: the on-chip reference voltage setting parameter is changed to change the chip reference voltage, and the flow goes to S3.
In some embodiments, in S1, the chip reference voltage auto-calibration test is enabled by receiving the test enable.
In some embodiments, in S2, the target reference voltage is generated by a low-order tester that is not equipped with a measurement unit for measuring a high-precision voltage.
In some embodiments, the step S5 specifically includes the following steps:
s 51: judging whether the difference value between the reference voltage of the chip and the target reference voltage is a positive value or a negative value, if the difference value is the positive value, jumping to s52, and if the difference value is the negative value, jumping to s 53;
s 52: reducing the reference voltage of the chip by a set voltage value and then jumping to S3;
s 53: the reference voltage of the chip is increased by the set voltage value and then the process proceeds to S3.
As shown in fig. 2, a test apparatus for automatic calibration of reference voltage includes:
the starting module 101 starts the chip reference voltage automatic calibration test;
a voltage receiving module 102 that receives a target reference voltage;
the judging module 103 is used for judging whether the difference value between the reference voltage of the chip and the target reference voltage is within an error range;
a calibration result output module 104, which outputs a calibration result when the chip reference voltage calibration is passed;
the parameter setting module 105 changes an on-chip reference voltage setting parameter to change a chip reference voltage.
In some embodiments, the parameter setting module 105 is implemented by using a reference voltage control module Verf block in a chip.
In some embodiments, the initial value of the reference voltage setting parameter in the reference voltage control module Verf block is a default reference voltage setting parameter in the chip.
In some embodiments, the determining module 103 is implemented by a voltage comparator.
In some embodiments, when the determining module 103 employs a voltage comparator, the reference voltage calibration process of the parameter setting module 105 is as follows: when the first voltage comparator outputs a high level (namely the reference voltage of the chip is greater than the target reference voltage), reducing the calibration bit of the reference voltage, and repeatedly executing the voltage comparison for one time until the voltage comparator outputs a low level; if the voltage comparator outputs a low level for the first time (i.e. the reference voltage of the chip is less than the target reference voltage), the calibration bit of the reference voltage is increased, and the voltage comparison is performed again until the voltage comparator outputs a high level.
In the technical scheme, a target reference voltage is sent, the reference voltage of the chip is compared with the target reference voltage through a comparator, and if the reference voltage of the chip is greater than the target reference voltage, the reference voltage of the chip is reduced until the difference value of the reference voltage of the chip and the target reference voltage falls into an error range; if the reference voltage of the chip is smaller than the target reference voltage, increasing the reference voltage of the chip until the difference value between the reference voltage of the chip and the target reference voltage falls into an error range; the traditional method of directly measuring the reference voltage of the chip is changed into the method of comparing the reference voltage of the chip with the set target reference voltage, the reference voltage of the chip is calibrated through the difference value of the reference voltage and the target reference voltage, the target reference voltage is generated through a low-order testing machine, a high-order testing machine is not needed in the whole process, and the testing cost is greatly reduced; and the whole process only involves the magnitude comparison of voltage values, and the test procedure is simple and has strong operability.
Referring to fig. 3, an embodiment of the present invention further provides a terminal. As shown, the terminal 300 includes a processor 301 and a memory 302. The processor 301 is electrically connected to the memory 302. The processor 301 is a control center of the terminal 300, connects various parts of the entire terminal using various interfaces and lines, and performs various functions of the terminal and processes data by running or calling a computer program stored in the memory 302 and calling data stored in the memory 302, thereby performing overall monitoring of the terminal 300.
In this embodiment, the processor 301 in the terminal 300 loads instructions corresponding to one or more processes of the computer program into the memory 302 according to the following steps, and the processor 301 runs the computer program stored in the memory 302, so as to implement various functions: starting an automatic calibration test of the chip reference voltage; receiving a target reference voltage; judging whether the difference value between the reference voltage of the chip and the target reference voltage is within an error range, if so, passing the calibration of the reference voltage of the chip, and outputting a calibration result; otherwise, changing the reference voltage setting parameter in the chip to change the reference voltage of the chip, and judging whether the difference value between the reference voltage of the chip and the target reference voltage is in the error range again.
Memory 302 may be used to store computer programs and data. The memory 302 stores computer programs containing instructions executable in the processor. The computer program may constitute various functional modules. The processor 301 executes various functional applications and data processing by calling a computer program stored in the memory 302.
An embodiment of the present application provides a storage medium, and when being executed by a processor, the computer program performs a method in any optional implementation manner of the foregoing embodiment to implement the following functions: starting an automatic calibration test of the chip reference voltage; receiving a target reference voltage; judging whether the difference value between the reference voltage of the chip and the target reference voltage is within an error range, if so, passing the calibration of the reference voltage of the chip, and outputting a calibration result; otherwise, changing the reference voltage setting parameter in the chip to change the reference voltage of the chip, and judging whether the difference value between the reference voltage of the chip and the target reference voltage is in the error range again. The storage medium may be implemented by any type of volatile or nonvolatile storage device or combination thereof, such as a Static Random Access Memory (SRAM), an Electrically Erasable Programmable Read-Only Memory (EEPROM), an Erasable Programmable Read-Only Memory (EPROM), a Programmable Read-Only Memory (PROM), a Read-Only Memory (ROM), a magnetic Memory, a flash Memory, a magnetic disk, or an optical disk.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and there may be other divisions when actually implemented, and for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some communication interfaces, and may be in an electrical, mechanical or other form.
In addition, units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
Furthermore, the functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (10)
1. A test method for automatic calibration of reference voltage is characterized by comprising the following steps:
starting an automatic calibration test of the chip reference voltage;
receiving a target reference voltage;
judging whether the difference value between the reference voltage of the chip and the target reference voltage is within an error range,
if so, the calibration of the chip reference voltage is passed, and a calibration result is output;
otherwise, changing the reference voltage setting parameter in the chip to change the reference voltage of the chip, and judging whether the difference value between the reference voltage of the chip and the target reference voltage is in the error range again.
2. The method of claim 1, wherein the initiating of the chip reference voltage auto-calibration test initiates the chip reference voltage auto-calibration test by receiving a test enable.
3. The method of claim 1, wherein the target reference voltage is generated by a low order tester.
4. The method as claimed in claim 1, wherein if not, the on-chip reference voltage setting parameter is changed to change the chip reference voltage, and the step of determining whether the difference between the reference voltage of the chip and the target reference voltage is within the error range is executed again, specifically comprising the following steps:
s 51: judging whether the difference value between the reference voltage of the chip and the target reference voltage is a positive value or a negative value, if the difference value is the positive value, jumping to s52, and if the difference value is the negative value, jumping to s 53;
s 52: reducing the reference voltage of the chip by a set voltage value, and then jumping to judge whether the difference value between the reference voltage of the chip and the target reference voltage is within an error range;
s 53: and increasing the reference voltage of the chip by a set voltage value, and then jumping to judge whether the difference value between the reference voltage of the chip and the target reference voltage is within an error range.
5. A test device for automatic calibration of reference voltage, comprising:
the starting module starts the chip reference voltage automatic calibration test;
a voltage receiving module that receives a target reference voltage;
the judgment module is used for judging whether the difference value between the reference voltage of the chip and the target reference voltage is within an error range;
the calibration result output module outputs a calibration result after the calibration of the chip reference voltage is passed;
and the parameter setting module is used for changing the reference voltage setting parameters in the chip so as to change the reference voltage of the chip.
6. The apparatus of claim 5, wherein the parameter setting module is implemented by using a reference voltage control module Verf block in a chip.
7. The apparatus for testing automatic calibration of reference voltage according to claim 6, wherein the initial value of the reference voltage setting parameter in the reference voltage control module Verf block is a default reference voltage setting parameter in a chip.
8. The apparatus for testing automatic calibration of reference voltage according to claim 5, wherein the determining module is implemented by a voltage comparator.
9. A storage medium having stored thereon a computer program which, when run on a computer, causes the computer to perform the method of any one of claims 1 to 4.
10. A terminal, characterized in that it comprises a processor and a memory, in which a computer program is stored, the processor being adapted to carry out the method of any one of claims 1 to 4 by calling the computer program stored in the memory.
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| CN202011594557.4A CN112578270A (en) | 2020-12-29 | 2020-12-29 | Test method and device for automatic calibration of reference voltage, storage medium and terminal |
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| CN202011594557.4A CN112578270A (en) | 2020-12-29 | 2020-12-29 | Test method and device for automatic calibration of reference voltage, storage medium and terminal |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113701714A (en) * | 2021-09-23 | 2021-11-26 | 深圳市微特精密科技股份有限公司 | Method and device for identifying flattening calibration of DUT (device under test) by infrared reflection sensor |
| CN113834469A (en) * | 2021-09-23 | 2021-12-24 | 深圳市微特精密科技股份有限公司 | Method and device for identifying flattening calibration of DUT (device under test) by infrared reflection sensor |
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| CN113701714A (en) * | 2021-09-23 | 2021-11-26 | 深圳市微特精密科技股份有限公司 | Method and device for identifying flattening calibration of DUT (device under test) by infrared reflection sensor |
| CN113834469A (en) * | 2021-09-23 | 2021-12-24 | 深圳市微特精密科技股份有限公司 | Method and device for identifying flattening calibration of DUT (device under test) by infrared reflection sensor |
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Application publication date: 20210330 |