CN112530938A - 一种用于soi工艺的横向scr抗静电结构及其制备方法 - Google Patents
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Abstract
本发明公开了一种用于SOI工艺的横向SCR抗静电结构及其制备方法,属于集成电路技术领域。该SCR抗静电结构整体采用环状结构,包括四个区域,构成SCR的横向PNPN结构,并利用金属布线引出,可以根据要求对杂质浓度和尺寸进行调整,采用深槽隔离,可以放置在电路的任何位置。采用高能离子注入及激光退火实现对掺杂浓度及掺杂区尺寸上的精确控制,离子注入采用两步进行,注入射程分别为外延层厚度的40%和30%,采用激光退火工艺实现杂质再扩散,该工艺制备在电路其他结构形成后进行,不经过热过程,不会对电路功能和性能产生影响;采用深槽隔离工艺过程实现对SCR抗静电结构的物理及电学隔离。
Description
技术领域
本发明涉及集成电路技术领域,具体涉及一种用于SOI工艺的横向SCR抗静电结构及其制备方法。
背景技术
随着集成电路的不断发展,在集成电路芯片的测试、封装、运输等环节产生的静电是导致产品可靠性下降的主要因素,如何设计和制备芯片的抗静电结构,即满足抗静电指标要求,同时又较容易实现,已经成为国内外研究的一个重点课题。目前较常见的抗静电结构包括二极管、三极管、MOS器件、SCR(可控硅)等,其中SCR结构由于其更高的鲁棒性,广泛应用于CMOS等集成电路中。
随着加工技术的发展及加工能力的提升,集成电路的尺寸不断缩小,目前主流制程工艺达到了28nm水平,由于SCR结构固有的PNPN结构、杂质横向扩散等方面影响,如图1所示,采用常规工艺制备面积较大,传统SCR结构主要是随阱区或注入区形成,不能自由选择掺杂浓度和掺杂区尺寸,无法满足越来越高的小型化需求,同时过多的杂质注入、热过程等对SCR性能也带来较大影响。在要求较小面积情况下,尤其对于SOI这种浅结工艺,如何形成有效的SCR抗静电结构,同时满足SCR触发电压、维持电压等要求,本专利在设计思路及制备工艺上做出新的尝试。
发明内容
本发明目的是提供一种用于SOI工艺的横向SCR抗静电结构及其制备方法,在满足抗静电性能情况下实现结构小型化,可广泛应用于多种电路设计,在制备工艺方面依靠先进注入及激光退火设备,工艺简单,且可以实现对掺杂浓度及掺杂区尺寸上的精确控制。
本发明为实现上述目的所采用的技术方案是:
一种用于SOI工艺的横向SCR抗静电结构,该SCR抗静电结构包括四个区域,采用环状结构构成SCR的横向PNPN结构,并利用金属布线引出,结构尺寸能够进行调整,采用深槽隔离,可以放置在电路的任何位置。
环状PNPN横向SCR抗静电结构,可以根据要求选择杂质浓度及尺寸,利用工艺实现对SCR参数特性的调整。
该SCR抗静电结构在其他结构形成后进行制备,可以放置在电路的大部分预留区域,具有较高的设计自由度。
所述用于SOI工艺的横向SCR抗静电结构的制备方法,包括以下步骤:
(1)进行N区光刻,形成注入区阻挡层,再进行两次高能磷注入,注入射程分别为外延层的40%和30%,P区也采用相同工艺形成,如果需要调整某区域杂质浓度,可以重复进行光刻、注入工艺过程;
(2)形成SCR结构后进行深槽刻蚀,低温氧化形成侧壁保护,采用PECVD方式淀积多晶硅进行深槽填充,采用CMP化学机械研磨保证表面平坦化,最后低温氧化形成表面氧化层;
(3)依次进行孔刻蚀、金属淀积和金属刻蚀,形成电极引出,实现SCR抗静电结构功能。
该抗静电结构采用高能离子注入,通过激光退火完成杂质的再分布,可以实现对掺杂浓度及掺杂区尺寸上的精确控制;该工艺制备在电路其他结构形成后进行,不经过热过程,不会对电路功能和性能产生影响。
高能离子注入分为两步进行,根据SCR的抗ESD要求,得出各区域掺杂浓度,并确定注入杂质剂量和能量,第一步要求注入射程达到外延层厚度的40%,第二步注入射程达到外延层厚度的30%。
采用深槽隔离方式对SCR抗静电结构进行隔离,以避免对电路其他结构带来电学上的影响;具体制备工艺包括:先进行深槽刻蚀,在SOI衬底片上刻蚀出贯穿整个外延层的沟槽,再进行表面氧化形成侧壁氧化层,采用PECVD进行多晶硅淀积填满深槽,采用化学机械研磨使表面平坦化,最后进行表面低温氧化形成氧化硅,完成深槽隔离。
本发明具有以下有益效果及优点:
1.本发明设计的SCR抗静电结构基于SOI衬底设计,SOI外延层厚度一般要求小于5微米(主要受注入、激光退火等工艺制约)。整体SCR抗静电结构尺寸较小,可以放置在芯片中任意位置,可以满足大多数基于SOI工艺的电路小尺寸等设计要求,相比较传统SCR结构约节省75%左右的面积。
2.该抗静电结构制备采用两步注入加激光退火的方式,制备方法较简单,且不经过热过程,不会对电路功能和性能产生影响。
3.本发明可以实现对SCR抗静电结构各区域对掺杂浓度及掺杂区尺寸上的精确控制,可以根据抗静电指标要求精确控制如触发电压、维持电压等关键参数,可以广泛应用于大多数CMOS电路及双极电路。
4.采用深槽隔离方式保证SCR抗静电结构独立运行,避免影响电路其他结构性能,保证产品可靠性。
附图说明
图1为传统横向SCR抗静电结构;
图2为本发明的SCR抗静电结构版图;
图3为本发明的SCR抗静电结构纵向示意图;
图4为本发明的SCR抗静电结构工艺制备基本流程。
具体实施方式
下面结合附图及实施例对本发明做进一步的详细说明。
如图1所示,传统的SCR抗静电结构多采用横向SCR结构,分别形成N阱和P阱区域,然后利用预淀积方式形成N+和P+区,这种制备方式由于要考虑横向扩散等因素,同时相关区域的形成取决于电路的氧化扩散制备工艺,需要利用的芯片面积较大,无法在保证电路性能的情况下调整SCR结构参数或杂质浓度,工艺局限较大。
如图2所示,本发明SCR抗静电结构为横向PNPN分布,整体分为4个区域,其中最内侧为P区,其引出是端口Ⅰ,为SCR的阳极。其余区域依次为N区、P区、N区,都为环状结构,包围前一个区域,其中第三层P区引出是端口Ⅲ,为SCR的栅极,最外层N区引出是端口Ⅱ,为SCR的阴极。N/P代表区域内不同的杂质类型,每个区域的掺杂浓度、尺寸可以根据SCR参数要求得出。
如图3所示,本发明涉及的SCR抗静电结构为PNPN环形排列的横向结构,应用于SOI工艺中,在外延层中形成相关结构。采用高能注入加激光退火的方式形成PNPN结构;采用深槽刻蚀、PECVD等工艺将SCR抗静电结构与电路进行隔离;采用金属层引出端口实现抗静电功能。
如图4所示,为本发明的SCR抗静电结构工艺制备基本流程,首先进行N区光刻,形成注入区阻挡层,再进行两次高能磷注入,注入射程分别为外延层的40%和30%,P区也采用相同工艺形成,如果需要调整某区域杂质浓度,可以重复进行光刻、注入工艺过程;然后进行深槽刻蚀,并进行低温氧化形成侧壁保护,采用PECVD方式淀积多晶硅,采用CMP化学机械研磨保证表面平坦化,利用低温氧化将SCR抗静电结构同电路其他结构进行隔离;最后依次进行孔刻蚀、金属淀积和金属刻蚀,形成电极引出,实现SCR抗静电结构的功能。
Claims (7)
1.一种用于SOI工艺的横向SCR抗静电结构,其特征在于:该SCR抗静电结构整体采用环状结构,包括四个区域,构成SCR的横向PNPN结构,并利用金属布线引出,结构尺寸能够进行调整,采用深槽隔离,可以放置在电路的任何位置。
2.根据权利要求1所述的用于SOI工艺的横向SCR抗静电结构,其特征在于:环状PNPN横向SCR抗静电结构,可以根据要求选择杂质浓度及尺寸,利用工艺实现对SCR参数特性的调整。
3.根据权利要求1所述的用于SOI工艺的横向SCR抗静电结构,其特征在于:该SCR抗静电结构在其他结构形成后进行制备,可以放置在电路的大部分预留区域,具有较高的设计自由度。
4.根据权利要求1-3任一所述的用于SOI工艺的横向SCR抗静电结构的制备方法,其特征在于:该方法包括以下步骤:
(1)进行N区光刻,形成注入区阻挡层,再进行两次高能磷注入,注入射程分别为外延层的40%和30%,P区也采用相同工艺形成,如果需要调整某区域杂质浓度,可以重复进行光刻、注入工艺过程;
(2)形成SCR结构后进行深槽刻蚀,低温氧化形成侧壁保护,采用PECVD方式淀积多晶硅进行深槽填充,采用CMP化学机械研磨保证表面平坦化,最后低温氧化形成表面氧化层;
(3)依次进行孔刻蚀、金属淀积和金属刻蚀,形成电极引出,实现SCR抗静电结构功能。
5.根据权利要求4所述的用于SOI工艺的横向SCR抗静电结构的制备方法,其特征在于:该抗静电结构采用高能离子注入,通过激光退火完成杂质的再分布,可以实现对掺杂浓度及掺杂区尺寸上的精确控制;该工艺制备在电路其他结构形成后进行,不经过热过程,不会对电路功能和性能产生影响。
6.根据权利要求4所述的用于SOI工艺的横向SCR抗静电结构制备方法,其特征在于:高能离子注入分为两步进行,根据SCR的抗ESD要求,得出各区域掺杂浓度,并确定注入杂质剂量和能量,第一步要求注入射程达到外延层厚度的40%,第二步注入射程达到外延层厚度的30%。
7.根据权利要求4所述的用于SOI工艺的横向SCR抗静电结构的制备方法,其特征在于:采用深槽隔离方式对SCR抗静电结构进行隔离,以避免对电路其他结构带来电学上的影响;具体制备工艺包括:先进行深槽刻蚀,在SOI衬底片上刻蚀出贯穿整个外延层的沟槽,再进行表面氧化形成侧壁氧化层,采用PECVD进行多晶硅淀积填满深槽,采用化学机械研磨使表面平坦化,最后进行表面低温氧化形成氧化硅,完成深槽隔离。
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CN113224000B (zh) * | 2021-04-25 | 2023-09-12 | 华虹半导体(无锡)有限公司 | 一种改善小尺寸接触孔工艺窗口的方法 |
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