CN112490135A - 封装组件及其形成方法 - Google Patents

封装组件及其形成方法 Download PDF

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Publication number
CN112490135A
CN112490135A CN202010222958.0A CN202010222958A CN112490135A CN 112490135 A CN112490135 A CN 112490135A CN 202010222958 A CN202010222958 A CN 202010222958A CN 112490135 A CN112490135 A CN 112490135A
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etch stop
stop layer
layer
semiconductor
semiconductor device
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陈振宇
刘铭棋
陈逸群
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

在一些实施例中，本发明涉及一种形成封装组件的方法。在半导体衬底的前侧上方形成湿式蚀刻终止层。在湿式蚀刻终止层上方形成牺牲半导体层，以及在牺牲半导体层上方形成干式蚀刻终止层。可在干式蚀刻终止层上方形成半导体装置层的堆叠。执行接合工艺以将半导体装置层的堆叠接合到集成电路管芯的前侧，其中半导体衬底的前侧面向集成电路管芯的前侧。执行湿式蚀刻工艺以去除半导体衬底，以及执行干式蚀刻工艺以去除湿式蚀刻终止层和牺牲半导体层。

Description

封装组件及其形成方法
技术领域
本发明实施例涉及一种封装组件及其形成方法。
背景技术
半导体产业通过例如减小最小特征大小而持续改进各种电子部件(例如晶体管、二极管、电阻器、电容器等)的集成密度，使更多部件集成于给定区域中。开发出利用较少区域或较小高度的较小的封装结构来封装半导体装置。举例来说，为进一步增加每个区域的电路密度，倒装芯片接合可用于通过焊料凸块将半导体装置竖直地耦接到集成芯片或电路板。
发明内容
本发明实施例的一种形成封装组件的方法，包括：在半导体衬底的前侧上方形成湿式蚀刻终止层；在湿式蚀刻终止层上方形成牺牲半导体层；在牺牲半导体层上方形成干式蚀刻终止层；在干式蚀刻终止层上方形成半导体装置层的堆叠；执行接合工艺以将半导体装置层的堆叠接合到集成电路管芯的前侧，其中半导体衬底的前侧面向集成电路管芯的前侧；执行湿式蚀刻工艺以去除半导体衬底；以及执行干式蚀刻工艺以去除湿式蚀刻终止层和牺牲半导体层。
本发明实施例的一种形成封装组件的方法，包括：在半导体衬底上方形成第一蚀刻终止层；在第一蚀刻终止层上方形成牺牲半导体层，其中牺牲半导体层比半导体衬底更厚；在牺牲半导体层上方形成第二蚀刻终止层；在第二蚀刻终止层上方形成装置层的堆叠，其中装置层的堆叠的背侧接触第二蚀刻终止层；将装置层的堆叠的前侧接合到集成电路管芯；执行湿式蚀刻工艺以去除半导体衬底；以及执行干式蚀刻工艺以去除第一蚀刻终止层和牺牲半导体层。
本发明实施例的一种封装组件，包括：集成电路管芯，包括衬底上方的金属互连结构；半导体装置，布置在金属互连结构上方且电性耦接到金属互连结构；蚀刻终止层，布置在半导体装置上方，其中蚀刻终止层包括介电材料；以及侧壁保护结构，包围半导体装置，其中侧壁保护结构的最上表面在蚀刻终止层上方，其中侧壁保护结构具有从蚀刻终止层的顶部表面到蚀刻终止层的底部表面直接地且连续地接触蚀刻终止层的外侧壁的内侧壁。
附图说明
结合附图阅读以下详细描述会最佳地理解本发明的各方面。应注意，根据业界中的标准惯例，各个特征未按比例绘制。实际上，为了论述清楚起见，可任意增大或减小各个特征的尺寸。
图1示出具有接合到集成电路管芯的半导体装置的封装组件的一些实施例的横截面视图，其中侧壁保护结构直接地并连续地接触半导体装置的外侧壁和干式蚀刻终止层，所述干式蚀刻终止层是介电材料。
图2A和图2B示出图1的封装组件的一些更详细实施例的横截面视图，其中半导体装置对应于发光二极管(light emitting diode；LED)和竖直腔表面发射激光器(verticalcavity surface emitting laser；VCSEL)。
图3到图13示出使用包含湿式蚀刻工艺和干式蚀刻工艺的倒装芯片接合工艺将半导体装置接合到集成电路管芯的方法的一些实施例的横截面视图。
图14示出对应于图3到图13的方法的一些实施例的流程图。
具体实施方式
以下揭示内容提供用于实施所提供主题的不同特征的许多不同实施例或实例。下文描述部件和布置的特定实例来简化本发明。当然，这些只是实例且并不意欲为限制性的。举例来说，在以下描述中，第一特征在第二特征上方或第二特征上的形成可包含第一特征和第二特征直接接触地形成的实施例，并且还可包含额外特征可在第一特征与第二特征之间形成，使得第一特征和第二特征可不直接接触的实施例。另外，本发明可在各个实例中重复附图标号和/或字母。此重复是出于简单和清晰的目的，且本身并不指示所论述的各种实施例和/或配置之间的关系。
此外，为易于描述，在本文中可使用例如“在…下面(beneath)”、“在…下方(below)”、“下部(lower)”、“在…上方(above)”、“上部(upper)”等等的空间相关术语，以描述如图中所示出的一个元件或特征相对于另一元件或特征的关系。除了图中所描绘的定向之外，空间相对术语意图涵盖在使用或操作中的装置的不同定向。设备可以其它方式定向(旋转90度或处于其它定向)，且本文中所使用的与空间相关的描述词可类似地相应地进行解释。
一些倒装芯片接合工艺可包含首先形成布置在半导体衬底上方的半导体装置层。第一蚀刻终止层可布置在半导体装置层的堆叠与半导体衬底之间。接合结构可形成于半导体装置层的堆叠上方，使得接合结构的背侧直接地接触半导体装置层的堆叠。半导体衬底可随后被倒装，且接合结构的前侧可经由例如焊料凸块接合到集成电路(integratedcircuit；IC)。侧壁保护结构可沿着半导体装置层的堆叠的外侧壁形成，以防止在去除半导体衬底期间损坏半导体装置层。
通常，随后使用湿式化学蚀刻剂去除半导体衬底以增加生产速度，这是因为湿式化学蚀刻剂可比干式蚀刻剂更快地去除半导体衬底。虽然第一蚀刻终止层旨在防止湿式化学蚀刻剂去除和/或损坏半导体装置层，但是湿式化学蚀刻剂可经由侧壁保护结构与蚀刻终止层之间的界面渗透到半导体装置层的堆叠中。对半导体装置层的堆叠的损坏可包含例如，因半导体装置层的堆叠与湿式化学蚀刻剂之间的化学反应所致的界面处的开裂或半导体装置层的堆叠区域中的组合物的变化。
本申请的各种实施例是针对两个蚀刻停止层、湿式蚀刻工艺以及干式蚀刻工艺，以减轻在去除半导体衬底时对半导体装置层的堆叠的损坏。在一些实施例中，第一蚀刻终止层形成于半导体衬底上方。比半导体衬底更薄的牺牲半导体层可随后形成于第一蚀刻终止层上方，且第二蚀刻终止层可沉积于牺牲半导体层上方。多个半导体层可形成于第二蚀刻终止层上方以形成半导体装置层的堆叠。接合层可形成于半导体装置层的堆叠上方。半导体衬底可倒装于IC管芯上方以将接合层接合到IC管芯的接合结构(例如焊料凸块)。为了从半导体装置层的堆叠去除半导体衬底和牺牲半导体层，可执行湿式蚀刻工艺以去除半导体衬底。第一蚀刻终止层可防止湿式蚀刻工艺继续经过第一蚀刻终止层。因此，第一蚀刻终止层和牺牲半导体层保护半导体装置层的堆叠免受湿式蚀刻工艺。可随后执行干式蚀刻工艺以去除第一蚀刻终止层和牺牲半导体层。由于牺牲半导体层、第二蚀刻终止层以及干式蚀刻工艺，防止由湿式化学蚀刻剂对半导体装置层的堆叠的损坏，从而产生与IC管芯接合的可靠半导体装置。
图1示出包括接合到集成电路管芯的半导体装置结构上方的干式蚀刻终止层的封装组件的一些实施例的横截面视图100。
横截面视图100中的封装组件包括接合到集成电路(IC)管芯130的半导体装置120。在一些实施例中，IC管芯130包括安置于IC管芯衬底132上方的互连结构140。在一些实施例中，IC管芯衬底132包括半导体材料，且晶体管装置134集成于IC管芯衬底132内。举例来说，在一些实施例中，晶体管装置134可各自是包括在IC管芯衬底132内的源极/漏极区134a的金属氧化物半导体场效应晶体管(metal oxide semiconductor field effecttransistor；MOSFET)。此外，在一些实施例中，晶体管装置134可各自包括栅极电极134b，所述栅极电极134b在IC管芯衬底132上的栅极介电层134c上方和在源极/漏极区134a之间。在一些实施例中，互连结构140可包括嵌入于介电结构142中的互连线146和互连通孔144的网络。在一些实施例中，互连线146和互连通孔144耦接到晶体管装置134。举例来说，在横截面视图100中，互连线146和互连通孔144耦接到晶体管装置134的源极/漏极区134a。在其它实施例中(未示出)，互连线146和互连通孔144可耦接到晶体管装置134的栅极电极134b。在又其它实施例中(未示出)，将了解，互连线146和互连通孔144中的一些可耦接到晶体管装置134中的一些的源极/漏极区134a，且其它互连线146和互连通孔144可耦接到其它晶体管装置134的栅极电极134b。
在一些实施例中，半导体装置120通过包括例如安置于接合垫148上方的焊料凸块150的接合结构147接合到IC管芯130。接合垫148可通过互连结构140接合到晶体管装置134且因此电性耦接到晶体管装置134。在一些实施例中，接合垫148布置在互连结构140的顶部表面上方，且焊料凸块150接合到半导体装置120的背侧120b。此外，在一些实施例中，接合垫148中的一些可通过其它电连接154(例如，线)耦接到半导体装置120的前侧120f，使得偏压(例如电压偏压)可在半导体装置120的操作期间施加在半导体装置120的前侧120f和背侧120b上。
在一些实施例中，每个半导体装置120可包括布置在接合层112上方的半导体装置层110的堆叠。半导体装置层110可制成各种半导体装置，例如发光二极管(LED)装置、竖直腔表面发射激光器(VCSEL)装置、传感器装置或某一其它半导体装置。接合层112可接合到接合结构147。在一些实施例中，封装组件可包括多于一个半导体装置120。在此类实施例中，每个半导体装置120可彼此电隔离，然而在其它实施例中，半导体装置120中的至少一些可彼此电性耦接。在一些实施例中，干式蚀刻终止层108可布置在半导体装置层110的堆叠上方，且侧壁保护结构122可横向地包围接合层112、半导体装置层110的堆叠以及干式蚀刻终止层108。在一些实施例中，侧壁保护结构122可具有在干式蚀刻终止层108上方延伸的顶部表面122t。
在一些实施例中，侧壁保护结构122和干式蚀刻终止层108可包围半导体装置层110的堆叠的外侧壁和上部表面，以在制造期间保护半导体装置层110的堆叠。在一些实施例中，干式蚀刻终止层108和侧壁保护结构122可包括相同材料，所述材料为例如氧化硅、氮化硅或氮氧化硅的介电材料。干式蚀刻终止层108的外侧壁可在第一界面152处直接地接触侧壁保护结构122的内侧壁。在一些实施例中，第一界面152可从干式蚀刻终止层108的顶部表面连续地延伸到干式蚀刻终止层108的底部表面。换句话说，在一些实施例中，在侧壁保护结构122与干式蚀刻终止层108之间不存在分层。在一些实施例中，侧壁保护结构122与干式蚀刻终止层108之间不存在分层可归因于侧壁保护结构122和干式蚀刻终止层108包括相同或相似的介电材料。此外，在一些实施例中，半导体装置层110的堆叠的外侧壁可在第二界面153处直接地接触侧壁保护结构122的内侧壁。第二界面153可从半导体装置层110的堆叠的顶部表面连续地延伸到半导体装置层110的堆叠的底部表面。换句话说，在一些实施例中，在侧壁保护结构122与半导体装置层110的堆叠之间不存在分层。因此，半导体装置层110的堆叠可由侧壁保护结构122和干式蚀刻终止层108保护，以防止制造条件对半导体装置层110的损坏。
图2A示出包括接合到集成电路管芯的发光二极管(LED)装置的封装组件的一些实施例的横截面视图200A。
在一些实施例中，半导体装置120可为或包括LED装置。在此类实施例中，半导体装置层110的堆叠可包括具有第一掺杂类型(例如n型)的第一半导体区202及布置在第一半导体区202上方的具有第二掺杂类型(例如p型)的第二半导体区206。有源区204可布置在第一半导体区202与第二半导体区206之间。举例来说，第一半导体区202可包括n型氮化镓，第二半导体区206可包括p型氮化镓，且有源区204可包括氮化铟镓。在LED装置中，由于施加在半导体装置层110的堆叠上的偏压，在有源区204处的电子-空穴复合，LED装置可发射彩色光。
图2B示出包括接合到集成电路管芯的竖直腔表面发射激光器(VCSEL)的封装组件的一些实施例的横截面视图200B。
在一些实施例中，半导体装置120可包括VCSEL装置。在此类实施例中，半导体装置层110的堆叠可包括交替堆叠的多个第一反射器层208和多个第二反射器层212。光学有源区210可布置在第一反射器层208与第二反射器层212的交替层之间。举例来说，在一些实施例中，第一反射器层208可包括铝砷化镓，且第二反射器层212可包括砷化镓。光学有源区210可在偏压施加在半导体装置层110的堆叠上之后发射光，且光可通过第一反射器层208和第二反射器层212反射以通过半导体装置120的前侧120f发射对焦激光。因此，在一些实施例中，为使对焦激光离开半导体装置120的前侧120f，干式蚀刻终止层108可为透明的；或在其它实施例中，在将半导体装置120接合到IC管芯130之后，可去除干式蚀刻终止层108的一部分。然而，在将半导体装置120接合到IC管芯130的制造工艺期间，干式蚀刻终止层108和侧壁保护结构122保护半导体装置层110的堆叠免受损坏。
图3到图13示出使用半导体装置上的干式蚀刻终止层和湿式蚀刻终止层形成封装组件的方法的一些实施例的横截面视图300到横截面视图1300。尽管关于方法描述图3到图13，但应了解，图3到图13中所公开的结构不限于此方法，但取而代之，可单独作为独立于方法的结构。
如图3的横截面视图300中所示，提供半导体衬底302。在一些实施例中，半导体衬底302可包括半导体材料，例如砷化镓。在一些实施例中，半导体衬底302可具有大于例如约600微米的第一厚度t1。半导体衬底302的前侧302f上可形成湿式蚀刻终止层304。在一些实施例中，湿式蚀刻终止层304可包括例如磷化铟镓、磷化铟、磷化铟镓砷或类似物。因此，在一些实施例中，湿式蚀刻终止层304可包括半导体材料。在一些实施例中，湿式蚀刻终止层304可具有等于最多例如40微米的第二厚度t2。湿式蚀刻终止层304的第二厚度t2必须足够厚以抵抗来自湿式蚀刻工艺(参见图11的湿式蚀刻工艺1102)的湿式蚀刻剂。在一些实施例中，湿式蚀刻终止层304可借助于气相沉积工艺(例如化学气相沉积(chemical vapordeposition；CVD)、物理气相沉积(physical vapor deposition；PVD)、原子层沉积(atomiclayer deposition；ALD)等)形成或可由外延生长或沉积工艺形成。
在湿式蚀刻终止层304上可形成牺牲半导体层306。在一些实施例中，牺牲半导体层306可包括砷化镓，且因此包括与半导体衬底302相同的半导体材料。在一些实施例中，牺牲半导体层306可具有最多为例如1微米的第三厚度t3。因此，牺牲半导体层306可比半导体衬底302更薄(例如t3小于t1)，这使得牺牲半导体层306相较半导体衬底302更有效地由干式蚀刻工艺(参见图12的干式蚀刻工艺1202)去除。在一些实施例中，牺牲半导体层306可以是衬底，且因此可接合到湿式蚀刻终止层304的顶部表面并由化学机械抛光(chemicalmechanical polish；CMP)或某一其它合适的薄化工艺薄化。在替代性实施例中，牺牲半导体层306可借助于外延生长工艺形成。因此，在一些实施例中，湿式蚀刻终止层304为或包括半导体材料以促进牺牲半导体层306的外延生长或沉积。
在牺牲半导体层306上可沉积干式蚀刻终止层308。在一些实施例中，干式蚀刻终止层308可包括介电材料，例如二氧化硅、氮化硅或氮氧化硅。因此，干式蚀刻终止层308可包括与湿式蚀刻终止层304不同的材料。在一些实施例中，干式蚀刻终止层308可具有最多例如70纳米的第四厚度t4。因此，在一些实施例中，干式蚀刻终止层308可比湿式蚀刻终止层304更薄，然而在其它实施例中，干式蚀刻终止层308可与湿式蚀刻终止层304的厚度大约相当或比湿式蚀刻终止层304更厚。在一些实施例中，如果干式蚀刻终止层308大于70纳米，则可能不利地影响制造时间。然而，如果干式蚀刻终止层308太薄(例如小于10纳米)，则可能无法抵抗干式蚀刻工艺(参见图12的干式蚀刻工艺1202)，且因此，将无法在一些实施例中充当蚀刻终止层。在一些实施例中，干式蚀刻终止层308可借助于气相沉积工艺(例如化学气相沉积(CVD)、物理气相沉积(PVD)、原子层沉积(ALD)等)来沉积。
在干式蚀刻终止层308上可形成半导体装置层310，使得半导体装置层310的背侧接触干式蚀刻终止层308。半导体装置层310可包括视所需应用而定的各种半导体材料的许多层。举例来说，在一些实施例中，半导体装置层310可包括用于传感器、LED装置(参见图2A)或VCSEL装置(参见图2B)的层。在一些实施例中，半导体装置层310可具有在例如约10微米与约15微米之间的范围内的厚度。在一些实施例中，半导体装置层310可借助于外延沉积工艺形成。
在一些实施例中，在半导体装置层310上可沉积接合层312。在一些实施例中，接合层312包括也经受焊接工艺(参见图8到图10)的导电材料，例如镍或金。在一些实施例中，接合层312可借助于气相沉积工艺(例如化学气相沉积(CVD)、物理气相沉积(PVD)、原子层沉积(ALD)、溅射等)来沉积。
如图4的横截面视图400中所示，在一些实施例中，掩蔽层402可在接合层312上方沉积和图案化。根据针对应用将形成的半导体装置的数量，掩蔽层402可经图案化为包括多个片段。举例来说，在一些实施例中，掩蔽层402可包括由旋转涂布工艺形成的感光材料(例如光刻胶)。在此类实施例中，感光材料的层根据光掩模(photomask)或光罩(photoreticle)选择性地暴露于电磁辐射。电磁辐射改变感光材料内的暴露区的可溶性以定义可溶区。感光材料随后显影以通过去除可溶区来定义感光材料内的开口404。在其它实施例中，掩蔽层402可包括硬掩模层(例如氮化硅层、碳化硅层或类似物)。
如图5的横截面视图500中所示，第一蚀刻工艺是根据掩蔽层402中的开口(图4的开口404)执行以将半导体装置层(图4的半导体装置层310)图案化为例如三个半导体装置120，所述三个半导体装置120中的每一个包括接合层112与干式蚀刻终止层108之间的半导体装置层110的堆叠。将了解，半导体装置120的数量可小于或大于三个，且视封装组件的所需应用的参数而定。在一些实施例中，第一蚀刻工艺使用多个蚀刻剂以蚀刻接合层112、半导体装置层110的堆叠以及干式蚀刻终止层108的各种材料。此外，在一些实施例中，第一蚀刻工艺可持续至牺牲半导体层306，但第一蚀刻工艺并不持续进行至蚀刻牺牲半导体层306的整个厚度。因此，在一些实施例中，在第一蚀刻工艺之后，牺牲半导体层306可将每个半导体装置120彼此连接。
如图6的横截面视图600中所示，在一些实施例中，介电层602沉积于半导体装置120和牺牲半导体层306上。介电层602可包括介电材料，例如二氧化硅、氮化硅或氮氧化硅。因此，在一些实施例中，介电层602可包括与干式蚀刻终止层108相同的材料。在一些实施例中，介电层602可具有例如在约100纳米与约130纳米之间的范围内的厚度。在其它实施例中，介电层602的厚度可例如大于130纳米。在一些实施例中，介电层602可借助于气相沉积工艺(例如化学气相沉积(CVD)、物理气相沉积(PVD)、原子层沉积(ALD)、溅射等)来沉积。介电层602可直接地且连续地接触每个干式蚀刻终止层108和每个半导体装置层110的堆叠的外表面。
如图7的横截面视图700中所示，可执行第二蚀刻工艺以去除介电层(图6的介电层602)的水平部分，从而在每个半导体装置120上形成侧壁保护结构122。在一些实施例中，第二蚀刻工艺是纵向蚀刻，使得可在不使用掩蔽层的情况下去除介电层(图6的介电层602)的水平部分。在一些实施例中，从图7的横截面视图700的角度，侧壁保护结构122可具有基本上磨圆的上部拐角122c。此外，在一些实施例中，从图7的横截面视图700的角度，侧壁保护结构122可具有低于干式蚀刻终止层108的最底部表面108b的最底部表面122b。
如图8的横截面视图800中所示，半导体衬底302是倒装的，使得半导体衬底302的前侧302f面向集成电路(IC)管芯130的前侧130f。IC管芯130可包括集成在IC管芯衬底132中的晶体管装置134。在一些实施例中，IC管芯衬底132可包括例如半导体晶片或晶片上的一个或多个管芯的任何类型的半导体主体(例如硅/CMOS块体、SiGe、SOI等)，以及形成在其上和/或与其相关联的任何其它类型的半导体和/或外延层。在一些实施例中，晶体管装置134包括IC管芯衬底132中的源极/漏极区134a以及布置在IC管芯衬底132上及源极/漏极区134a之间的栅极电极134b。在一些实施例中，栅极介电层134c将栅极电极134b与IC管芯衬底132分离开。包括嵌入于介电结构142中的互连线146和互连通孔144的互连结构140可在IC管芯衬底132上方形成。在一些实施例中，介电结构142可包括陶瓷材料，例如碳化硅、氧化铝、硼化硅或类似物。互连线146和互连通孔144可包括导电材料，例如铜或钨。互连线146和互连通孔144可将晶体管装置134耦接到IC管芯130的前侧130f上的接合结构147。在一些实施例中，接合结构147包括接合垫148，且每个接合垫148可耦接到每个晶体管装置134。在一些实施例中，焊料凸块150可在接合垫148上沉积以接合到半导体装置120。在一些实施例中，接合垫148可包括导电材料，例如铜、钨、铝、镍或金。在一些实施例中，焊料凸块150可包括例如镍或金。
在一些实施例中，半导体装置120中的每一个可在焊料凸块150中的一个上方对准。因此，在一些实施例中，半导体装置120可具有与焊料凸块150中的每一个相同或约相同的间距。接合工艺802可随后开始，这可首先开始于使半导体衬底302朝向IC管芯130移动。接合工艺802可随后持续进行到图9。
如图9的横截面视图900中所示，接合层112与焊料凸块150接触。在一些实施例中，接合工艺(图8的接合工艺802)可包含加热过程，其中焊料凸块150充分地加热使得焊料凸块150接合到接合层112。
如图10的横截面视图1000中所示，接合工艺(图8的接合工艺802)可持续进行到在牺牲半导体层306与IC管芯130之间注入底部填充材料1002。底部填充材料1002还可以在相邻半导体装置120之间注入。在一些实施例中，底部填充材料1002是具有高热膨胀系数的环氧树脂。可随后进行热压缩工艺以加固并机械稳定焊料凸块150与接合层112之间的接合。
如图11的横截面视图1100中所示，可使用湿式化学蚀刻剂来执行湿式蚀刻工艺1102以去除半导体衬底(图10的半导体衬底302)。因为半导体衬底(图10的半导体衬底302)极厚(例如大于100微米)，所以湿式蚀刻工艺1102用于具有时效性的制造工艺。湿式蚀刻工艺1102对半导体衬底(图10的半导体衬底302)的去除为基本上选择性的(substantiallyselective)，且对湿式蚀刻终止层304的去除为基本上非选择性的。因此，湿式蚀刻终止层304防止湿式蚀刻工艺1102的湿式化学蚀刻剂渗入到牺牲半导体层306中。在一些实施例中，湿式化学蚀刻剂可包括例如硫酸、柠檬酸或过氧化氢。在一些实施例中，在湿式蚀刻工艺1102之后，湿式蚀刻终止层304可更薄。然而，在其它实施例中，湿式蚀刻终止层304的组合物可对湿式蚀刻工艺1102的湿式化学蚀刻剂具有耐受性，使得湿式蚀刻终止层304保持不受湿式蚀刻工艺1102影响。
如图12的横截面视图1200中所示，可使用干式蚀刻剂来执行干式蚀刻工艺1202以去除湿式蚀刻终止层(图11的湿式蚀刻终止层304)和牺牲半导体层(图11的牺牲半导体层306)。因为湿式蚀刻终止层(图11的湿式蚀刻终止层304)和牺牲半导体层(图11的牺牲半导体层306)足够薄(例如小于100微米)，所以可在不用大量使用制造时间的情况下使用干式蚀刻工艺1202。在一些实施例中，干式蚀刻工艺1202首先使用第一干式蚀刻剂以去除湿式蚀刻终止层(图11的湿式蚀刻终止层304)。举例来说，在一些实施例中，第一干式蚀刻剂包括氟基气体，例如氟化碳化合物(例如CF4、C4F8、CHF3等)。在一些实施例中，牺牲半导体层(图11的牺牲半导体层306)可抵抗通过第一干式蚀刻剂的去除。因此，在通过第一干式蚀刻剂去除湿式蚀刻终止层(图11的湿式蚀刻终止层304)之后，干式蚀刻工艺1202可随后使用第二干式蚀刻剂以去除牺牲半导体层(图11的牺牲半导体层306)。举例来说，在一些实施例中，第二干式蚀刻剂可包括氯基气体，例如氯气(Cl2)或氯化硼(BCl3)。为防止干式蚀刻剂去除覆盖并保护半导体装置层110的堆叠的干式蚀刻终止层108，干式蚀刻终止层108包括与牺牲半导体层(图11的牺牲半导体层306)不同的材料，且干式蚀刻终止层108对第二干式蚀刻剂具有耐受性。在一些实施例中，一些干式蚀刻终止层108可在干式蚀刻工艺1202期间去除。举例来说，在一些实施例中，在干式蚀刻工艺1202之前，干式蚀刻终止层108可具有第四厚度(参见图3和图11的第四厚度t4)，且在干式蚀刻工艺1202之后，干式蚀刻终止层108可具有小于第四厚度(图11的第四厚度t4)的第五厚度t5。然而，干式蚀刻终止层108对第二干式蚀刻剂越耐受，则第四厚度(图11的第四厚度t4)与第五厚度t5之间的差异越小，且干式蚀刻终止层108的顶表面越光滑。在一些实施例中，侧壁保护结构122也包括与干式蚀刻终止层108相同的材料。因此，在一些实施例中，侧壁保护结构122也基本上对干式蚀刻工艺1202的第二蚀刻剂具有耐受性。因此，侧壁保护结构122和干式蚀刻终止层108都可保护半导体装置层110的堆叠免受由干式蚀刻工艺1202导致的损坏。此外，因为使用干式蚀刻工艺1202代替湿式蚀刻工艺(例如图11的湿式蚀刻工艺1102)以去除牺牲半导体层(图11的牺牲半导体层306)，从而暴露出干式蚀刻终止层108，因此防止侧壁保护结构122、干式蚀刻终止层108以及半导体装置层110的堆叠之间的分层导致的损坏。此外，因为侧壁保护结构122和干式蚀刻终止层108都是相同的介电材料，这可能造成相较在侧壁保护结构122和干式蚀刻终止层108包括不同材料的情况分层更困难，所以还可以减轻分层。因此，在一些实施例中，半导体装置层110的堆叠可在湿式蚀刻工艺(图11的湿式蚀刻工艺1102)之前具有第一缺陷浓度且在干式蚀刻工艺1202之后具有第二缺陷浓度。因为半导体装置层110的堆叠受干式蚀刻终止层108和侧壁保护结构122的保护，所以第一缺陷浓度可等于第二缺陷浓度。此外，因为防止了分层，可防止对半导体装置层110的其它损坏，例如湿式蚀刻工艺1102和干式蚀刻工艺1202的蚀刻剂与半导体装置层110的堆叠之间的化学反应。
如图13的横截面视图1300中所示，在一些实施例中，可去除底部填充材料1002。在一些实施例中，可通过溶剂去除底部填充材料1002。此外，在去除底部填充材料1002之后，可进行更多图案化和/或电连接(例如图1的电连接154)以产生包括功能性半导体装置120的封装组件。
图14示出对应于图3到图13的方法1400的一些实施例的流程图。
虽然方法1400在下文示出且描述为一系列动作或事件，但应了解，不应以限制意义来解释此类动作或事件的所示出的排序。举例来说，除本文中所示出和/或描述的动作或事件之外，一些动作可与其它动作或事件以不同次序和/或同时出现。另外，可能需要并非所有的所示出动作以实施本文中的描述的一个或多个方面或实施例。此外，本文中所描绘的动作中的一个或多个可以一个或多个单独动作和/或阶段进行。
在动作1402处，在半导体衬底上方形成湿式蚀刻终止层。
在动作1404处，在湿式蚀刻终止层上方形成牺牲半导体层，其中牺牲半导体层比半导体衬底更薄。
在动作1406处，在牺牲半导体层上方沉积包括介电材料的干式蚀刻终止层。
在动作1408处，在干式蚀刻终止层上方形成半导体装置层的堆叠。
在动作1410处，在半导体装置层的堆叠上方沉积接合层。图3示出对应于动作1402、动作1404、动作1406、动作1408以及动作1410的一些实施例的横截面视图300。
在动作1412处，将接合层接合到接合垫上的一个或多个焊料凸块。图8到图10示出对应于动作1412的一些实施例的横截面视图800到横截面视图1000。
在动作1414处，执行湿式蚀刻工艺以去除半导体衬底。图11示出对应于动作1414的一些实施例的截面视图1100。
在动作1416处，执行干式蚀刻工艺以去除湿式蚀刻终止层和牺牲半导体层。图12示出对应于动作1416的一些实施例的横截面视图1200。
因此，本发明实施例涉及一种形成封装组件的方法，其使用化学蚀刻工艺随后使用干式蚀刻工艺以使用湿式化学蚀刻剂从半导体层的堆叠去除牺牲衬底层而不损坏半导体层。
因此，在一些实施例中，本发明涉及一种形成封装组件的方法，包括：在半导体衬底的前侧上方形成湿式蚀刻终止层；在湿式蚀刻终止层上方形成牺牲半导体层；在牺牲半导体层上方形成干式蚀刻终止层；在干式蚀刻终止层上方形成半导体装置层的堆叠；执行接合工艺以将半导体装置层的堆叠接合到集成电路管芯的前侧，其中半导体衬底的前侧面向集成电路管芯的前侧；执行湿式蚀刻工艺以去除半导体衬底；以及执行干式蚀刻工艺以去除湿式蚀刻终止层和牺牲半导体层。
在一些实施例中，所述半导体衬底比所述牺牲半导体层更厚。
在一些实施例中，所述方法进一步包括：将所述半导体装置层的堆叠及所述干式蚀刻终止层图案化，以形成第一半导体装置及与所述第一半导体装置横向间隔开的第二半导体装置，其中在图案化之后，所述第一半导体装置及所述第二半导体装置由所述牺牲半导体层连接。
在一些实施例中，所述干式蚀刻终止层在所述干式蚀刻工艺之后比在所述干式蚀刻工艺之前更薄。
在一些实施例中，所述接合工艺包括：在所述牺牲半导体层与所述集成电路管芯之间沉积底部填充材料。
在一些实施例中，所述方法进一步包括：在所述干式蚀刻工艺之后去除所述底部填充材料。
在一些实施例中，所述方法进一步包括：在执行所述湿式蚀刻工艺之前，在所述半导体装置层的堆叠的外侧壁上形成侧壁保护结构。
在一些实施例中，在执行所述干式蚀刻工艺之后，所述侧壁保护结构具有在所述干式蚀刻终止层的最顶部表面上方的顶部表面。
在一些实施例中，所述干式蚀刻终止层在界面处与所述侧壁保护结构直接接触，以及其中所述界面从所述干式蚀刻终止层的顶部表面连续地延伸到所述干式蚀刻终止层的底部表面。
在其它实施例中，本发明涉及一种形成封装组件的方法，包括：在半导体衬底上方形成第一蚀刻终止层；在第一蚀刻终止层上方形成牺牲半导体层，其中牺牲半导体层比半导体衬底更厚；在牺牲半导体层上方形成第二蚀刻终止层；在第二蚀刻终止层上方形成装置层的堆叠，其中装置层的堆叠的背侧接触第二蚀刻终止层；将装置层的堆叠的前侧接合到集成电路管芯；执行湿式蚀刻工艺以去除半导体衬底；以及执行干式蚀刻工艺以去除第一蚀刻终止层和牺牲半导体层。
在一些实施例中，所述第一蚀刻终止层包括不同于所述第二蚀刻终止层的材料。
在一些实施例中，所述第一蚀刻终止层比所述第二蚀刻终止层更厚。
在一些实施例中，在所述干式蚀刻工艺之后，所述第二蚀刻终止层完全覆盖所述装置层的堆叠的所述背侧。
在一些实施例中，所述干式蚀刻工艺使用第一干式蚀刻剂以去除所述第一蚀刻终止层，以及使用不同于所述第一干式蚀刻剂的第二干式蚀刻剂以去除所述牺牲半导体层。
在一些实施例中，所述装置层的堆叠在所述湿式蚀刻工艺之前具有第一缺陷浓度，其中所述装置层的堆叠在所述干式蚀刻工艺之后具有第二缺陷浓度，以及其中所述第一缺陷浓度等于所述第二缺陷浓度。
在又其它实施例中，本发明涉及一种封装组件，包括：集成电路管芯，包括衬底上方的金属互连结构；半导体装置，布置在金属互连结构上方且电性耦接到金属互连结构；蚀刻终止层，布置在半导体装置上方，其中蚀刻终止层包括介电材料；以及侧壁保护结构，包围半导体装置，其中侧壁保护结构的最上表面在蚀刻终止层上方，其中侧壁保护结构具有从蚀刻终止层的顶部表面到蚀刻终止层的底部表面直接地且连续地接触蚀刻终止层的外侧壁的内侧壁。
在一些实施例中，所述半导体装置是发光二极管装置或竖直腔表面发射激光器装置。
在一些实施例中，所述蚀刻终止层包括硅。
在一些实施例中，所述侧壁保护结构连续地并直接地接触所述半导体装置的所有外侧壁。
在一些实施例中，所述侧壁保护结构及所述蚀刻终止层包括相同介电材料。
前文概述若干实施例的特征以使得本领域的技术人员可更好地理解本发明的方面。本领域的技术人员应了解，其可很容易地将本发明用作设计或修改用于实现本文引入的实施例或实例的相同目的及/或达成相同优势的其它工艺和结构的基础。所属领域的技术人员还应认识到，此类等效构造并不脱离本发明的精神和范围，且其可在不脱离本发明的精神和范围的情况下在本文中进行各种改变、替代以及更改。

Claims (10)

1.一种形成封装组件的方法，其特征在于，包括：
在半导体衬底的前侧上方形成湿式蚀刻终止层；
在所述湿式蚀刻终止层上方形成牺牲半导体层；
在所述牺牲半导体层上方形成干式蚀刻终止层；
在所述干式蚀刻终止层上方形成半导体装置层的堆叠；
执行接合工艺以将所述半导体装置层的堆叠接合到集成电路管芯的前侧，其中所述半导体衬底的所述前侧面向所述集成电路管芯的所述前侧；
执行湿式蚀刻工艺以去除所述半导体衬底；以及
执行干式蚀刻工艺以去除所述湿式蚀刻终止层及所述牺牲半导体层。
2.根据权利要求1所述的方法，其中所述半导体衬底比所述牺牲半导体层更厚。
3.根据权利要求1所述的方法，进一步包括：
将所述半导体装置层的堆叠及所述干式蚀刻终止层图案化，以形成第一半导体装置及与所述第一半导体装置横向间隔开的第二半导体装置，其中在图案化之后，所述第一半导体装置及所述第二半导体装置由所述牺牲半导体层连接。
4.根据权利要求1所述的方法，其中所述干式蚀刻终止层在所述干式蚀刻工艺之后比在所述干式蚀刻工艺之前更薄。
5.根据权利要求1所述的方法，其中所述接合工艺包括：
在所述牺牲半导体层与所述集成电路管芯之间沉积底部填充材料。
6.根据权利要求1所述的方法，进一步包括：
在执行所述湿式蚀刻工艺之前，在所述半导体装置层的堆叠的外侧壁上形成侧壁保护结构。
7.一种形成封装组件的方法，其特征在于，包括：
在半导体衬底上方形成第一蚀刻终止层；
在所述第一蚀刻终止层上方形成牺牲半导体层，其中所述牺牲半导体层比所述半导体衬底更厚；
在所述牺牲半导体层上方形成第二蚀刻终止层；
在所述第二蚀刻终止层上方形成装置层的堆叠，其中所述装置层的堆叠的背侧接触所述第二蚀刻终止层；
将所述装置层的堆叠的前侧接合到集成电路管芯；
执行湿式蚀刻工艺以去除所述半导体衬底；以及
执行干式蚀刻工艺以去除所述第一蚀刻终止层及所述牺牲半导体层。
8.根据权利要求7所述的方法，其中所述第一蚀刻终止层包括不同于所述第二蚀刻终止层的材料。
9.根据权利要求7所述的方法，其中所述第一蚀刻终止层比所述第二蚀刻终止层更厚。
10.一种封装组件，其特征在于，包括：
集成电路管芯，包括衬底上方的金属互连结构；
半导体装置，布置在所述金属互连结构上方并电性耦接到所述金属互连结构；
蚀刻终止层，布置在所述半导体装置上方，其中所述蚀刻终止层包括介电材料；以及
侧壁保护结构，包围所述半导体装置，其中所述侧壁保护结构的最上部表面在所述蚀刻终止层上方，其中所述侧壁保护结构具有内侧壁，所述内侧壁从所述蚀刻终止层的顶部表面到所述蚀刻终止层的底部表面直接地并连续地接触所述蚀刻终止层的外侧壁。
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