CN112490126A - 晶体管及其制备方法 - Google Patents

晶体管及其制备方法 Download PDF

Info

Publication number
CN112490126A
CN112490126A CN201910866406.0A CN201910866406A CN112490126A CN 112490126 A CN112490126 A CN 112490126A CN 201910866406 A CN201910866406 A CN 201910866406A CN 112490126 A CN112490126 A CN 112490126A
Authority
CN
China
Prior art keywords
insulating layer
substrate
layer
transistor
inert gas
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201910866406.0A
Other languages
English (en)
Other versions
CN112490126B (zh
Inventor
李相遇
崔基雄
金成基
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xia Tai Xin Semiconductor Qing Dao Ltd
Original Assignee
Xia Tai Xin Semiconductor Qing Dao Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xia Tai Xin Semiconductor Qing Dao Ltd filed Critical Xia Tai Xin Semiconductor Qing Dao Ltd
Priority to CN201910866406.0A priority Critical patent/CN112490126B/zh
Publication of CN112490126A publication Critical patent/CN112490126A/zh
Application granted granted Critical
Publication of CN112490126B publication Critical patent/CN112490126B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/3115Doping the insulating layers
    • H01L21/31155Doping the insulating layers by ion implantation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31105Etching inorganic layers
    • H01L21/31111Etching inorganic layers by chemical means
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31105Etching inorganic layers
    • H01L21/31111Etching inorganic layers by chemical means
    • H01L21/31116Etching inorganic layers by chemical means by dry-etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

一种晶体管的制备方法,其包括如下步骤:提供一基板,并在所述基板上形成栅极结构;在所述基板上形成覆盖所述栅极结构的绝缘层,所述绝缘层的材质为氧化硅;对所述绝缘层进行惰性气体离子注入并对惰性离子注入后的绝缘层进行湿法蚀刻以去除部分的绝缘层;以及对所述绝缘层进行干法蚀刻以去除部分的绝缘层。本发明还提供上述方法制备得到的晶体管。所述晶体管的制备方法通过对湿法蚀刻前的绝缘层进行惰性气体离子注入,蚀刻后得到的绝缘层会具有均一的膜厚,进而提升晶体管的性能。

Description

晶体管及其制备方法
技术领域
本发明涉及一种晶体管及其制备方法。
背景技术
晶体管是半导体领域的一种应用十分广泛的元件。现有的一种晶体管的制备方法包括如下步骤:在基板上形成栅极,然后在基板上形成完全覆盖所述栅极的绝缘层;接着对绝缘层进行湿法蚀刻。绝缘层通常为无机氧化物材料,然而湿法蚀刻绝缘层的过程中,绝缘层的蚀刻速度较快,蚀刻后容易形成不均一的厚度,进而导致影响晶体管的性能,例如晶体管的阈值电压的均匀性降低。
发明内容
鉴于此,有必要提供一种晶体管的制备方法,其可有效解决上述问题。
一种晶体管的制备方法,其包括如下步骤:
提供一基板,并在所述基板上形成栅极结构;
在所述基板上形成覆盖所述栅极结构的绝缘层,所述绝缘层的材质为氧化硅;
对所述绝缘层进行惰性气体离子注入并对惰性离子注入后的绝缘层进行湿法蚀刻以去除部分的绝缘层;以及
对所述绝缘层进行干法蚀刻以去除部分的绝缘层。
本发明还提供上述制备方法制得的晶体管,其包括:
基板;
形成在所述基板上的栅极结构;以及
覆盖所述栅极结构的绝缘层,所述绝缘层的材质为氧化硅;
所述绝缘层经惰性气体离子注入并蚀刻形成。
本发明的晶体管的制备方法,通过对湿法蚀刻前的绝缘层进行惰性气体离子注入,可有效提升绝缘层对酸性蚀刻液的耐蚀刻性,即绝缘层蚀刻过程中蚀刻速度会相应放缓,如此湿法蚀刻后得到的绝缘层会具有均一的膜厚,进而提升晶体管的性能,例如保证晶体管的阈值电压的均匀性。
附图说明
图1是本发明的晶体管的制备方法流程图。
图2A-2C为晶体管的制备方法的示意图一。
图3为晶体管的剖面示意图。
主要元件符号说明
Figure BDA0002201398370000021
Figure BDA0002201398370000031
具体实施方式将结合上述附图进一步说明本发明。
具体实施方式
附图中示出了本发明的实施例,本发明可以通过多种不同形式实现,而并不应解释为仅局限于这里所阐述的实施例。相反,提供这些实施例是为了使本发明更为全面和完整的公开,并使本领域的技术人员更充分地了解本发明的范围。为了清晰可见,在图中,层和区域的尺寸被放大了。
除非另外定义,这里所使用的所有术语(包括技术和科学术语)具有与本发明所述领域的普通技术人员所通常理解的含义相同的含义。还应当理解,比如在通用的辞典中所定义的那些的术语,应解释为具有与它们在相关领域的环境中的含义相一致的含义,而不应以过度理想化或过度正式的含义来解释,除非在本文中明确地定义。
请参阅图1,一种半导体器件的制备方法。该半导体器件可为晶体管;且本实施例的制备方法中主要涉及动态随机存取存储器中的晶体管的制备。当然所述制备方法也可适用于其他的各种半导体装置的晶体管的制备。所述制备方法,其包括如下步骤。
步骤S1:如图2A所示,提供一基板10,并在基板10上形成栅极结构20。
该基板10可为硅基板。该基板10中形成多个间隔设置的沟槽隔离2。
本实施例中,该栅极结构20为多层结构,其包括依次层叠在所述基板10上的多晶硅层21、阻挡层22、金属导电层23、以及遮罩层24。该栅极结构20可采用常规的方式形成,例如涂覆、物理气相沉积(溅镀)、化学气相沉积等。所述多晶硅层21、阻挡层22、金属导电层23、以及遮罩层24需依次形成在所述基板10上。
该金属导电层23可为本领域常规的导电金属,例如金属钨。该阻挡层22设置在该多晶硅层21与金属导电层23之间,用以防止金属导电层23中的金属朝多晶硅层21扩散,其材质可为Ti、TiN或WN。本实施例中,该遮罩层24设置在该金属导电层23远离该基板10的一侧,该遮罩层24的材质可为绝缘材料,例如SiN。
该栅极结构20局部覆盖该基板10。该多晶硅层21、该阻挡层22、该金属导电层23、以及该遮罩层24具有相同的面积且小于所述基板10的面积。
如图2A所示,该栅极结构20与该基板10之间还设置有栅极氧化物层101。即,该栅极氧化物层101设置在该多晶硅层21与该基板10之间。该栅极氧化物层101也局部覆盖该基板10,该栅极氧化物层101在基板10上的垂直投影与所述栅极结构20在基板10上的垂直投影完全重叠。该栅极氧化物层101的材质可为氧化硅。制备时可在基板10上预先沉积栅极氧化物层101,再依次在栅极氧化物层101上沉积形成多晶硅层21、阻挡层22、金属导电层23、以及遮罩层24。
如图2A所示,该栅极结构20具有远离所述基板10的顶面201、以及连接所述顶面201和所述基板10的侧面203。本案中涉及的侧面203包括该栅极氧化物层101的侧面。
步骤S2:如图2B所示,在所述基板10上形成覆盖所述栅极结构20的绝缘层30,所述绝缘层30的材质为氧化硅。
如图2B所示,该绝缘层30完全覆盖所述栅极结构20的顶面201和侧面203且延伸覆盖到所述基板10上。
一实施例中,该绝缘层30的厚度为
Figure BDA0002201398370000052
本实施例中,如图2B所示,该栅极结构20的侧面203和该绝缘层30之间还有一厚度较薄的绝缘材料层40。即,在形成所述绝缘层30之间,所述方法还包括在所述绝缘层30的侧面203上形成绝缘材料层40的步骤。该绝缘材料层40的材质可与该遮罩层24具有相同的材料,例如SiN。
步骤S3:如图2C所示,对所述绝缘层30进行惰性气体离子注入,然后对惰性离子注入后的绝缘层30进行湿法蚀刻。
所述惰性气体离子注入采用氩气离子注入,即,以氩气作为注入离子源。氩气离子注入的具体工艺条件为:氩离子能量大于等于5keV且小于等于20keV,氩离子注入剂量小于1×1014cm-2,氩离子的平均投影射程为
Figure BDA0002201398370000051
注入绝缘层30的氩离子会导致氩离子周围的Si-O发生一定的变形,进而使所述绝缘层30中的Si-O键结合得更加稳定,进而提高所述绝缘层30的耐蚀刻性。
所述湿法蚀刻采用的蚀刻液包含氢氟酸和稀硫酸,即为氢氟酸和稀硫酸的混合物。湿法蚀刻将去除部分的绝缘层30。
一对比例中,采用上述蚀刻液蚀刻未经惰性气体离子注入的绝缘层30,180秒的时间内消耗的绝缘层30的厚度为
Figure BDA0002201398370000061
而采用上述蚀刻液蚀刻经氩离子注入的所述绝缘层30,180秒的时间内消耗的绝缘层30的厚度为
Figure BDA0002201398370000062
通过惰性气体离子注入所述绝缘层30,所述绝缘层30的耐蚀刻性显著提高。
步骤S4:对所述绝缘层30进行干法蚀刻。
干法蚀刻可采用蚀刻气体对湿法蚀刻后的绝缘层30进行蚀刻以去除部分的绝缘层30。如图3所示,经过湿法蚀刻和干法蚀刻后的绝缘层30仅覆盖所述栅极结构20的侧面203。
可以理解的,对所述绝缘层30进行干法蚀刻的步骤也可在步骤S3进行之前进行,即对所述绝缘层30先进行干法蚀刻,然后进行惰性离子注入和湿法蚀刻。
所述半导体器件的制备方法还包括在蚀刻后,对所述绝缘层30进行清洗的步骤;然后可以在所述绝缘层30上沉积形成其他的功能层的步骤。
上述半导体器件的的制备方法,通过对湿法蚀刻前的绝缘层30进行惰性气体离子注入,可有效提升绝缘层30对酸性蚀刻液的耐蚀刻性,即绝缘层30蚀刻过程中蚀刻速度会相应放缓,如此蚀刻后得到的绝缘层30表面形貌会更加平整,相对会具有更均匀的膜厚,进而提升晶体管的性能,例如保证晶体管的阈值电压的均匀性。
请参阅图3,由上述制备方法制得的晶体管,其包括基板10、形成在所述基板10上的栅极结构20、以及覆盖所述栅极结构20的绝缘层30。所述绝缘层30的材质为氧化硅。
该基板10可为硅基板。该栅极结构20局部覆盖该基板10。该栅极结构20具有远离所述基板10的顶面201、以及连接所述顶面201和所述基板10的侧面203。所述绝缘层30经惰性气体离子注入并蚀刻形成仅覆盖所述栅极结构20的侧面203。
本实施例中,该栅极结构20为多层结构,其包括依次层叠在所述基板10上的多晶硅层21、阻挡层22、金属导电层23、遮罩层24。该金属导电层23可为本领域常规的导电金属,例如金属钨。该阻挡层22设置在该多晶硅层21与该金属导电层23之间,用以防止金属导电层23中的金属朝多晶硅层21扩散,其材质可为Ti、TiN或WN。本实施例中,该遮罩层24设置在该金属导电层23远离该基板10的一侧,该遮罩层24的材质可为绝缘材料,例如SiN。该多晶硅层21、该阻挡层22、该金属导电层23、该遮罩层24具有相同的面积尺寸且小于所述基板10的面积尺寸。
如图3所示,该栅极结构20与该基板10之间还设置有栅极氧化物层101。即,该栅极氧化物层101设置在该多晶硅层21与该基板10之间。该栅极氧化物层101局部覆盖该基板10,该栅极氧化物层101在基板10上的垂直投影与所述栅极结构20在基板10上的垂直投影完全重叠。该栅极氧化物层101的材质可为氧化硅。
该栅极结构20的侧面203和该绝缘层30之间还有一厚度较薄的绝缘材料层40。该绝缘材料层40的材质可与该遮罩层24具有相同的材料,例如SiN。
以上实施例仅用以说明本发明的技术方案而非限制,图示中出现的上、下、左及右方向仅为了方便理解,尽管参照较佳实施例对本发明进行了详细说明,本领域的普通技术人员应当理解,可以对本发明的技术方案进行修改或等同替换,而不脱离本发明技术方案的精神和范围。

Claims (10)

1.一种晶体管的制备方法,其特征在于:其包括如下步骤:
提供一基板,并在所述基板上形成栅极结构;
在所述基板上形成覆盖所述栅极结构的绝缘层,所述绝缘层的材质为氧化硅;
对所述绝缘层进行惰性气体离子注入并对惰性离子注入后的绝缘层进行湿法蚀刻以去除部分的绝缘层;以及
对所述绝缘层进行干法蚀刻以去除部分的绝缘层。
2.如权利要求1所述的晶体管的制备方法,其特征在于:所述湿法蚀刻采用氢氟酸和稀硫酸的混合物。
3.如权利要求1所述的晶体管的制备方法,其特征在于:所述惰性气体离子注入采用氩气离子注入。
4.如权利要求3所述的晶体管的制备方法,其特征在于:氩气离子注入的具体工艺条件为:氩离子能量小于20keV,注入剂量小于1×1014cm-2
5.如权利要求1所述的晶体管的制备方法,其特征在于:所述栅极结构局部覆盖该基板;所述栅极结构具有远离所述基板的顶面、以及连接所述顶面和所述基板的侧面;对所述绝缘层进行湿法蚀刻和干法蚀刻的目的是去除该绝缘层除覆盖所述栅极结构的侧面以外的部分。
6.如权利要求1所述的晶体管的制备方法,其特征在于:所述栅极结构包括依次层叠在所述基板上的多晶硅层、阻挡层、金属导电层和遮罩层。
7.如权利要求1所述的晶体管的制备方法,其特征在于:对所述绝缘层进行干法蚀刻的步骤为在对所述绝缘层进行惰性气体离子注入和湿法蚀刻的步骤之前或之后进行。
8.一种晶体管,其包括:
基板;
形成在所述基板上的栅极结构;以及
覆盖所述栅极结构的绝缘层,所述绝缘层的材质为氧化硅;
其特征在于:所述绝缘层经惰性气体离子注入并蚀刻形成。
9.如权利要求8所述的晶体管,其特征在于:所述栅极结构局部覆盖该基板;所述栅极结构具有远离所述基板的顶面、以及连接所述顶面和所述基板的侧面;所述绝缘层仅覆盖所述栅极结构的侧面。
10.如权利要求8所述的晶体管,其特征在于:所述栅极结构包括依次层叠在所述基板上的多晶硅层、阻挡层、金属导电层和遮罩层。
CN201910866406.0A 2019-09-12 2019-09-12 晶体管及其制备方法 Active CN112490126B (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201910866406.0A CN112490126B (zh) 2019-09-12 2019-09-12 晶体管及其制备方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201910866406.0A CN112490126B (zh) 2019-09-12 2019-09-12 晶体管及其制备方法

Publications (2)

Publication Number Publication Date
CN112490126A true CN112490126A (zh) 2021-03-12
CN112490126B CN112490126B (zh) 2023-03-31

Family

ID=74920906

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910866406.0A Active CN112490126B (zh) 2019-09-12 2019-09-12 晶体管及其制备方法

Country Status (1)

Country Link
CN (1) CN112490126B (zh)

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1140538A (ja) * 1997-07-15 1999-02-12 Sony Corp 半導体装置の製造方法
US6350696B1 (en) * 2000-09-28 2002-02-26 Advanced Micro Devices, Inc. Spacer etch method for semiconductor device
JP2008047691A (ja) * 2006-08-16 2008-02-28 Yamaha Corp 半導体装置の製法
US20110012209A1 (en) * 2009-07-14 2011-01-20 Ching-Hung Kao Gate structure and method of making the same
CN102082124A (zh) * 2009-12-01 2011-06-01 无锡华润上华半导体有限公司 多种器件集成工艺中栅极间隙壁的制造方法
US20120244658A1 (en) * 2011-03-23 2012-09-27 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
US20140187046A1 (en) * 2012-12-28 2014-07-03 Commissariat A L'energie Atomique Et Aux Ene Alt Method for forming spacers for a transitor gate
CN104979292A (zh) * 2015-05-15 2015-10-14 上海华力微电子有限公司 一种形成不同侧墙结构的方法
CN109244142A (zh) * 2018-09-29 2019-01-18 深圳市南硕明泰科技有限公司 一种ldmos及其制造方法

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1140538A (ja) * 1997-07-15 1999-02-12 Sony Corp 半導体装置の製造方法
US6350696B1 (en) * 2000-09-28 2002-02-26 Advanced Micro Devices, Inc. Spacer etch method for semiconductor device
JP2008047691A (ja) * 2006-08-16 2008-02-28 Yamaha Corp 半導体装置の製法
US20110012209A1 (en) * 2009-07-14 2011-01-20 Ching-Hung Kao Gate structure and method of making the same
CN102082124A (zh) * 2009-12-01 2011-06-01 无锡华润上华半导体有限公司 多种器件集成工艺中栅极间隙壁的制造方法
US20120244658A1 (en) * 2011-03-23 2012-09-27 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
US20140187046A1 (en) * 2012-12-28 2014-07-03 Commissariat A L'energie Atomique Et Aux Ene Alt Method for forming spacers for a transitor gate
CN104979292A (zh) * 2015-05-15 2015-10-14 上海华力微电子有限公司 一种形成不同侧墙结构的方法
CN109244142A (zh) * 2018-09-29 2019-01-18 深圳市南硕明泰科技有限公司 一种ldmos及其制造方法

Also Published As

Publication number Publication date
CN112490126B (zh) 2023-03-31

Similar Documents

Publication Publication Date Title
TW200411933A (en) Enhanced T-gate structure for modulation doped field effect transistors
TW202013510A (zh) 鰭狀場效電晶體的製作方法
US5899741A (en) Method of manufacturing low resistance and low junction leakage contact
TW201814832A (zh) 半導體裝置之形成方法
CN117198997A (zh) 半导体结构的制作方法以及半导体结构
US8350311B2 (en) Semiconductor device
TWI360225B (en) Low-power multiple-channel fully depleted quantum
KR101937512B1 (ko) 반도체 장치 및 이의 제조방법
CN112490126B (zh) 晶体管及其制备方法
US20150102400A1 (en) Ion implantation-assisted etch-back process for improving spacer shape and spacer width control
US4505024A (en) Method of manufacturing semiconductor device, including a step of patterning a conductor layer
US11735476B2 (en) Semiconductor structure and fabrication method thereof
CN112366179A (zh) 半导体器件结构和制备方法
CN109994479A (zh) 一次性可编程器件的制造方法及一次性可编程器件
CN103107075B (zh) 金属栅极的形成方法
TWI443744B (zh) 具有經改善絕緣特性之介電層之製造方法及具有經改善絕緣特性之介電層之半導體結構之製造方法
CN108962742B (zh) 半导体结构的制造方法
JP2009259996A (ja) 半導体装置およびその製造方法
KR20050116432A (ko) 박막 커패시터의 제조 방법
CN108417526B (zh) 一种半导体器件的制造方法
TWI431721B (zh) 降低接觸孔電阻之半導體元件製造方法
CN109346409B (zh) 半导体器件与其制作方法
KR100633988B1 (ko) 반도체 소자 및 그 제조 방법
CN108346698A (zh) 一种半导体器件的制造方法
KR101973269B1 (ko) 산화물 반도체 박막 트랜지스터 및 이의 제조방법

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant