CN112466927B - Heterojunction semiconductor device with avalanche shock resistance - Google Patents
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- CN112466927B CN112466927B CN202011351448.XA CN202011351448A CN112466927B CN 112466927 B CN112466927 B CN 112466927B CN 202011351448 A CN202011351448 A CN 202011351448A CN 112466927 B CN112466927 B CN 112466927B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 156
- 230000035939 shock Effects 0.000 title description 3
- 229910052751 metal Inorganic materials 0.000 claims abstract description 51
- 239000002184 metal Substances 0.000 claims abstract description 51
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000002161 passivation Methods 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 description 9
- 229910002601 GaN Inorganic materials 0.000 description 6
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 6
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 230000001939 inductive effect Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 229910021478 group 5 element Inorganic materials 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a heterojunction semiconductor device resisting impact by avalanche, which comprises a substrate (1) and a second dielectric layer (23), wherein a first dielectric layer (21) is arranged on the substrate (1), a first semiconductor layer (24) is arranged on the second dielectric layer (23), a second semiconductor layer (3) is arranged on the first semiconductor layer (24), the first semiconductor layer (24) is in contact with the second semiconductor layer (3) to form a conductive channel layer (25), a metal source electrode (7), a metal gate electrode (8) and a metal drain electrode (9) are arranged on the second semiconductor layer (3), and a third dielectric layer (10) is arranged between the second semiconductor layer (3) and the metal gate electrode (8), and the heterojunction semiconductor device is characterized in that an avalanche layer is arranged between the first dielectric layer (21) and the second dielectric layer (23), and is respectively connected with the metal source electrode (7) and the metal drain electrode (9), The metal drain electrode (9) is connected. The device has avalanche capability and high surge robustness.
Description
Technical Field
The invention mainly relates to the field of high-voltage power semiconductor devices, in particular to a heterojunction semiconductor device resisting impact by avalanche.
Background
Wide bandgap semiconductors, which are third-generation semiconductors, have become hot research in the semiconductor field, and have the characteristics of large bandgap width, high breakdown electric field strength, high electron saturation drift rate, good thermal conductivity, strong radiation resistance, and the like, compared with first-generation and second-generation semiconductors. The peak voltage which can be borne by the wide-bandgap semiconductor device is greatly improved due to the larger bandgap and the high breakdown electric field intensity; the high electron saturation drift rate enables the device to withstand higher frequencies; the high thermal conductivity and good thermal stability enable the device to bear higher temperature, the device is suitable for severe working environment, and the stability and reliability of the device and the system are improved.
Gallium nitride is a representative wide bandgap semiconductor material among others. The gallium nitride-based device comprises a heterojunction formed by growing two semiconductor materials with different forbidden band widths together, such as a gallium nitride high electron mobility transistor, wherein the gallium nitride material and an aluminum gallium nitrogen material are contacted to form a gallium nitride/aluminum gallium nitrogen heterojunction, electrons flow from one side of the wide forbidden band semiconductor to the narrow forbidden band semiconductor, so that a quantum well is formed on one side of a contact surface close to the narrow forbidden band semiconductor, and the movement of the electrons is limited in a two-dimensional plane, so that the electron mobility is high. Meanwhile, the gallium nitride high electron mobility transistor has the advantages of high power density and the like, and is very suitable for manufacturing high-power, high-efficiency and high-frequency devices.
However, the conventional heterojunction semiconductor device does not have avalanche capability, cannot bear the impact of surge current, does not have surge robustness, and is extremely easy to burn, so that the conventional heterojunction semiconductor device needs to be improved.
Disclosure of Invention
The present invention is directed to solving the above problems, and provides an avalanche surge-resistant heterojunction semiconductor device with self-protection capability.
The invention adopts the following technical scheme:
a heterojunction semiconductor device that is impact resistant with avalanche, comprising: the semiconductor device comprises a substrate and a second dielectric layer, wherein a first dielectric layer is arranged on the substrate, a first semiconductor layer is arranged on the second dielectric layer, a second semiconductor layer is arranged on the first semiconductor layer, the first semiconductor layer is in contact with the second semiconductor layer to form a conductive channel layer, a metal source electrode, a metal gate electrode and a metal drain electrode are arranged on the second semiconductor layer, a third dielectric layer is arranged between the second semiconductor layer and the metal gate electrode, an avalanche layer is arranged between the first dielectric layer and the second dielectric layer, and the avalanche layer is respectively connected with the metal source electrode and the metal drain electrode.
Compared with the prior art, the invention has the following advantages:
(1) the p-type wavy semiconductor strips and the n-type wavy semiconductor strips of the device are distributed in a staggered manner in the horizontal plane transverse direction and the extending direction, namely the p-type wavy semiconductor strips are directly adjacent to the n-type wavy semiconductor strips in contact, and the top view section of the p-type wavy semiconductor strips is shown in figure 5; and, a source connection region is added under the source to connect the source metal to the p-type corrugated semiconductor strips, and a drain connection region is added under the drain to connect the drain metal to the n-type corrugated semiconductor strips. When the device is externally connected with an inductive load and is switched off from the on state, the current in the inductive load cannot be instantly reduced to zero, so that surge current impacts the device, the surge current flows through the device to generate higher impact voltage on the device, the potential of the drain electrode is higher than that of the source electrode, the potential of the corresponding n-type wavy semiconductor strip connected with the drain electrode is higher than that of the p-type wavy semiconductor strip connected with the source electrode, so that the reverse bias of a pn junction formed by the contact of the p-type wavy semiconductor strip and the n-type wavy semiconductor strip is caused, and when the reverse bias voltage of the pn junction is increased to a certain value, the avalanche phenomenon of the pn junction starts to occur. The pn junction avalanche process dissipates energy, so that the impulse voltage does not continuously rise and is clamped to a fixed value, namely the high impulse voltage in the traditional device is reduced to the lower avalanche voltage in the device, so that the device is protected and is not easy to burn, and the surge robustness of the device is further improved. When the semiconductor device is conducted in the forward direction, the forward voltage is low, the pn junction cannot be started, and the p-type wavy semiconductor strips and the n-type wavy semiconductor strips which are distributed in a staggered mode cannot affect the normal switching of the device.
(2) The p-type wave-shaped semiconductor strips and the n-type wave-shaped semiconductor strips of the device are distributed in a staggered mode to form an array, so that an avalanche region is enlarged, and the dissipation efficiency of surge energy is improved.
(3) According to the semiconductor device, the source electrode is directly connected with the p-type wavy semiconductor strip through the source electrode connecting area, the drain electrode is directly connected with the n-type wavy semiconductor strip through the drain electrode connecting area, and meanwhile, in order to prevent the first semiconductor layer from being influenced by the connecting area and further influence the work of the device, the connecting area and the first semiconductor layer are isolated through the first passivation layer, so that the stability of the device is further improved.
(4) The first semiconductor layer of the device of the invention has high resistance, and the first dielectric layer and the second dielectric layer ensure the high resistance of the first semiconductor layer, thereby further reducing the leakage current of the first semiconductor layer.
(5) Compared with an externally integrated device, the device reduces external metal interconnection and can reduce the parasitic characteristic of the device.
(6) The implementation mode of the device is to improve the prior art on the basis of analyzing the prior device, is compatible with the prior art and reduces the manufacturing cost.
Drawings
Fig. 1 is a perspective view of a conventional heterojunction semiconductor device structure.
Fig. 2 is a perspective view of a structure of a heterojunction semiconductor device with avalanche shock resistance according to the present invention.
Fig. 3 is a partial structural perspective view of a heterojunction semiconductor device with avalanche surge resistance proposed by the present invention.
Fig. 4 is a front cross-sectional view of a heterojunction semiconductor device with avalanche surge resistance as proposed by the present invention.
Fig. 5 is a top cross-sectional view of a p-type waved semiconductor strip and an n-type waved semiconductor strip interleaved with a device of the present invention.
Fig. 6 is a graph of the operating voltage of the device of the present invention versus a conventional heterojunction semiconductor device, from which it can be seen that the device of the present invention clamps the high surge voltage to a lower avalanche voltage, indicating that the device of the present invention has avalanche capability, improving the surge robustness of the device.
Fig. 7 is a perspective view of a structure of a first step in the specific fabrication of a device of the present invention.
Fig. 8 is a perspective view of a second step in the specific fabrication of a device of the present invention.
Fig. 9 is a perspective view of a third step in the detailed fabrication of a device of the present invention.
FIG. 10 is a perspective view of a fourth step in the fabrication of a device according to the present invention.
FIG. 11 is a perspective view of a fifth step in the detailed fabrication of a device of the present invention.
FIG. 12 is a perspective view of a sixth step in the specific fabrication of a device of the present invention.
Fig. 13 and 14 are perspective views showing the structure of the seventh step of the device of the present invention.
FIG. 15 is a perspective view of the eighth step in the detailed fabrication of the device of the present invention.
Detailed Description
A heterojunction semiconductor device that is impact resistant with avalanche, comprising: the semiconductor device comprises a substrate 1 and a second dielectric layer 23, wherein a first dielectric layer 21 is arranged on the substrate 1, a first semiconductor layer 24 is arranged on the second dielectric layer 23, a second semiconductor layer 3 is arranged on the first semiconductor layer 24, the first semiconductor layer 24 is in contact with the second semiconductor layer 3 to form a conductive channel layer 25, a metal source electrode 7, a metal gate electrode 8 and a metal drain electrode 9 are arranged on the second semiconductor layer 3, and a third dielectric layer 10 is arranged between the second semiconductor layer 3 and the metal gate electrode 8, and is characterized in that an avalanche layer is arranged between the first dielectric layer 21 and the second dielectric layer 23 and is respectively connected with the metal source electrode 7 and the metal drain electrode 9. In the present embodiment, it is preferred that,
the avalanche layer is composed of p-type waved semiconductor strips 221 connected to the source metal 7 and n-type waved semiconductor strips 222 connected to the drain metal 9 which are fitted to each other, and the p-type waved semiconductor strips 221 and the n-type waved semiconductor strips 222 are arranged at intervals from each other.
A p-type semiconductor body 223 connected to the source metal 7 is filled in the recess of the n-type wavy semiconductor stripe 222 located on the boundary of the avalanche layer, and an n-type semiconductor body 224 connected to the drain metal 9 is filled in the recess of the p-type wavy semiconductor stripe 221 located on the boundary of the avalanche layer; the p-type semiconductor body 223 and the n-type semiconductor body 224 may be floating.
The p-type wavy semiconductor strip 221 is connected with the source metal 7 through a source connection region 5, the n-type wavy semiconductor strip 222 is connected with the drain metal 9 through a drain connection region 6, and the first passivation layer 4 is respectively wrapped on the source connection region 5 and the drain connection region 6.
The invention is described in detail below with reference to the accompanying drawings.
Referring to fig. 2, a avalanche surge resistant heterojunction semiconductor device structure, comprising: a substrate, a first medium layer is arranged on the substrate, a p-type wave-shaped semiconductor strip and an n-type wave-shaped semiconductor strip are arranged on the first medium layer, the p-type wave-shaped semiconductor strip and the n-type wave-shaped semiconductor strip are distributed in a staggered manner in the horizontal plane transverse direction and the extending direction, namely the p-type wave-shaped semiconductor strip is directly adjacent to the n-type wave-shaped semiconductor strip, the p-type wave-shaped semiconductor strip is diagonally adjacent to the p-type wave-shaped semiconductor strip, a second medium layer is arranged on the p-type wave-shaped semiconductor strip and the n-type wave-shaped semiconductor strip, a first semiconductor layer is arranged on the second medium layer, a second semiconductor layer is arranged on the first semiconductor layer, the first semiconductor layer is contacted with the second semiconductor layer to form a conductive channel layer, a metal source electrode, a metal drain electrode and a third medium layer are arranged on the second semiconductor layer, and a source electrode connecting area and a drain electrode connecting area are respectively arranged below the metal source electrode and the metal drain electrode, and the side walls of the source electrode connecting area and the drain electrode connecting area are provided with first passivation layers, source electrode metal is directly contacted with the p-type wavy semiconductor strip through the source electrode connecting area, drain electrode metal is directly contacted with the n-type wavy semiconductor strip through the drain electrode connecting area, and a metal gate electrode is arranged on the third dielectric layer.
The voltage curve of the device is shown in fig. 6, and the p-type wavy semiconductor strips and the n-type wavy semiconductor strips which are distributed in a staggered mode clamp a higher impact voltage to a lower avalanche voltage, so that the device is protected.
The invention adopts the following method to prepare:
in a first step, referring to fig. 7, a first dielectric layer 21 is grown on the surface of the substrate 1.
Secondly, referring to fig. 8, a first semiconductor layer 24 is grown on the surface of the first dielectric layer 21, a p-type waved semiconductor strip 221 and an n-type waved semiconductor strip 222 are formed in different areas of the upper surface of the first semiconductor layer 24 by ion implantation of a group v element and a group iii element, the p-type waved semiconductor strip 221 and the n-type waved semiconductor strip 222 are in direct adjacent contact, the p-type waved semiconductor strip 221 and the p-type waved semiconductor strip 221 are diagonally adjacent, that is, the p-type waved semiconductor strip 221 and the n-type waved semiconductor strip 222 are distributed in a staggered manner in the horizontal plane, in the horizontal direction and in the extending direction.
Third, referring to fig. 9, a second dielectric layer 23 is grown on the surfaces of the p-type corrugated semiconductor strip 221 and the n-type corrugated semiconductor strip 222.
Fourth, referring to fig. 10, a first semiconductor layer 24 is grown on the second dielectric layer 23.
In a fifth step, referring to fig. 11, the second semiconductor layer 3 is grown on the first semiconductor layer 24, and the first semiconductor layer 24 and the second semiconductor layer 3 are contacted to form the conductive channel layer 25.
Sixthly, referring to fig. 12, grooves are engraved above the p-type waved semiconductor strips 221 and the n-type waved semiconductor strips 222 at predetermined positions, and the first passivation layer 4 is deposited in the grooves.
Seventhly, referring to fig. 13 and 14, the first passivation layer 4 is etched, and then metal is deposited to form a source connection region 5 and a drain connection region 6, and a source electrode 7 and a drain electrode 9 are respectively led out on the source connection region 5 and the drain connection region 6.
Eighthly, referring to fig. 15, a groove is formed at a predetermined position on the second semiconductor layer 3 and a third dielectric layer 10 is deposited, and then a metal is deposited in the groove in the third dielectric layer 10 to form a metal gate electrode 8.
Claims (4)
1. A heterojunction semiconductor device that is impact resistant with avalanche, comprising: the semiconductor device comprises a substrate (1) and a second medium layer (23), wherein a first medium layer (21) is arranged on the substrate (1), a first semiconductor layer (24) is arranged on the second medium layer (23), a second semiconductor layer (3) is arranged on the first semiconductor layer (24), the first semiconductor layer (24) is in contact with the second semiconductor layer (3) to form a conductive channel layer (25), a metal source electrode (7), a metal gate electrode (8) and a metal drain electrode (9) are arranged on the second semiconductor layer (3), and a third medium layer (10) is arranged between the second semiconductor layer (3) and the metal gate electrode (8), and is characterized in that a wave-shaped semiconductor strip (221) which is mutually embedded and connected with the source metal (7) and an n-shaped semiconductor strip connected with the drain metal (9) are arranged between the first medium layer (21) and the second medium layer (23) and are respectively connected with the metal source electrode (7) and the metal drain electrode (9), and the wave-shaped semiconductor strip comprises a p-shaped semiconductor strip (221) which is mutually embedded and connected with the source metal (7) and an n-shaped semiconductor strip connected with the drain electrode (9) The waved semiconductor strips (222), and the p-type waved semiconductor strips (221) and the n-type waved semiconductor strips (222) are alternately arranged with each other.
2. The avalanche surge resistant heterojunction semiconductor device according to claim 1, wherein the p-type semiconductor body (223) connected to the source metal (7) is filled in the recess of the n-type wavelike semiconductor strip located on the boundary of the avalanche layer, and the n-type semiconductor body (224) connected to the drain metal (9) is filled in the recess of the p-type wavelike semiconductor strip located on the boundary of the avalanche layer.
3. The avalanche strike resistant heterojunction semiconductor device according to claim 2, wherein the p-type semiconductor body (223) and the n-type semiconductor body (224) are floating.
4. A semiconductor device with avalanche surge protection according to claim 1 or 2, characterized in that the p-type undulating semiconductor strip (221) is connected to the source metal (7) via a source connection region (5), the n-type undulating semiconductor strip (222) is connected to the drain metal (9) via a drain connection region (6), and the first passivation layer (4) is respectively wrapped around the source connection region (5) and the drain connection region (6).
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| Application Number | Priority Date | Filing Date | Title |
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| CN202011351448.XA CN112466927B (en) | 2020-11-26 | 2020-11-26 | Heterojunction semiconductor device with avalanche shock resistance |
| PCT/CN2021/072831 WO2022110523A1 (en) | 2020-11-26 | 2021-01-20 | Avalanche impact-resistant heterojunction semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202011351448.XA CN112466927B (en) | 2020-11-26 | 2020-11-26 | Heterojunction semiconductor device with avalanche shock resistance |
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| CN112466927A CN112466927A (en) | 2021-03-09 |
| CN112466927B true CN112466927B (en) | 2021-11-02 |
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| CN104821340A (en) * | 2014-02-05 | 2015-08-05 | 瑞萨电子株式会社 | Semiconductor device |
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| TWI695418B (en) * | 2017-09-22 | 2020-06-01 | 新唐科技股份有限公司 | Semiconductor device and method of manufacturing the same |
| CN110047910B (en) * | 2019-03-27 | 2020-07-31 | 东南大学 | Heterojunction semiconductor device with high voltage endurance capability |
| CN111969047B (en) * | 2020-08-27 | 2022-05-24 | 电子科技大学 | Gallium nitride heterojunction field effect transistor with composite back barrier layer |
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