CN112271218A - Power semiconductor device and preparation method thereof - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 44
- 238000002360 preparation method Methods 0.000 title description 3
- 238000000034 method Methods 0.000 claims abstract description 24
- 230000007704 transition Effects 0.000 claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 claims abstract description 16
- 239000010410 layer Substances 0.000 claims description 183
- 229910052751 metal Inorganic materials 0.000 claims description 51
- 239000002184 metal Substances 0.000 claims description 51
- 239000000758 substrate Substances 0.000 claims description 30
- 150000002500 ions Chemical class 0.000 claims description 29
- 238000005468 ion implantation Methods 0.000 claims description 21
- 229920002120 photoresistant polymer Polymers 0.000 claims description 15
- 239000011229 interlayer Substances 0.000 claims description 14
- 238000002347 injection Methods 0.000 claims description 12
- 239000007924 injection Substances 0.000 claims description 12
- 238000009413 insulation Methods 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims description 3
- 238000012545 processing Methods 0.000 claims description 2
- 230000015556 catabolic process Effects 0.000 abstract description 14
- 230000003071 parasitic effect Effects 0.000 abstract description 14
- 230000001965 increasing effect Effects 0.000 abstract description 9
- 230000017525 heat dissipation Effects 0.000 abstract description 6
- 230000020169 heat generation Effects 0.000 abstract description 2
- 230000008569 process Effects 0.000 description 7
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 7
- 229910010271 silicon carbide Inorganic materials 0.000 description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 230000001939 inductive effect Effects 0.000 description 4
- 238000004088 simulation Methods 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 238000004904 shortening Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000000137 annealing Methods 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- FFBHFFJDDLITSX-UHFFFAOYSA-N benzyl N-[2-hydroxy-4-(3-oxomorpholin-4-yl)phenyl]carbamate Chemical compound OC1=C(NC(=O)OCC2=CC=CC=C2)C=CC(=C1)N1CCOCC1=O FFBHFFJDDLITSX-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- 230000008719 thickening Effects 0.000 description 1
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0626—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a localised breakdown region, e.g. built-in avalanching region
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78642—Vertical transistors
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
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Abstract
The present disclosure provides a power semiconductor device and a method for manufacturing the same, the power semiconductor device includes an active region, a termination region and a transition region, wherein the active region and the termination region are arranged on an epitaxial layer; the active region comprises a plurality of second conductive type well regions arranged in the surface of the epitaxial layer at intervals, a groove arranged in the surface of the well region, a first conductive type source region positioned in the surface of the well region and positioned at two sides of the groove, and a second conductive type short-circuit region positioned in the well region and positioned below the groove; and a concave structure is arranged at the bottom of the well region at the corresponding position of the groove. The concave structure is formed at the bottom of the well region at the corresponding position of the groove, so that the avalanche breakdown position is transferred from the terminal region to the active region with a larger area, the heat dissipation area is increased, the avalanche current path avoids the parasitic npn transistor base region, the avalanche current path is shortened, the heat generation is reduced, and the avalanche tolerance is improved.
Description
Technical Field
The disclosure relates to the technical field of semiconductor devices, in particular to a power semiconductor device and a preparation method thereof.
Background
In a power Semiconductor device, such as a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), in a switching application, an inductive load and a parasitic inductor are not clamped intentionally or unintentionally, when the power device is turned off from an on state to an instant, energy stored in the inductor when a loop is turned on must be completely released by the power device at the turn-off instant, due to abrupt change of a drain current of the MOSFET, a large induced electromotive force generated by the inductor is superimposed on a power supply voltage, so that the power device is subjected to a large voltage, is in an avalanche state and flows a large current, and a large power loss is caused.
Switching processes under Unclamped Inductive Switching (UIS) are generally considered to be the most extreme electrical stress situations that power devices can encounter in system applications. In practical application, it is often necessary to design a complicated suppression and overvoltage protection circuit, resulting in an increase in system cost. Generally, it is desirable that the device have some inductive energy tolerance. The avalanche robustness of a power device is evaluated in terms of avalanche energy that can be dissipated in the device without causing catastrophic destruction.
There are two main failure modes of a MOSFET device during Switching under an Unclamped Inductive Switching (UIS): one is a parasitic Bipolar Junction Transistor (BJT) conduction breakdown of the power MOSFET, and the other is thermal breakdown. The parasitic BJT is conducted and damaged, namely when a large reverse current flows through a device base region, the temperature of the base region is increased, the resistance of the base region is in a positive temperature characteristic, so that the voltage drop of the base region is increased, and if the voltage drop is increased to be close to the self-built potential between the base region and an emitter of the parasitic BJT, the parasitic BJT is started. The turned-on BJT can further amplify the large current flowing through the base region, so that the junction temperature is raised, a positive feedback is formed, and finally the device is overheated and fails. This would lead to catastrophic thermal runaway for Si p-n junctions with forward voltages around 0.7. The forward voltage of the SiC p-n junction has a higher value (2-3V) and is less temperature dependent. During avalanche, the device may fail due to inherent thermal limitations. This limit is reached when the number of thermally generated carriers is equal to the background doping concentration. Theoretically, SiC has a much higher intrinsic thermal limit than Si because SiC has a lower intrinsic carrier concentration and a wider band gap. Therefore, SiC MOSFETs should have higher thermal stability than Si devices. However, SiC MOSFETs have a higher current density than Si MOSFETs, which can counteract the thermal effects of the material. Thus, the junction temperature of a weak portion of the device will overheat and fail when it rises to the maximum value allowed by the device material.
The conventional power semiconductor device is shown in fig. 1, and includes a substrate 101, an epitaxial layer 102, a drain metal layer 103, an active region 110, a transition region 120, and a terminal region 130, wherein the active region 110 includes a well region 111, a source region 112, a short-circuit region 113, a gate insulating layer 114, a gate 115, an interlayer dielectric layer 116, and a first source metal layer 117, the transition region 120 includes a doped region 121, a second source metal layer 122, and an interlayer dielectric layer 123, and the terminal region 130 includes a field limiting ring 131 and an interlayer dielectric layer 132. As shown in fig. 2, when the avalanche breakdown point of the device is in the termination region, since the potential of the termination region is floating and is not led out through the electrode, the avalanche breakdown current must flow a long distance from the breakdown point to reach the source, which causes a local over-high temperature in the termination region, which is not favorable for improving the avalanche resistance of the device. As shown in fig. 3, when the breakdown point is at the active region, the avalanche current is discharged through the source contact of the active region, and the current discharge path is wide; however, when an avalanche current flows through the active region, the avalanche current may flow through the base region of the parasitic npn transistor, which may turn on the parasitic npn transistor, and the current leakage path is long, which also affects the avalanche tolerance of the device.
Disclosure of Invention
In order to solve the problems, the disclosure provides a power semiconductor device and a manufacturing method thereof, and solves the technical problems that in the prior art, an avalanche current bleeder circuit of the power semiconductor device flows through a base region of a parasitic npn transistor, and the avalanche tolerance of the device is affected due to a long path.
In a first aspect, the present disclosure provides a power semiconductor device, including a first conductivity type substrate and a first conductivity type epitaxial layer located over the substrate, and an active region, a termination region and a transition region located between the active region and the termination region, which are disposed on the epitaxial layer;
the active region comprises a plurality of grooves arranged in the surface of the epitaxial layer at intervals, a plurality of second conductive type well regions arranged in the surface of the epitaxial layer at intervals and surrounding the grooves respectively, a first conductive type source region arranged in the surface of the well region and arranged at two sides of the grooves, a second conductive type short-circuit region arranged in the well region and arranged below the grooves, a gate structure arranged between two adjacent well regions and in contact with the well region and the source region, and a first source metal layer arranged above the gate structure and in the grooves and simultaneously in ohmic contact with the source region and the short-circuit region;
and the bottom of the well region is provided with a concave structure at a position corresponding to the groove, and the gate structure is isolated from the first source electrode metal layer through an interlayer dielectric layer.
According to an embodiment of the present disclosure, preferably, the depth of the trench is 0.2 to 0.5 μm.
According to the embodiment of the present disclosure, preferably, the gate structure includes a gate insulating layer located above the epitaxial layer and simultaneously in contact with the source region, the well region and the surface of the epitaxial layer, and a gate located above the gate insulating layer.
According to the embodiment of the present disclosure, preferably, the transition region includes a second conductive type doped region disposed in the surface of the epitaxial layer and a second source metal layer located above the doped region and forming an ohmic contact with the doped region;
wherein the second source metal layer is in contact with the first source metal layer.
According to the embodiment of the present disclosure, preferably, the termination region includes a plurality of field limiting rings of the second conductivity type disposed at intervals in the surface of the epitaxial layer.
According to the embodiment of the present disclosure, preferably, the method further includes:
and the drain metal layer is positioned below the substrate and is electrically connected with the substrate.
In a second aspect, the present disclosure provides a method for manufacturing a power semiconductor device, including:
providing a first conductive type substrate;
forming a first conductive type epitaxial layer over the substrate;
forming a plurality of grooves arranged at intervals in the surface of the epitaxial layer;
forming a plurality of second conductivity type well regions which are arranged at intervals and respectively surround the groove in the surface of the epitaxial layer so as to form an active region, and forming a terminal region and a transition region between the active region and the terminal region in the region where the well region is not formed in the surface of the epitaxial layer; a concave structure is arranged at the bottom of the well region at the corresponding position of the groove;
forming first conductive type source regions on two sides of the groove in the surface of the well region;
forming a second conductive type short-circuit region below the trench in the well region;
forming a gate structure which is in contact with the well region and the source region between two adjacent well regions;
forming a first source metal layer over the gate structure and in the trench while forming ohmic contacts with the source region and the shorting region; and the gate structure is isolated from the first source electrode metal layer through an interlayer dielectric layer.
According to the embodiment of the present disclosure, preferably, a plurality of second conductivity type well regions disposed at intervals and respectively surrounding the trench are formed in the surface of the epitaxial layer to form an active region, and a termination region and a transition region between the active region and the termination region are formed in a region where the well region is not formed in the surface of the epitaxial layer, including the following steps:
forming a photoresist mask layer above the epitaxial layer, and performing patterning processing on the photoresist mask layer to form a first ion implantation window at a corresponding position of the trench on the photoresist mask layer, and forming a second ion implantation window and a third ion implantation window in a region where the first ion implantation window is not formed on the photoresist mask layer;
injecting second conductive type high-energy ions into the surface of the epitaxial layer through the first ion injection window, the second ion injection window and the third ion injection window so as to form a second conductive type well region, a second conductive type doping region and a second conductive type field limiting ring at the corresponding positions of the first ion injection window, the second ion injection window and the third ion injection window in the surface of the epitaxial layer respectively, thereby forming an active region, a transition region and a terminal region respectively;
wherein the well region surrounds the trench.
According to the embodiment of the present disclosure, preferably, a gate structure in contact with the well region and the source region is formed between two adjacent well regions, including the following steps:
forming a grid insulation layer which is simultaneously contacted with the source region, the well region and the surface of the epitaxial layer above the epitaxial layer and between two adjacent well regions;
a gate is formed over the gate insulation layer.
According to the embodiment of the present disclosure, preferably, forming a first source metal layer over the gate structure and in the trench while forming ohmic contacts with the source region and the short-circuiting region includes:
and forming a first source metal layer which is simultaneously in ohmic contact with the source region and the short-circuit region above the gate structure and in the groove, and forming a second source metal layer which is in ohmic contact with the doped region above the doped region.
By adopting the technical scheme, the following technical effects can be at least achieved:
the active region of the power semiconductor device comprises a plurality of grooves arranged in the surface of an epitaxial layer at intervals, a plurality of second conductive type well regions arranged in the surface of the epitaxial layer at intervals and respectively surrounding the grooves, first conductive type source regions arranged in the surface of the well regions and arranged on two sides of the grooves, second conductive type short-circuit regions arranged in the well regions and arranged below the grooves, a gate structure arranged between two adjacent well regions and in contact with the well regions and the source regions, and a first source metal layer arranged above the gate structure and in the grooves and simultaneously in ohmic contact with the source regions and the short-circuit regions; and a concave structure is arranged at the bottom of the well region at the corresponding position of the groove. The structure enables an avalanche breakdown position to be transferred from the terminal region to the active region with a larger area, the heat dissipation area is increased, the avalanche current path avoids the parasitic npn transistor base region, the avalanche current path is shortened, the heat generation is reduced, and the avalanche tolerance is improved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain the disclosure without limiting the disclosure. In the drawings:
fig. 1 is a schematic cross-sectional structure of a conventional power semiconductor device;
fig. 2 is a diagram showing simulation results of a termination region avalanche current path a of a conventional power semiconductor device;
fig. 3 is a diagram showing simulation results of an active region avalanche current path B of a conventional power semiconductor device;
fig. 4 is a schematic cross-sectional structure diagram of a power semiconductor device according to an exemplary embodiment of the present disclosure;
fig. 5 is a diagram illustrating simulation results of an avalanche current path C of a power semiconductor device according to an exemplary embodiment of the present disclosure;
fig. 6 is a schematic flow chart illustrating a method for manufacturing a cell structure of a power semiconductor device according to an exemplary embodiment of the present disclosure;
FIGS. 7-12 are schematic cross-sectional structural views formed at steps associated with a method of fabricating a cell structure of a power semiconductor device according to an exemplary embodiment of the present disclosure;
in the drawings, like parts are designated with like reference numerals, and the drawings are not drawn to scale.
Detailed Description
Embodiments of the present disclosure will be described in detail with reference to the accompanying drawings and examples, so that how to apply technical means to solve technical problems and achieve the corresponding technical effects can be fully understood and implemented. The embodiments and the features of the embodiments of the present disclosure can be combined with each other without conflict, and the formed technical solutions are all within the protection scope of the present disclosure. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure.
It will be understood that spatial relationship terms, such as "above", "below", "beneath", and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" other elements would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the present disclosure are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present disclosure. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present disclosure should not be limited to the particular shapes of regions illustrated herein, but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present disclosure.
In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. The following detailed description of the preferred embodiments of the present disclosure, however, the present disclosure may have other embodiments in addition to these detailed descriptions.
Example one
As shown in fig. 4, the embodiment of the present disclosure provides a power semiconductor device 200, which includes a substrate 201, an epitaxial layer 202, a drain metal layer 203, an active region 210, a transition region 220, and a termination region 230.
Illustratively, the substrate 201 is a silicon carbide substrate or a silicon substrate of the first conductivity type. The substrate 201 has a resistivity of 0.01 to 0.03. omega. cm and a thickness of 200 to 400. mu.m.
The epitaxial layer 202 is an epitaxial layer of the first conductivity type and is located over the substrate 201. The epitaxial layer 202 has an ion doping concentration of 5e14 to 5e16cm-3. The doping concentration and thickness of the epitaxial layer 202 are adjusted according to different withstand voltage capabilities of the device.
The drain metal layer 203 is located under the substrate 201 and forms an ohmic contact with the substrate 201.
A number of trench spaces are provided in the surface of epitaxial layer 202. The depth of the trench is 0.2 to 0.5 μm.
The well region 211 is a well region of the second conductivity type, the plurality of well regions 211 are disposed in the surface of the epitaxial layer 202 at intervals, moats respectively surround the trenches, and the upper surface of the well region 211 is flush with the upper surface of the epitaxial layer 202. Correspondingly, the bottom of the well region 211 is provided with a recessed structure at a corresponding position of the trench. The depth of the well region 211 is 0.6-1.5 μm, and the ion doping concentration of the well region 211 is 1e 18-5 e19cm-3。
The source region 212 is a source region of the first conductivity type, located in the surface of the well region 211 and on both sides of the trench, and one end of the source region 212 close to the trench and the trenchThe sidewalls of the trenches contact and the upper surface of source regions 212 is level with the upper surface of epitaxial layer 202. The width of the source region 212 is smaller than that of the well region 211, the well region 211 has a width difference with an end of the source region 212 away from the trench, and is used for forming a channel (not shown) with the gate insulating layer 214, and an area between two adjacent channels is a JFET region (not shown). The source region 212 has a depth of 0.2 to 0.5 μm and an ion doping concentration of 5e18 to 5e20cm-3。
The short-circuit region 213 is a second conductive type short-circuit region, the short-circuit region 213 is located below the trench, and an upper surface of the short-circuit region is flush with a bottom of the trench. The ion doping concentration of the short-circuit region 213 is greater than that of the well region 211. The short-circuit region 213 has a depth of 0.2 to 0.5 μm and an ion doping concentration of 5e18 to 5e20cm-3。
The layout of the well region 211, the source region 212 and the short-circuit region 213 may be square, hexagonal, lattice array, etc.
The gate structure is disposed between two adjacent well regions 211, and is in contact with the well regions 211 and the source regions 212. The gate structure includes a gate insulating layer 214 and a gate electrode 215. Wherein a gate insulating layer 214 is disposed over the epitaxial layer 202 and simultaneously contacts the source region 212, the well region 211 and the surface of the epitaxial layer 202 for isolating the gate 215 from the source region 212, the well region 211 and the epitaxial layer 202, wherein a channel (not shown) is formed between the gate insulating layer 214 and the well region 211. The gate electrode 215 is located above the gate insulating layer 214, and the gate electrode 215 is a polysilicon gate.
As can be seen, the power semiconductor device 200 in the present embodiment may be (but is not limited to) a planar gate structure power semiconductor device.
An interlayer dielectric layer 216 covers the top and sides of the gate structure (i.e., the top and sides of the gate, and the sides of the gate insulation layer).
The first source metal layer 217 is located over the gate structure and within the trench and forms a good ohmic contact with both the source region 212 and the shorting region 213. Wherein the first source metal 217 cannot contact the epitaxial layer 202. The first source metal 217 may be a metal having low contact resistivity, such as aluminum, nickel, or the like. The first source metal 217 is isolated from the gate insulating layer 214 and the gate electrode 215 (gate structure) by an interlayer dielectric layer 216 (not shown).
The transition region 220 includes a doped region 221, an interlayer dielectric layer 222, and a second source metal layer 223.
The doped region 221 is a doped region of the second conductivity type, and is located in the surface of the epitaxial layer 202, an upper surface of the doped region 221 is flush with an upper surface of the epitaxial layer 202, an ion doping concentration of the doped region 221 is the same as that of the well region 211, and a depth of the doped region 221 is the same as that of the well region 211.
A second source metal layer 223 is located over the epitaxial layer 202 and forms an ohmic contact with the doped region 221. The second source metal layer 223 contacts the first source metal layer 217. The second source metal layer 223 may be a metal having low contact resistivity, such as aluminum, nickel, or the like.
At the location of the transition region 220, the interlayer dielectric layer 222 covers a portion of the doped region 221.
Correspondingly, the first conductivity type and the second conductivity type are opposite. For example, when the first conductivity type is N-type, the second conductivity type is P-type; when the first conductive type is P type, the second conductive type is N type.
As shown in fig. 4, in the present embodiment, due to the existence of the recessed structure at the bottom of the well 211 at the corresponding position of the trench, the depth of the recessed well is deeper than that of the field limiting ring at the terminal, and since the recessed structure is closer to the drain, when the gate voltage is 0 or negative and the drain voltage is positive, the electric field is concentrated at the corner C point of the recessed structure, the avalanche breakdown occurs first at C point, and the avalanche current path is shown by the dotted arrow in the figure, and flows out of the source from C point through the recessed structure and the short-circuit region 213. The avalanche breakdown position is transferred from the termination region to the active region with a larger area, increasing the heat dissipation area. And the avalanche current path C avoids the base region of the parasitic npn transistor, shortens the avalanche current path, reduces the generation of heat, and improves the avalanche tolerance, and a simulation result schematic diagram of the avalanche current path C is shown in fig. 5.
It should be noted that the power semiconductor device in this embodiment may be a MOSFET with a planar Gate structure, an Insulated Gate Bipolar Transistor (IGBT) with a planar Gate structure, or a Junction Barrier Schottky diode (JBS).
The embodiment provides a power semiconductor device 200, an active region 210 of the power semiconductor device 200 includes a plurality of trenches disposed at intervals in a surface of an epitaxial layer 202, a plurality of second conductivity type well regions 211 disposed at intervals in the surface of the epitaxial layer 202 and respectively surrounding the trenches, first conductivity type source regions 212 disposed in the surface of the well regions 211 and disposed at two sides of the trenches, second conductivity type short-circuit regions 213 disposed in the well regions 211 and disposed below the trenches, a gate structure disposed between two adjacent well regions 211 and in contact with the well regions 211 and the source regions 212, and a first source metal layer 217 disposed above the gate structure and in the trenches and simultaneously forming ohmic contact with the source regions 212 and the short-circuit regions 213; wherein, a recess structure is disposed at the bottom of the well region 211 at a position corresponding to the trench. With the structure, the avalanche breakdown position is transferred from the terminal region 230 to the active region 210 with a larger area, so that the heat dissipation area is increased, and the avalanche current path avoids the parasitic npn transistor base region, thereby shortening the avalanche current path, reducing the generation of heat and improving the avalanche tolerance.
Example two
On the basis of the first embodiment, the present embodiment provides a method for manufacturing a power semiconductor device 200. Fig. 6 is a schematic flow chart illustrating a method for manufacturing the power semiconductor device 200 according to an embodiment of the disclosure. Fig. 7-12 are schematic cross-sectional structures formed at steps related to a method for manufacturing a power semiconductor device 200 according to an embodiment of the disclosure. Next, detailed steps of an exemplary method of a method of manufacturing the power semiconductor device 200 according to the embodiment of the present disclosure will be described with reference to fig. 6 and fig. 7 to 12.
As shown in fig. 6, the method for manufacturing the power semiconductor device 200 of the present embodiment includes the following steps:
step S101: a first conductivity type substrate 201 is provided.
The substrate 201 is a silicon carbide substrate or a silicon substrate of the first conductivity type. The substrate 201 has a resistivity of 0.01 to 0.03. omega. cm and a thickness of 200 to 400. mu.m.
Step S102: a first conductive type epitaxial layer 202 is formed over a substrate 201.
Specifically, the epitaxial layer 202 is an epitaxial layer of the first conductivity type, and is located over the substrate 201. The epitaxial layer 202 has an ion doping concentration of 5e14 to 5e16cm-3. The doping concentration and thickness of the epitaxial layer 202 are adjusted according to different withstand voltage capabilities of the device.
Step S103: as shown in fig. 7, trenches (not labeled) are formed in the surface of epitaxial layer 202 at spaced intervals.
Specifically, a photolithography process is adopted, a part of the surface of the epitaxial layer 202 is selectively shielded by a photoresist, and then a plurality of trenches arranged at intervals are formed in the surface of the epitaxial layer 202 by an etching process. The depth of the trench is 0.2 to 0.5 μm.
Step S104: as shown in fig. 8 to 9, a plurality of second conductivity type well regions 211 are formed in the surface of the epitaxial layer 202 at intervals and respectively surround the trenches to form active regions 210, and a termination region 230 and a transition region 220 between the active regions 210 and the termination region 230 are formed in the surface of the epitaxial layer 202 in a region where the well regions 211 are not formed; wherein, a recess structure (not labeled) is disposed at the bottom of the well region 211 at a position corresponding to the trench.
Specifically, step S104 includes the following steps:
s104 a: as shown in fig. 8, a photoresist mask layer 204 is formed over the epitaxial layer 202, and patterning is performed on the photoresist mask layer 204, so as to form a first ion implantation window (not labeled) on the photoresist mask layer 204 at a corresponding position of the trench, and form a second ion implantation window (not labeled) and a third ion implantation window (not labeled) on the photoresist mask layer at a region where the first ion implantation window (not labeled) is not formed;
s104 b: as shown in fig. 9, second conductivity type high energy ions are implanted into the surface of the epitaxial layer 202 through the first ion implantation window, the second ion implantation window and the third ion implantation window to form a second conductivity type well region 211, a second conductivity type doped region 221 and a second conductivity type field limiting ring 231 in the surface of the epitaxial layer 202 at positions corresponding to the first ion implantation window, the second ion implantation window and the third ion implantation window, respectively, thereby forming an active region 210, a transition region 220 and a terminal region 230, respectively.
The well region 211, the doped region 221 and the field limiting ring 231 are formed in one step, the depth is 0.6 to 1.5 μm, and the ion doping concentration is 1e18 to 5e19cm-3. The upper surfaces of well region 211, doped region 221, and field limiting ring 231 are flush with the upper surface of epitaxial layer 202. this approach does not add process steps and reticles.
Step S105: first conductive type source regions 212 are formed in the surface of the well region 211 at both sides of the trench.
Specifically, a photolithography process is adopted to selectively shield a portion of the surface of the well region 211, a trench, and other surfaces of the epitaxial layer 202 where the well region 211 is not formed, by using a photoresist, and then, by using an ion implantation process, first conductivity type high energy ions are implanted into the surface of the well region 211, so as to form first conductivity type source regions 212 on two sides of the trench in the surface of the well region 211.
One end of source region 212 near the trench contacts the sidewalls of the trench and the upper surface of source region 212 is flush with the upper surface of epitaxial layer 202. The width of the source region 212 is smaller than that of the well region 211, the well region 211 has a width difference with an end of the source region 212 away from the trench, and is used for forming a channel (not shown) with the gate insulating layer 214, and an area between two adjacent channels is a JFET region (not shown). The source region 212 has a depth of 0.2 to 0.5 μm and an ion doping concentration of 5e18 to 5e20cm-3。
Step S106: as shown in fig. 10, a second conductive-type short-circuiting region 213 is formed under the trench in the well region 211.
Specifically, the well region 211 and the other non-formed well regions 21 are selectively shielded by photoresist using a photolithography process1, an ion implantation window is formed only above the trench, and then second conductivity type high energy ions are implanted into the surface of the well region 211 through an ion implantation process to form a second conductivity type short circuit region 213 below the trench in the well region 211. The upper surface of the short-circuit area is flush with the bottom of the groove. The ion doping concentration of the short-circuit region 213 is greater than that of the well region 211. The short-circuit region 213 has a depth of 0.2 to 0.5 μm and an ion doping concentration of 5e18 to 5e20cm-3。
After step S106, a high temperature annealing process is performed to activate the impurities in all the implanted regions (the well region, the source region, the short-circuit region, the doped region, and the field limiting ring).
Step S107: as shown in fig. 11, a gate structure contacting the well region 211 and the source region 212 is formed between two adjacent well regions 211.
Specifically, step S107 includes the following steps:
s107 a: forming a gate insulating layer 214 over the epitaxial layer 202 and between two adjacent well regions 211 while being in contact with the source region 212, the well regions 211 and the surface of the epitaxial layer 202;
s107 b: a gate electrode 215 is formed over the gate insulating layer 214.
A channel (not shown) is formed between the gate insulating layer 214 and the well region 211. The gate electrode 215 is located above the gate insulating layer 214, and the gate electrode 215 is a polysilicon gate.
Step S108: as shown in fig. 12, a first source metal layer 217 is formed over the gate structure and in the trench while forming ohmic contacts with the source region 212 and the short-circuiting region 213; the gate structure is isolated from the first source metal layer 217 by an interlayer dielectric layer 216.
Specifically, a first source metal layer 217 is formed over the gate structure and in the trench, in ohmic contact with both the source region 212 and the short-circuiting region 213, and a second source metal layer 222 is formed over the doped region 221, in ohmic contact with the doped region 221.
The first source metal 217 and the second source metal layer 222 may be a metal having low contact resistivity, such as aluminum, nickel, or the like.
Wherein an interlevel dielectric layer 222 is formed in the transition region 220 and an interlevel dielectric layer 232 is formed in the termination region simultaneously with the formation of interlevel dielectric layer 216.
Step S109: a drain metal layer 203 is formed under the substrate 201 in ohmic contact with the substrate 201.
Specifically, a drain metal layer 203 on the back side of the device is formed by adopting laser annealing, metal thickening and deposition processes.
And finally, forming protective glue on the front surface of the device.
Correspondingly, the first conductivity type and the second conductivity type are opposite. For example, when the first conductivity type is N-type, the second conductivity type is P-type; when the first conductive type is P type, the second conductive type is N type.
In this embodiment, due to the existence of the recessed structure at the bottom of the well 211 corresponding to the trench, the depth of the recessed well is deeper than that of the field limiting ring at the terminal, and due to the fact that the recessed structure is closer to the drain, when the gate voltage is 0 or negative and the drain voltage is positive, the electric field is concentrated at the corner C point of the recessed structure, the avalanche breakdown occurs at the C point first, and the avalanche current path is shown by the dotted arrow in the figure, and flows out of the source from the C point through the recessed structure and the short-circuit region 213. The avalanche breakdown position is transferred from the termination region 230 to the active region 210 with a larger area, increasing the heat dissipation area, and the avalanche current path C avoids the parasitic npn transistor base region, shortening the avalanche current path, reducing the generation of heat, and improving the avalanche tolerance.
It should be noted that the power semiconductor device in this embodiment may be a MOSFET of a planar gate structure, an IGBT of a planar gate structure, or a JBS.
The embodiment provides a method for manufacturing a power semiconductor device 200, wherein an active region 210 of the power semiconductor device 200 includes a plurality of trenches formed at intervals in a surface of an epitaxial layer 202; forming a plurality of second conductivity type well regions 211 which are arranged at intervals and respectively surround the trenches in the surface of the epitaxial layer 202 to form active regions 212, and forming terminal regions 230 and transition regions 220 between the active regions 210 and the terminal regions 230 in the surface of the epitaxial layer 202 in regions where the well regions 211 are not formed; wherein, a concave structure is arranged at the bottom of the well region 211 at the corresponding position of the trench; forming first conductive type source regions 212 on two sides of the trench in the surface of the well region 211; a second conductive-type short-circuiting region 213 is formed in the well region 211 below the trench. With the structure, the avalanche breakdown position is transferred from the terminal region 230 to the active region 210 with a larger area, so that the heat dissipation area is increased, and the avalanche current path avoids the parasitic npn transistor base region, thereby shortening the avalanche current path, reducing the generation of heat and improving the avalanche tolerance.
The above is merely a preferred embodiment of the present disclosure and is not intended to limit the present disclosure, which may be variously modified and varied by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present disclosure should be included in the protection scope of the present disclosure. Although the embodiments disclosed in the present disclosure are described above, the embodiments are merely used for understanding the present disclosure, and are not intended to limit the present disclosure. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure, and that the scope of the disclosure is to be limited only by the appended claims.
Claims (10)
1. A power semiconductor device is characterized by comprising a first-conductivity-type substrate, a first-conductivity-type epitaxial layer located above the substrate, an active region, a terminal region and a transition region, wherein the active region, the terminal region and the transition region are arranged on the epitaxial layer;
the active region comprises a plurality of grooves arranged in the surface of the epitaxial layer at intervals, a plurality of second conductive type well regions arranged in the surface of the epitaxial layer at intervals and surrounding the grooves respectively, a first conductive type source region arranged in the surface of the well region and arranged at two sides of the grooves, a second conductive type short-circuit region arranged in the well region and arranged below the grooves, a gate structure arranged between two adjacent well regions and in contact with the well region and the source region, and a first source metal layer arranged above the gate structure and in the grooves and simultaneously in ohmic contact with the source region and the short-circuit region;
and the bottom of the well region is provided with a concave structure at a position corresponding to the groove, and the gate structure is isolated from the first source electrode metal layer through an interlayer dielectric layer.
2. The power semiconductor device of claim 1, wherein the depth of the trench is 0.2 to 0.5 μ ι η.
3. The power semiconductor device of claim 1, wherein the gate structure comprises a gate insulating layer over the epitaxial layer and in contact with the source region, the well region and the surface of the epitaxial layer, and a gate over the gate insulating layer.
4. The power semiconductor device of claim 1, wherein the transition region comprises a doped region of the second conductivity type disposed within the epitaxial layer surface and a second source metal layer located above and in ohmic contact with the doped region;
wherein the second source metal layer is in contact with the first source metal layer.
5. The power semiconductor device of claim 1, wherein said termination region includes a plurality of field limiting rings of second conductivity type spaced apart within a surface of said epitaxial layer.
6. The power semiconductor device of claim 1, further comprising:
and the drain metal layer is positioned below the substrate and is electrically connected with the substrate.
7. A method for manufacturing a power semiconductor device, comprising:
providing a first conductive type substrate;
forming a first conductive type epitaxial layer over the substrate;
forming a plurality of grooves arranged at intervals in the surface of the epitaxial layer;
forming a plurality of second conductivity type well regions which are arranged at intervals and respectively surround the groove in the surface of the epitaxial layer so as to form an active region, and forming a terminal region and a transition region between the active region and the terminal region in the region where the well region is not formed in the surface of the epitaxial layer; a concave structure is arranged at the bottom of the well region at the corresponding position of the groove;
forming first conductive type source regions on two sides of the groove in the surface of the well region;
forming a second conductive type short-circuit region below the trench in the well region;
forming a gate structure which is in contact with the well region and the source region between two adjacent well regions;
forming a first source metal layer over the gate structure and in the trench while forming ohmic contacts with the source region and the shorting region; and the gate structure is isolated from the first source electrode metal layer through an interlayer dielectric layer.
8. The method according to claim 7, wherein a plurality of second conductivity type well regions are formed in the surface of the epitaxial layer, and are spaced apart from each other and respectively surround the trenches to form active regions, and a termination region and a transition region between the active regions and the termination region are formed in the surface of the epitaxial layer in a region where the well regions are not formed, the method comprising the steps of:
forming a photoresist mask layer above the epitaxial layer, and performing patterning processing on the photoresist mask layer to form a first ion implantation window at a corresponding position of the trench on the photoresist mask layer, and forming a second ion implantation window and a third ion implantation window in a region where the first ion implantation window is not formed on the photoresist mask layer;
injecting second conductive type high-energy ions into the surface of the epitaxial layer through the first ion injection window, the second ion injection window and the third ion injection window so as to form a second conductive type well region, a second conductive type doping region and a second conductive type field limiting ring at the corresponding positions of the first ion injection window, the second ion injection window and the third ion injection window in the surface of the epitaxial layer respectively, thereby forming an active region, a transition region and a terminal region respectively;
wherein the well region surrounds the trench.
9. The method for manufacturing a power semiconductor device according to claim 7, wherein a gate structure in contact with the well region and the source region is formed between two adjacent well regions, and the method comprises the following steps:
forming a grid insulation layer which is simultaneously contacted with the source region, the well region and the surface of the epitaxial layer above the epitaxial layer and between two adjacent well regions;
a gate is formed over the gate insulation layer.
10. The method of manufacturing a power semiconductor device according to claim 8, wherein a first source metal layer is formed over the gate structure and in the trench while forming ohmic contacts with the source region and the shorting region, comprising the steps of:
and forming a first source metal layer which is simultaneously in ohmic contact with the source region and the short-circuit region above the gate structure and in the groove, and forming a second source metal layer which is in ohmic contact with the doped region above the doped region.
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