CN113644133B - Semiconductor device and preparation method thereof - Google Patents
Semiconductor device and preparation method thereof Download PDFInfo
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- CN113644133B CN113644133B CN202110859760.8A CN202110859760A CN113644133B CN 113644133 B CN113644133 B CN 113644133B CN 202110859760 A CN202110859760 A CN 202110859760A CN 113644133 B CN113644133 B CN 113644133B
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
Abstract
The invention provides a semiconductor device and a preparation method thereof, wherein the semiconductor device comprises: the drift layer is positioned on the semiconductor substrate layer, and a part of the drift layer near the junction of the gate lead-out line region and the transition region is a spacing region; a first well region located at a top region in the drift layer of the gate lead-out line region and the transition region, and located at a side of the spacer region; an insulating layer, the insulating layer comprising: the first insulating layer is positioned on the surface of the drift layer of the gate lead-out circuit region; the second insulating layer is positioned on the surface of the drift layer in the transition region, and the thickness of the second insulating layer is smaller than that of the first insulating layer; the field plate electrode layer is positioned on the first insulating layer and also extends to the surface of part of the second insulating layer; and the drainage conducting structure penetrates through the insulating layer and the field plate electrode layer above the interval region and also extends to part of the first well region around the interval region. The semiconductor device can avoid breakdown at the transition region.
Description
Technical Field
The invention relates to the field of semiconductors, in particular to a semiconductor device and a preparation method thereof.
Background
Metal oxide semiconductor field effect transistors ("MOSFETs") are a well known type of semiconductor transistor that may be used as switching devices. A MOSFET is a three-terminal device that includes a source region and a drain region separated by a channel region, and a gate electrode disposed adjacent to the channel region. The MOSFET may be turned on or off by applying a gate bias voltage to the gate electrode. When the MOSFET is turned on (i.e., in its "on state"), current is conducted through the channel region of the MOSFET between the source and drain regions. When the bias voltage is removed from the gate electrode (or reduced below a threshold level), current flow ceases to conduct through the channel region. For example, an n-type MOSFET has n-type source and drain regions and a p-type channel. Thus, an n-type MOSFET has an "n-p-n" design. The n-type MOSFET is turned on when a gate bias voltage is applied to the gate electrode sufficient to create a conductive n-type inversion layer in the p-type channel region that electrically connects the n-type source and drain regions, allowing majority carriers to conduct therebetween.
The power MOSFET is a unipolar voltage control device, is mainly applied to power supplies and power processing systems, and plays a role in controlling electric energy conversion. The gate electrode of a power MOSFET is typically separated from the channel region by a thin gate insulation pattern, such as a silicon oxide pattern. Because the gate electrode of the MOSFET is insulated from the channel region by the gate insulation pattern, a minimum gate current is required to maintain the MOSFET in its on-state or to switch the MOSFET between its on-and off-states. Compared with the traditional Si-based power device, the SiC-based power MOSFET is easier to realize high voltage, low loss and high power density, and therefore, the SiC-based power MOSFET is gradually becoming the main stream of the market.
However, the insulation layer of current power MOSFETs is easily broken down in the transition region.
Disclosure of Invention
Therefore, the technical problem to be solved by the invention is to overcome the problem that the semiconductor device in the prior art is easy to break down in the transition region, so as to provide a semiconductor device and a preparation method thereof.
The invention provides a semiconductor device, which is provided with a cell region, a gate lead-out line region and a transition region, wherein the transition region is positioned between the gate lead-out line region and the cell region; the semiconductor device includes: a semiconductor substrate layer; a drift layer on the semiconductor substrate layer, wherein a part of the drift layer near the junction of the gate lead-out line region and the transition region is a spacing region; the first well region is positioned at the top region in the drift layer of the gate lead-out line region and the transition region, the first well region is positioned at the side part of the interval region, the doping concentration of well ions in the first well region is larger than that of drift ions in the interval region, and the conductivity types of the well ions and the drift ions are opposite; an insulating layer, the insulating layer comprising: the first insulating layer is positioned on the surface of the drift layer of the gate lead-out circuit region; the second insulating layer is positioned on the surface of the drift layer in the transition region, and the thickness of the second insulating layer is smaller than that of the first insulating layer; a field plate electrode layer on the first insulating layer, the field plate electrode layer also extending to a surface of the portion of the second insulating layer; and the drainage conducting structure penetrates through the insulating layer and the field plate electrode layer above the spacing region, is spaced from the field plate electrode layer and also extends to part of the first well region around the spacing region.
Optionally, the spacer is located in a part of the gate lead-out line area, and the orthographic projection of the second insulating layer on the surface of the drift layer has no overlapping area with the spacer; the drainage conductive structure penetrates through the first insulating layer and the field plate electrode layer above the spacer region and above part of the first well region around the spacer region.
Optionally, the spacer is located in a part of the transition region, and the orthographic projection of the first insulating layer on the surface of the drift layer has no overlapping area with the spacer; the drainage conductive structure penetrates through the second insulating layer and the field plate electrode layer above the spacer region and above part of the first well region around the spacer region.
Optionally, the spacer is located in a part of the gate lead-out line region and a part of the transition region; the drainage conductive structure penetrates through the second insulating layer, the first insulating layer and the field plate electrode layer above the spacer region and above part of the first well region around the spacer region.
Optionally, the method further comprises: a plurality of second well regions positioned at intervals in the top region of the drift layer of the cell region, wherein the second well regions are adjacent to the first well regions, and the conductivity type of the second well regions is the same as that of the first well regions; a source region located in the top region of the second well region; a source conductive structure located on the source region.
Optionally, the drain conductive structure is the same potential applied to the source conductive structure.
Optionally, the doping concentration of the well ions in the first well region is greater than the doping concentration of the well ions in the second well region.
Optionally, the method further comprises: a gate structure on a portion of the drift layer of the cell region, the gate structure covering the drift layer between adjacent second well regions and extending to a portion of the surfaces of the second well regions and the source region; the field plate electrode layer is electrically connected with the gate structure.
Optionally, the contact width of the drainage conductive structure and the first well region around the spacer region is 1.5 times to 3 times that of the drainage conductive structure and the spacer region.
Optionally, the contact width between the drainage conductive structure and the first well region around the spacer region is 0.1 to 15 micrometers; the contact width of the drainage conductive structure and the spacer is 1-10 microns.
Optionally, the method further comprises: and the drain electrode layer is positioned on the surface of the semiconductor substrate layer, which is opposite to the drift layer.
Optionally, the semiconductor device is a SiC-based semiconductor device, and the material of the first well region includes SiC doped with well ions.
The invention also provides a preparation method of the semiconductor device, the semiconductor device is provided with a cell area, a gate leading-out line area and a transition area, the transition area is positioned between the gate leading-out line area and the cell area, and the preparation method comprises the following steps: providing a semiconductor substrate layer; forming a drift layer on the semiconductor substrate layer, wherein a part of the drift layer near the junction of the gate lead-out line region and the transition region is a spacing region; forming a first well region positioned at the side part of a spacing region in the top region in the drift layer of the gate lead-out line region and the transition region, wherein the doping concentration of well ions in the first well region is larger than that of drift ions in the spacing region, and the conductivity types of the well ions and the drift ions are opposite; forming an insulating layer after forming the first well region, wherein the method for forming the insulating layer comprises the steps of forming a first insulating layer on the surface of a drift layer of the gate lead-out line region; forming a second insulating layer on the surface of the drift layer in the transition region, wherein the thickness of the second insulating layer is smaller than that of the first insulating layer; forming a field plate electrode layer on the first insulating layer and part of the second insulating layer; and forming a drainage conductive structure penetrating through the insulating layer and the field plate electrode layer on part of the first well region above the spacing region and around the spacing region.
Optionally, the spacer is located in a part of the gate lead-out line area, and the orthographic projection of the second insulating layer on the surface of the drift layer has no overlapping area with the spacer; the step of forming the drainage conductive structure comprises the following steps: and forming a drainage conductive structure penetrating through the first insulating layer and the field plate electrode layer on part of the first well region above the spacing region and around the spacing region.
Optionally, the spacer is located in a part of the transition region, and the orthographic projection of the first insulating layer on the surface of the drift layer has no overlapping area with the spacer; the step of forming the drainage conductive structure comprises the following steps: and forming a drainage conductive structure penetrating through the second insulating layer and the field plate electrode layer on part of the first well region above the spacing region and around the spacing region.
Optionally, the spacer is located in a part of the gate lead-out line region and a part of the transition region; the step of forming the drainage conductive structure comprises the following steps: and forming a drainage conductive structure in the second insulating layer, the first insulating layer and the field plate electrode layer on part of the first well region above the spacing region and around the spacing region.
Optionally, the method further comprises: a plurality of spaced second well regions in the top region of the drift layer of the cell region, the second well regions being contiguous with the first well regions, prior to forming the insulating layer; forming a gate structure on the drift layer between adjacent second well regions and over a portion of the second well regions; the field plate electrode layer is electrically connected with the gate structure.
Optionally, the method further comprises: forming source regions in the second well regions at two sides of the gate structure respectively; forming a source conductive structure on source regions at two sides of the gate structure; the source conductive structure is the same potential applied to the drain conductive structure.
The technical scheme of the invention has the following beneficial effects:
according to the semiconductor device provided by the technical scheme of the invention, the contact between the drainage conductive structure and the spacer is Schottky contact. The contact between the drainage conductive structure and the first well region around the spacer region is ohmic contact. In the process of switching off and switching on the device of the cellular region, the displacement current flowing through the first well region can be shunted from the drainage conductive structure, so that the current distribution below the second insulating layer is greatly reduced, the transverse voltage drop of the displacement current on the first well region is reduced, the second insulating layer on the transition region is prevented from being broken down, and the high switching speed or high tolerance capability of the second insulating layer is improved. For a more sensitive shut-down process, the draining conductive structure will have a stiffening effect with the spacer and the schottky contact between them. When the device of the cell region is in the turn-off process, a transient positive voltage difference is generated on the transverse path of the first well region by displacement current, when the voltage drop near ohmic contact between the drainage conducting structure and the first well region is higher than the forward conduction voltage of a PN junction formed by the first well region and the spacer region in the gate lead-out line region and the transition region, hole current is injected into the spacer region, and at the moment, the space depletion layer of the PN junction formed by the first well region in the gate lead-out line region and the transition region and the drift layer below the first well region is mainly in the drift layer, the space depletion layer is depleted, and the electric field direction of the space depletion layer points to the Schottky junction. Minority carriers in a spacer region below the Schottky junction rapidly migrate out of the Schottky junction under the action of an electric field of a space depletion layer and are collected by a drainage conductive structure, so that the clamping effect on the voltage of a first well region adjacent to the Schottky junction is achieved, extra hole current paths are generated by Schottky contact in the turn-off process, a clamping effect is formed, and the reinforcing effect is achieved. In summary, the second insulating layer of the transition region is prevented from being broken down.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a power switching device;
FIG. 2 is a schematic diagram of the displacement current of the power switching device of FIG. 1 during turn-on;
FIG. 3 is a schematic diagram of the displacement current of the power switching device of FIG. 1 during turn-off;
fig. 4 is a top view of a semiconductor device according to an embodiment of the present invention;
fig. 5 is an enlarged view along a dotted line area Q in fig. 4;
FIG. 6 is a schematic cross-sectional view along the cutting line M-N in FIG. 5;
FIG. 7 is a schematic current diagram of the semiconductor device turn-on process of FIG. 6;
fig. 8 and 9 are current schematic diagrams of the semiconductor device turn-off process in fig. 6;
fig. 10 is a schematic structural diagram of a semiconductor device according to another embodiment of the present invention;
fig. 11 is a schematic structural view of a semiconductor device according to another embodiment of the present invention;
Fig. 12 to 14 are simulation diagrams of a semiconductor device according to an embodiment of the present invention;
fig. 15 to 20 are schematic structural views of a semiconductor device manufacturing process according to an embodiment of the present invention.
Detailed Description
The power switch device needs to be frequently turned on and turned off in operation, the voltage on/off speed is dV/dt, and if the absolute value of dV/dt is too large, electric stress is generated in the power switch device, so that breakdown phenomenon occurs.
Specifically, fig. 1 is a power switching device, where the power switching device includes a cell area a, a gate lead-out line area C, and a transition area B, and the transition area B is located between the gate lead-out line area C and the cell area a; the power switching device includes: a semiconductor substrate layer 10; a drift layer 12 on the semiconductor substrate layer 10; a plurality of spaced apart second well regions 121 located in the top region of the drift layer 12 of the cell region a; a source region 123 located at a top region in the second well region 121; a gate structure 130 on a portion of the drift layer 12 of the cell region a, the gate structure 130 covering the drift layer 12 between adjacent second well regions 121 and extending onto a portion of the surfaces of the second well regions 121 and the source region 123; a first well region 122 located in a top region in the drift layer 12 of the gate extraction line region C and a top region in the drift layer 12 of the transition region B, and the first well region 122 is adjacent to the second well region 121; a first insulating layer 150 on the drift layer 12 of the gate lead-out wiring region C; a second insulating layer 151 located on the surface of the drift layer 12 in the transition region B, wherein the thickness of the second insulating layer 151 is smaller than that of the first insulating layer 150; a field plate electrode layer 160 on the first insulating layer 150, the field plate electrode layer 160 further extending to a surface of the portion of the second insulating layer 151, the field plate electrode layer 160 being electrically connected to the gate electrode layer in the gate structure 130; lead-out wires 170 on the surface of the field plate electrode layer 160 on the gate lead-out wire region C; and a drain layer 11 positioned on the surface of the semiconductor substrate layer 10 on the side facing away from the drift layer 12.
The effect of the arrangement of the transition zone B comprises: the first insulating layer 150 is designed to have a certain distance from the cell region a, so that the thick first insulating layer 150 is prevented from occupying the area of the cell region a in the manufacturing process, and the source electrical connection layer 140 is easily formed on the source region 123.
When the device in the cell region a is turned off, the potential applied to the gate structure 130 is 0 or negative, the potential applied to the source region 123 is 0, and the potential applied to the drain layer 11 is high, and at this time, the PN junction formed by the drift layer 12 and the first well region 122 in the transition region B is reverse biased, and the space charge region in the PN junction is large. In the process of turning on the device in the cell region a, a positive potential is applied to the gate structure 130, and the voltage on the drain layer 11 is continuously reduced, so that for the PN junction formed by the drift layer 12 and the first well region 122 in the transition region B, the space charge region in the PN junction is continuously reduced, and a transient displacement current Ia (refer to fig. 2) is formed from the source region 123 to the drain layer 11 during the discharging process of the space charge region, where the displacement current I (displacement current) =c (dV/dt), C is the capacitance of the space charge region, and dV/dt is the voltage change rate of the drain layer 11. The faster the device of cell region A is turned on, the greater the dV/dt, the greater the transient displacement current I. The displacement current Ia has a resistance in the lateral path of the first well region 122, and factors affecting the resistance of the displacement current Ia in the lateral path of the first well region 122 include the resistivity of the first well region 122 and the lateral dimension of the transition region, the area of the transition region needs to have a relatively large range, the first well region 122 is P-type, the mobility of the first well region 122 is high, and for SiC-based power switching devices, the activation rate of aluminum ions is low, so that even if the doping concentration in the first well region 122 is relatively higher than that of the second well region 121, the resistance of the first well region 122 cannot be reduced to a very low level, and accordingly, the displacement current Ia tends to generate a certain high lateral voltage drop in the lateral path of the first well region 122, the lateral voltage drop is reduced in a negative voltage with respect to the source region 123, the positive potential on the field plate electrode layer 160 and the lateral voltage drop form a superposition effect, and the thickness of the second insulating layer 151 is smaller than that of the first insulating layer 150, that is the thickness of the second insulating layer 151 of the transition region is smaller, so that a transient voltage difference is easily generated, which is far above the critical breakdown of the second insulating layer 151.
When the device turn-off process of the cell region a is opposite to the turn-on process, the direction of the displacement current Ia' (refer to fig. 3) is opposite from the direction of the lateral voltage drop from the drain layer 11 to the source region 123, and similar failure modes are generated in the same manner. Second, although the gate potential is zero or negative when the device in cell region a is turned off, the field plate electrode layer 160 has a lower negative critical breakdown field strength for SiC-based power switching devices, and therefore has no stronger tolerance to this failure during the turn-off process, but is more prone to failure. In addition, in the same system, particularly in an inductive load system commonly seen in a power supply system, the voltage change rate of the off process is generally higher than that of the on process, so that the voltage change rate is higher than that of the on process, and therefore, the displacement current Ia' is higher. Further reinforcement is therefore required during device turn-off to avoid failure.
On the basis, the invention provides a semiconductor device, which can avoid breakdown of the semiconductor device in a transition region.
The following description of the embodiments of the present invention will be made apparent and fully in view of the accompanying drawings, in which some, but not all embodiments of the invention are shown. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In the description of the present invention, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present invention and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; the two components can be directly connected or indirectly connected through an intermediate medium, or can be communicated inside the two components, or can be connected wirelessly or in a wired way. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.
In addition, the technical features of the different embodiments of the present invention described below may be combined with each other as long as they do not collide with each other.
Example 1
Referring to fig. 4 and 5, the semiconductor device has a cell area A1, a gate lead-out line area C1 and a transition area B1, wherein the transition area B1 is located between the gate lead-out line area C1 and the cell area A1; the semiconductor device includes:
a semiconductor substrate layer 200;
a drift layer 210 on the semiconductor substrate layer 200, wherein a portion of the drift layer 210 near the boundary between the gate lead-out line region C1 and the transition region B1 is a spacer region 210a;
a first well region 211 located at a top region in the drift layer 210 of the gate lead-out line region C1 and the transition region B1, and the first well region 211 is located at a side portion of the spacer region 210a, a doping concentration of well ions in the first well region 211 is greater than a doping concentration of drift ions in the spacer region 210a, the well ions being opposite in conductivity type to the drift ions;
an insulating layer, the insulating layer comprising: a first insulating layer 241 located on the surface of the drift layer 210 of the gate lead-out line region C1; a second insulating layer 242 located on the surface of the drift layer 210 in the transition region B1, wherein the thickness of the second insulating layer 242 is smaller than that of the first insulating layer 241;
A field plate electrode layer 220 on the first insulating layer 241, the field plate electrode layer 220 further extending to a surface of the portion of the second insulating layer 242;
the drain conductive structure 230 penetrates through the insulating layer and the field plate electrode layer 220 above the spacer region 210a, and the drain conductive structure 230 is spaced from the field plate electrode layer 220, and the drain conductive structure 230 further extends onto a portion of the first well region 211 around the spacer region 210 a.
The cell region A1, the gate lead line region C1, and the transition region B1 are regions different in plan view layout of the semiconductor device.
In this embodiment, the semiconductor device is described as a power MOSFET. A new generation of semiconductor devices typified by SiC has higher reverse withstand voltage capability, lower forward conduction loss, faster switching frequency, high power density, and stronger environmental withstand capability, and is therefore considered as a new hope in the field of electric energy conversion, and gradually becomes the mainstream of the market. The semiconductor substrate layer 200 is silicon carbide (SiC) doped with conductive ions, for example, the conductivity type of the semiconductor substrate layer 200 is N-type, and the conductive ions doped in the semiconductor substrate layer 200 are phosphorus ions or nitrogen ions. The doping concentration of the conductive ions in the semiconductor substrate layer 200 may be, for example, 1×10 18 atom/cm 3 ～1×10 21 atom/cm 3 But other doping concentrations may be used. The semiconductor substrate layer 200 may be of any suitable thickness (e.g., a thickness between 50 microns and 500 microns). In other embodiments, the semiconductor substrate layer may be a silicon-based substrate. The material of the semiconductor substrate layer is not limited.
The drift layer 210 is doped with drift ions. The material of the drift layer 210 is silicon carbide doped with drift ions. In this embodiment, the conductivity type of the drift layer 210 is N-type. It should be noted that, in other embodiments, the material of the drift layer 210 may be other materials. The drift ions may be either phosphorus ions or nitrogen ions. The doping concentration of drift ions in the drift layer 210 is less than the doping concentration of conductive ions in the semiconductor substrate layer 210. The drift layer 210 has a conductivity type identical to that of the semiconductor substrate layer 210. In this embodiment, the conductivity type of the drift layer 210 is N-type.
The functions of the arrangement of the transition zone B1 include: the first insulating layer 241 is designed to have a certain distance from the cell region A1, so that the thick first insulating layer 241 is prevented from occupying the area of the cell region A1 in the preparation process, and the subsequent source conductive structure is easy to form on the source region.
In one embodiment, the transition zone B1 has a width of 1 micron to 50 microns, such as 1 micron, 5 microns, 10 microns, 15 microns, 20 microns, 25 microns, 30 microns, 35 microns, 40 microns, 45 microns, or 50 microns.
The part of the drift layer 210 near the junction between the gate lead-out line region C1 and the transition region B1 is a spacer region 210a, the conductivity type of the spacer region 210a is the same as that of the drift layer 210, and the doping concentration in the spacer region 210a is identical to that in the drift layer 210, in fact, it is that part of the drift layer 210 forms the spacer region 210a, and the spacer region 210a is used for defining the position of the drain conductive structure 230.
In one embodiment, the distance from the center point of the spacer 210a to the interface of the gate lead-out line region C1 and the transition region B1 is 10 μm or less.
The first well region 211 is located at a top region in the drift layer 210 on the gate lead-out line region C1 and the transition region B1 and at a side of the spacer region 210 a. In this embodiment, the first well region 211 surrounds the side portion of the spacer 210a, and the first well region 211 illustrated in fig. 6 surrounds the spacer 210a, so that the first well region 211 around the spacer 210a is connected.
The first well region 211 has a conductivity type opposite to that of the drift layer 210. In this embodiment, the conductivity type of the first well region 211 is P-type, and the first well region 211 is doped with P-type well ions, such as Al ions or boron ions.
In one embodiment, the semiconductor device is a SiC-based semiconductor device and the material of the first well region includes SiC doped with well ions.
The semiconductor device further includes: a plurality of spaced apart second well regions 212 located in the top region of the drift layer 210 of the cell region A1, the second well regions 212 being adjacent to the first well regions 211, the second well regions 212 having the same conductivity type as the first well regions 211. In this embodiment, the conductivity types of the second well region 212 and the first well region 211 are P-type. In a specific embodiment, the material of the second well region 212 includes SiC doped with well ions.
The doping concentration in the well ions in the first well region 211 is greater than the doping concentration in the well ions in the second well region 212 such that the resistance of the first well region 211 is less than the second well region 212, the resistance of the first well region 211 is relatively small, and the lateral resistance of the first well region 211 is relatively small. The doping concentration of the well ions in the second well region 212 is to satisfy the threshold voltage of the device in the cell region A1.
In one embodiment, the doping concentration of the well ions in the first well region 211 is 10 times to 10 times that of the drift ions in the spacer region 210a 7 Multiple. In a specific embodiment, the doping concentration of the well ions in the first well region 211 is 5×10 17 atom/cm 3 ～5×10 21 atom/cm 3 The doping concentration of drift ions in the spacer 210a is 1×10 14 atom/cm 3 ～5×10 17 atom/cm 3 . Preferably, the doping concentration of the well ions in the first well region 211 is 1E4 to 1E5 times that of the drift ions in the spacer region 210 a.
The semiconductor device further includes: a source region 213 located at a top region in the second well region 212; a gate structure 260 on a portion of the drift layer 210 of the cell region A1, the gate structure 260 covering the drift layer 210 between adjacent second well regions 212 and extending onto a portion of the surfaces of the second well regions 212 and the source regions 213; a source conductive structure 250 is located on the source region 213.
The gate structure 260 includes a gate dielectric layer 261 and a gate electrode layer 262 on the gate dielectric layer 261. The gate dielectric layer 261 material includes silicon oxide. The material of the gate electrode layer 262 includes polysilicon. In other embodiments, the material of gate dielectric layer 261 includes a high-K dielectric layer with K being 3.9 or greater.
The source region 213 is heavily doped, and the conductivity type of the source region 213 is opposite to the conductivity type of the second well region 212, and in this embodiment, the conductivity type of the source region 213 is N-type.
In this embodiment, the thickness of the second insulating layer 242 is smaller than that of the first insulating layer 241. The second insulating layer 242 and the gate dielectric layer 261 are formed in the same process, the material of the second insulating layer 242 is the same as that of the gate dielectric layer 261, and the thickness of the second insulating layer 242 is the same as that of the gate dielectric layer 261. In a specific embodiment, the material of the second insulating layer 242 is silicon oxide.
The thickness of the second insulating layer 242 on the transition region B1 is 0.01 to 0.1 micrometers, and the thickness of the first insulating layer 241 is several to tens of micrometers. For example, in one specific embodiment, the second insulating layer 242 has a thickness of 0.03 micrometers to 0.1 micrometers, and the first insulating layer 241 has a thickness of 0.5 micrometers to 2 micrometers.
In other embodiments, the material of the second insulating layer is different from the material of the gate dielectric layer, and the thickness of the second insulating layer is different from the thickness of the gate dielectric layer.
The material of the field plate electrode layer 220 includes polysilicon. The field plate electrode layer 220 is electrically connected to the gate structure 260, and in particular, the field plate electrode layer 220 is electrically connected to the gate electrode layer 262 (refer to fig. 5).
The end of the gate electrode layer 262 along the extending direction of the gate electrode layer 262 is connected to the field plate electrode layer 220, that is, the end of the gate electrode layer 262 along the extending direction of the gate electrode layer 262 is in contact with the field plate electrode layer 220. For the first well region 211 on the part of the transition region B1, the part of the first well region 211 is adjacent to the second well region 212 along the sidewall of the second well region 212 in the extending direction, and for convenience of description, this part of the transition region B1 is referred to as a feature transition region, the field plate electrode layer 220 extends onto a part of the feature transition region, and a space is provided between the field plate electrode layer 220 on the feature transition region and the cell region A1 (refer to fig. 6). The function of this interval setting is that: the distance between the source conductive structure 250 and the field plate electrode layer 220 on the second well region 212 is larger in the extending direction along the second well region 212, so that the short circuit between the source conductive structure 250 and the field plate electrode layer 220 is avoided.
In this embodiment, the method further includes: and a drain layer 270 positioned on a side surface of the semiconductor substrate layer 200 facing away from the drift layer 210. The device of A1 of the cell region is a MOSFET device.
In this embodiment, the method further includes: and a lead-out line 280 positioned on the surface of the field plate electrode layer 220 on the gate lead-out line region C1.
An ohmic contact region 214 in the top region of the second well region 212, the ohmic contact region 214 being contiguous with the source region 213, the source conductive structure 250 also being located on the ohmic contact region 214 and being electrically connected to the ohmic contact region 214, the ohmic contact region 214 having a low contact resistance with the source conductive structure 250. In other embodiments, the ohmic contact regions 214 may not be provided.
In this embodiment, referring to fig. 6, the spacer 210a is located on a portion of the gate lead-out line region C1, and the orthographic projection of the second insulating layer 242 on the surface of the drift layer 210 has no overlapping area with the spacer 210 a; the drain conductive structure 230 penetrates the first insulating layer 241 and the field plate electrode layer 220 above the spacer 210a and above a portion of the first well region 211 around the spacer 210 a.
The contact between the drain conductive structure 230 and the spacer 210a is a schottky contact. The contact between the drain conductive structure 230 and the first well region 211 around the spacer 210a is an ohmic contact. In the process of turning off and on the device in the cell region A1, the displacement current flowing through the first well region 211 can be shunted from the drainage conductive structure 230, so that the current distribution below the second insulating layer 242 is greatly reduced, the lateral voltage drop of the displacement current on the first well region 211 is reduced, the second insulating layer 242 on the transition region B1 is prevented from being broken down, and the tolerance of the second insulating layer 242 to high switching speed or high dV/dt is improved.
In the semiconductor device of this embodiment, as shown in fig. 7, the conduction conductive structure 230 forms a large current shunt during the opening process of the cellular region A1, so that the current flowing through the first well region 211 under the second insulating layer 242 is greatly reduced, the transient lateral voltage drop is reduced, and the dV/dt tolerance of the second insulating layer 242 is improved.
In this embodiment, for a more sensitive turn-off process, the schottky contact between the drain conductive structure 230 and the spacer 210a will have a reinforcing effect. When the device in the cell region A1 is in the process of turning off, a transient positive voltage difference is generated on the lateral path of the first well region 211 by the displacement current, the positive voltage difference is positive voltage drop relative to the source region 213, when the voltage drop near the ohmic contact between the drain conductive structure 230 and the first well region 211 is higher than the forward conduction voltage of the PN junction formed by the first well region 211 and the spacer region 210a in the gate lead-out line region C1 and the transition region B1, the hole current is injected into the PN junction 210a, and at this time, because the potential on the drain region is relatively high, the space depletion layer of the PN junction formed by the first well region 211 in the gate lead-out line region C1 and the transition region B1 and the drift layer 210 below the first well region 211 is mainly in the drift layer 210, the space depletion layer is depleted, and the electric field direction of the space depletion layer is directed to the schottky junction. Minority carriers in the spacer region 210a below the schottky junction rapidly migrate out of the schottky junction under the action of the electric field of the space depletion layer and are collected by the drainage conductive structure, so that the clamping effect on the voltage of the first well region 211 adjacent to the schottky junction is achieved, an extra hole current path is generated by schottky contact in the turn-off process, a clamping effect is formed, and the reinforcing effect is achieved.
In the turn-off process of the semiconductor device of this embodiment, referring to fig. 8, the current-guiding conductive structure 230 forms a large current shunt in the turn-off process of the cell region A1, so that the current flowing through the first well region 211 under the second insulating layer 242 is greatly reduced, the transient lateral voltage drop is reduced, and the dV/dt tolerance of the second insulating layer 242 is improved. Referring to fig. 9, the schottky contact will create an additional hole current path during turn-off, creating a clamping effect.
In one embodiment, the contact width between the drain conductive structure 230 and the first well region 211 around the spacer 210a is 1.5 times to 3 times, such as 1.5 times, 1.8 times, 2.0 times, 2.5 times, 2.8 times, or 3 times, the contact width between the drain conductive structure 230 and the spacer 210 a. The contact width between the drain conductive structure 230 and the first well region 211 around the spacer 210a refers to: the contact width of the first well region 211 and the drain conductive structure 230 on either side of the spacer 210 a. If the contact width between the drain conductive structure 230 and the first well region 211 around the spacer 210a is too small, the shunting effect of the first well region 211 around the spacer 210a is poor, and if the contact width between the drain conductive structure 230 and the first well region 211 around the spacer 210a is too large, the layout area is affected. If the contact width between the drain conductive structure 230 and the spacer 210a is too small, the shunting effect of the schottky junction is poor, and if the contact width between the drain conductive structure 230 and the spacer 210a is too large, the leakage current of the semiconductor device during operation increases. The contact width between the drain conductive structure 230 and the first well region 211 around the spacer 210a is 1.5 to 3 times that between the drain conductive structure 230 and the spacer 210a, which is advantageous in that: the device can be prevented from breakdown failure in the switching process, and the device can keep low leakage current when the drain electrode area is at high voltage.
In one embodiment, the contact width between the drain conductive structure 230 and the first well region 211 around the spacer 210a is 0.1 to 15 micrometers, and the contact width between the drain conductive structure 230 and the spacer 210a is 1 to 10 micrometers.
In one embodiment, the drain conductive structure 230 is the same potential as the source conductive structure 250.
Example 2
This embodiment differs from embodiment 1 in that: referring to fig. 10, a spacer 210a 'is located in a portion of the transition region B1, and an orthographic projection of the first insulating layer 241 on the surface of the drift layer 210 has no overlapping area with the spacer 210 a'; the drain conductive structure 230' penetrates the second insulating layer 242 and the field plate electrode layer 220 over the spacer 210a ' and over a portion of the first well region 211 around the spacer 210a '.
The drain conductive structure 230' is spaced apart from the field plate electrode layer 220.
The same contents as those of embodiment 1 are not described in detail.
Example 3
This embodiment differs from embodiment 1 in that: referring to fig. 11, a spacer 210a″ is located at a portion of the gate lead-out line region C1 and a portion of the transition region B1; the drain conductive structure 230″ penetrates the second insulating layer 242, the first insulating layer 241, and the field plate electrode layer 220 over the spacer 210a 'and over a portion of the first well region 211 around the spacer 210 a'.
The semiconductor devices of example 1, example 2 and example 3 described above were confirmed by TCAD simulation: reference is made to fig. 12 to 14.
Fig. 12 is a schematic diagram of a device simulation structure including a schottky contact and an ohmic contact surrounding the schottky contact between the drain conductive structure and the drift layer.
Fig. 13 shows that the drainage conductive structure can significantly reduce the voltage born by the second insulating layer in the turn-off process of the device, and effectively inhibit the transient electric field in the turn-off process. The horizontal axis of fig. 13 represents time, and the vertical axis represents voltage.
Fig. 14 shows the flow direction and distribution of the maximum current of the semiconductor device in the turn-off process, the schottky contact and the ohmic contact both play a role in shunting, and the reverse biased N-type schottky effectively extracts hole current and reduces the voltage born by the second insulating layer.
Example 4
This embodiment provides a method of manufacturing a semiconductor device, and a process of manufacturing a semiconductor device of the present invention will be described in detail with reference to fig. 15 to 20. The semiconductor device has a cell region A1, a gate lead-out wiring region C1, and a transition region B1, the transition region B1 being located between the gate lead-out wiring region C1 and the cell region A1.
Referring to fig. 15, a semiconductor substrate layer 200 is provided.
The description about the semiconductor substrate layer 200 is referred to the content of embodiment 1 and will not be described in detail.
With continued reference to fig. 15, a drift layer 210 is formed on the semiconductor substrate layer 200, and a portion of the drift layer 210 near the boundary between the gate lead line region C1 and the transition region B1 is a spacer region 210a.
The description about the drift layer 210 is referred to the content in embodiment 1 and will not be described in detail.
Referring to fig. 16, a first well region 211 is formed at a side of a spacer region 210a at a top region in a drift layer 210 on the gate lead-out line region C1 and the transition region B1, and a doping concentration of well ions in the first well region 211 is greater than a doping concentration of drift ions in the spacer region 210a, the well ions being opposite in conductivity type to the drift ions.
The description about the first well region 211 and the spacer region 210a is referred to the content in embodiment 1, and will not be described in detail.
The process of forming the first well region 211 is a masked ion implantation process.
With continued reference to fig. 16, in the drift layer 210 of the cell region A1, a plurality of spaced apart second well regions 212 are provided in the top region, the second well regions 212 being adjacent to the first well regions 211.
The process of forming the second well region 212 is a masked ion implantation process.
The description about the second well region 212 is referred to the content of embodiment 1 and will not be described in detail.
After forming the first well region 211, forming a second well region 212; alternatively, after the second well region 212 is formed, the first well region 211 is formed.
In this embodiment, the spacer 210a is located on a portion of the gate lead-out line region C1.
Referring to fig. 17, an insulating layer is formed by forming a first insulating layer 241 on the surface of the drift layer 210 of the gate lead-out line region C1; a second insulating layer 242 is formed on the surface of the drift layer 210 in the transition region B1, and the thickness of the second insulating layer 242 is smaller than that of the first insulating layer 241.
In this embodiment, the orthographic projection of the second insulating layer 242 on the surface of the drift layer 210 has no overlapping area with the spacer 210 a.
With continued reference to fig. 17, a gate structure 260 is formed over the drift layer 210 between adjacent second well regions 212 and over a portion of the second well regions 212; a field plate electrode layer 220 is formed on the first insulating layer 241 and a portion of the second insulating layer 242.
The step of forming the gate structure 260 includes: forming a gate dielectric layer 261 on the drift layer 210 between adjacent second well regions 212 and on a part of the second well regions 212; a gate electrode layer 262 is formed on the gate dielectric layer 261. The description of the gate dielectric layer 261 and the gate electrode layer 262 is described with reference to embodiment 1, and will not be described in detail.
In this embodiment, the gate dielectric layer 261 is formed during the process of forming the second insulating layer 242, which simplifies the process. The second insulating layer 242 and the gate dielectric layer 261 are connected together. The second insulating layer 242 and the gate dielectric layer 261 are formed in the same process.
In the present embodiment, the field plate electrode layer 220 is formed in the process of forming the gate electrode layer 262, simplifying the process. In this embodiment, the method further includes: a portion of the field plate electrode layer 220 over the transition region B1 is etched away such that there is a separation between the final field plate electrode layer 220 to the second well region 212.
Referring to fig. 18, source regions 213 are formed in the second well regions 212 on both sides of the gate structure 260, respectively.
In this embodiment, the method further includes: ohmic contact regions 214 are formed in the second well regions 212 on both sides of the gate structure 260, respectively. The source region 213 is located around the ohmic contact region 214.
The ohmic contact region 214 has a conductivity type opposite to that of the source region 213.
Referring to fig. 19, a source conductive structure 250 is formed on the source region 213 at both sides of the gate structure 260; a drain conductive structure 230 penetrating the insulating layer and the field plate electrode layer 220 is formed on a portion of the first well region 211 above the spacer 210a and around the spacer 210 a.
In this embodiment, the source conductive structure 250 is also located on the ohmic contact region 214.
In this embodiment, the drain conductive structure 230 is formed during the process of forming the source conductive structure 250, which simplifies the process.
In this embodiment, specifically, a drain conductive structure 230 penetrating the first insulating layer 241 and the field plate electrode layer 220 is formed on a portion of the first well region 211 above the spacer 210a and around the spacer 210 a.
Referring to fig. 20, a lead-out line 280 is formed on the surface of the field plate electrode layer 220 on the gate lead-out line region C1; a drain layer 270 is formed on a surface of the semiconductor substrate layer 200 facing away from the drift layer 210.
Example 5
This embodiment differs from embodiment 4 in that: the spacer region is positioned in a part of the transition region, and the orthographic projection of the first insulating layer on the surface of the drift layer has no overlapping region with the spacer region; the step of forming the drainage conductive structure is as follows: and forming a drainage conductive structure penetrating through the second insulating layer and the field plate electrode layer on part of the first well region above the spacing region and around the spacing region.
The same contents as those of embodiment 4 in this embodiment will not be described in detail.
Example 6
This embodiment differs from embodiment 4 in that: the interval area is positioned in a part of the grid lead-out line area and a part of the transition area; the step of forming the drainage conductive structure is as follows: and forming a drainage conductive structure in the second insulating layer, the first insulating layer and the field plate electrode layer on the first well region above the spacing region and around the spacing region.
The same contents as those of embodiment 4 in this embodiment will not be described in detail.
It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. While still being apparent from variations or modifications that may be made by those skilled in the art are within the scope of the invention.
Claims (16)
1. A semiconductor device, wherein the semiconductor device has a cell region, a gate lead-out line region, and a transition region, the transition region being located between the gate lead-out line region and the cell region; the semiconductor device includes:
a semiconductor substrate layer;
a drift layer on the semiconductor substrate layer, wherein a part of the drift layer near the junction of the gate lead-out line region and the transition region is a spacing region; the spacing region is at least partially positioned in the gate lead-out line region;
the first well region is positioned at the top region in the drift layer of the gate lead-out line region and the transition region, the first well region is positioned at the side part of the interval region, the doping concentration of well ions in the first well region is larger than that of drift ions in the interval region, and the conductivity types of the well ions and the drift ions are opposite;
an insulating layer, the insulating layer comprising: the first insulating layer is positioned on the surface of the drift layer of the gate lead-out circuit region; the second insulating layer is positioned on the surface of the drift layer in the transition region, and the thickness of the second insulating layer is smaller than that of the first insulating layer;
a field plate electrode layer on the first insulating layer, the field plate electrode layer also extending to a surface of the portion of the second insulating layer;
The drainage conducting structure penetrates through the first insulating layer and the field plate electrode layer above the spacing region, is spaced from the field plate electrode layer and also extends to part of the first well region around the spacing region;
the contact between the drainage conductive structure and the spacing region is schottky contact, and the contact between the drainage conductive structure and the first well region around the spacing region is ohmic contact.
2. The semiconductor device according to claim 1, wherein the spacer is located in a part of the gate lead-out wiring region, and an orthographic projection of the second insulating layer on a surface of the drift layer has no overlapping region with the spacer; the drainage conductive structure penetrates through the first insulating layer and the field plate electrode layer above the spacer region and above part of the first well region around the spacer region.
3. The semiconductor device of claim 1, wherein the spacer is located in a portion of the gate lead-out line region and a portion of the transition region; the drainage conductive structure penetrates through the second insulating layer, the first insulating layer and the field plate electrode layer above the spacer region and above part of the first well region around the spacer region.
4. The semiconductor device according to claim 1, further comprising: a plurality of second well regions positioned at intervals in the top region of the drift layer of the cell region, wherein the second well regions are adjacent to the first well regions, and the conductivity type of the second well regions is the same as that of the first well regions; a source region located in the top region of the second well region; a source conductive structure located on the source region.
5. The semiconductor device of claim 4, wherein the drain conductive structure is the same potential applied to the source conductive structure.
6. The semiconductor device of claim 4, wherein a doping concentration of well ions in the first well region is greater than a doping concentration of well ions in the second well region.
7. The semiconductor device according to claim 4, further comprising: a gate structure on a portion of the drift layer of the cell region, the gate structure covering the drift layer between adjacent second well regions and extending to a portion of the surfaces of the second well regions and the source region; the field plate electrode layer is electrically connected with the gate structure.
8. The semiconductor device of claim 1, wherein a contact width of the drain conductive structure with the first well region around the spacer is 1.5 times to 3 times a contact width of the drain conductive structure with the spacer.
9. The semiconductor device of claim 8, wherein a contact width of the drain conductive structure with the first well region around the spacer region is 0.1 microns to 15 microns; the contact width between the drainage conductive structure and the spacing region is 1-10 micrometers.
10. The semiconductor device according to claim 1, further comprising: and the drain electrode layer is positioned on the surface of the semiconductor substrate layer, which is opposite to the drift layer.
11. The semiconductor device of claim 1, wherein the semiconductor device is a SiC-based semiconductor device and the material of the first well region comprises SiC doped with well ions.
12. A method of manufacturing a semiconductor device having a cell region, a gate lead-out wiring region, and a transition region between the gate lead-out wiring region and the cell region, comprising:
providing a semiconductor substrate layer;
forming a drift layer on the semiconductor substrate layer, wherein a part of the drift layer near the junction of the gate lead-out line region and the transition region is a spacing region; the spacing region is at least partially positioned in the gate lead-out line region;
forming a first well region positioned at the side part of a spacing region in the top region in the drift layer of the gate lead-out line region and the transition region, wherein the doping concentration of well ions in the first well region is larger than that of drift ions in the spacing region, and the conductivity types of the well ions and the drift ions are opposite;
forming an insulating layer after forming the first well region, wherein the method for forming the insulating layer comprises the steps of forming a first insulating layer on the surface of a drift layer of the gate lead-out line region; forming a second insulating layer on the surface of the drift layer in the transition region, wherein the thickness of the second insulating layer is smaller than that of the first insulating layer;
Forming a field plate electrode layer on the first insulating layer and part of the second insulating layer;
forming a drainage conductive structure penetrating through the first insulating layer and the field plate electrode layer on part of the first well region above the interval region and around the interval region;
the contact between the drainage conductive structure and the spacing region is schottky contact, and the contact between the drainage conductive structure and the first well region around the spacing region is ohmic contact.
13. The method for manufacturing a semiconductor device according to claim 12, wherein the spacer is located in a part of the gate lead-out wiring region, and an orthographic projection of the second insulating layer on the surface of the drift layer has no overlapping region with the spacer;
the step of forming the drainage conductive structure comprises the following steps: and forming a drainage conductive structure penetrating through the first insulating layer and the field plate electrode layer on part of the first well region above the spacing region and around the spacing region.
14. The method of manufacturing a semiconductor device according to claim 12, wherein the spacer is located in a portion of the gate lead-out line region and a portion of the transition region;
the step of forming the drainage conductive structure comprises the following steps: and forming a drainage conductive structure in the second insulating layer, the first insulating layer and the field plate electrode layer on part of the first well region above the spacing region and around the spacing region.
15. The method for manufacturing a semiconductor device according to claim 12, further comprising: a plurality of spaced second well regions in the top region of the drift layer of the cell region, the second well regions being contiguous with the first well regions, prior to forming the insulating layer; forming a gate structure on the drift layer between adjacent second well regions and over a portion of the second well regions;
the field plate electrode layer is electrically connected with the gate structure.
16. The method for manufacturing a semiconductor device according to claim 15, further comprising: forming source regions in the second well regions at two sides of the gate structure respectively; forming a source conductive structure on source regions at two sides of the gate structure;
the source conductive structure is the same potential applied to the drain conductive structure.
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| KR20110000941A (en) * | 2009-06-29 | 2011-01-06 | 주식회사 동부하이텍 | Semiconductor memory device of single gate structure and semiconductor memory device array of single gate structure |
| CN105074921A (en) * | 2013-04-03 | 2015-11-18 | 三菱电机株式会社 | Semiconductor device |
| CN108321188A (en) * | 2017-01-18 | 2018-07-24 | 中芯国际集成电路制造(上海)有限公司 | Insulated gate bipolar transistor and forming method thereof |
| CN106952946A (en) * | 2017-04-19 | 2017-07-14 | 中航（重庆）微电子有限公司 | A kind of transition plot structure |
| CN113054016A (en) * | 2019-12-26 | 2021-06-29 | 株洲中车时代半导体有限公司 | Cell structure of silicon carbide MOSFET device and power semiconductor device |
| CN113054015A (en) * | 2019-12-26 | 2021-06-29 | 株洲中车时代半导体有限公司 | Silicon carbide MOSFET chip |
| CN112271218A (en) * | 2020-10-16 | 2021-01-26 | 湖南国芯半导体科技有限公司 | Power semiconductor device and preparation method thereof |
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