CN112447743A - 具有环绕式栅极薄膜晶体管的非易失性存储器及制造方法 - Google Patents
具有环绕式栅极薄膜晶体管的非易失性存储器及制造方法 Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 239000010409 thin film Substances 0.000 title abstract description 4
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 239000004020 conductor Substances 0.000 claims abstract description 28
- 238000000034 method Methods 0.000 claims description 101
- 230000008569 process Effects 0.000 claims description 83
- 238000005530 etching Methods 0.000 claims description 50
- 238000003860 storage Methods 0.000 claims description 25
- 229920000642 polymer Polymers 0.000 claims description 24
- 239000011810 insulating material Substances 0.000 claims description 22
- 125000004122 cyclic group Chemical group 0.000 claims description 10
- 238000004140 cleaning Methods 0.000 claims description 7
- OFIYHXOOOISSDN-UHFFFAOYSA-N tellanylidenegallium Chemical compound [Te]=[Ga] OFIYHXOOOISSDN-UHFFFAOYSA-N 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 3
- 239000000463 material Substances 0.000 description 28
- 239000004215 Carbon black (E152) Substances 0.000 description 9
- 229930195733 hydrocarbon Natural products 0.000 description 9
- 150000002430 hydrocarbons Chemical class 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 230000004888 barrier function Effects 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 8
- 229910052814 silicon oxide Inorganic materials 0.000 description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 229920005591 polysilicon Polymers 0.000 description 6
- 238000000231 atomic layer deposition Methods 0.000 description 4
- 230000008901 benefit Effects 0.000 description 4
- 229910017052 cobalt Inorganic materials 0.000 description 4
- 239000010941 cobalt Substances 0.000 description 4
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 150000001335 aliphatic alkanes Chemical class 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- 229910019001 CoSi Inorganic materials 0.000 description 2
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 150000001336 alkenes Chemical class 0.000 description 2
- 150000001345 alkine derivatives Chemical class 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 125000004432 carbon atom Chemical group C* 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 239000011737 fluorine Substances 0.000 description 2
- 229910052731 fluorine Inorganic materials 0.000 description 2
- 125000001153 fluoro group Chemical group F* 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000004381 surface treatment Methods 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 2
- 229910021342 tungsten silicide Inorganic materials 0.000 description 2
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000001154 acute effect Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 239000000908 ammonium hydroxide Substances 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 239000008367 deionised water Substances 0.000 description 1
- 229910021641 deionized water Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- RWRIWBAIICGTTQ-UHFFFAOYSA-N difluoromethane Chemical compound FCF RWRIWBAIICGTTQ-UHFFFAOYSA-N 0.000 description 1
- 230000005685 electric field effect Effects 0.000 description 1
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910000311 lanthanide oxide Inorganic materials 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- SEOYNUHKXVGWFU-UHFFFAOYSA-N mu-oxidobis(oxidonitrogen) Chemical compound O=NON=O SEOYNUHKXVGWFU-UHFFFAOYSA-N 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000005496 tempering Methods 0.000 description 1
- 229910000314 transition metal oxide Inorganic materials 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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Abstract
一种具有环绕式栅极薄膜晶体管的非易失性存储器及制作方法,存储器包括多层结构、长形插塞结构、第一导体插塞与第二导体插塞。多层结构,包括多个栅极层,彼此分隔堆叠于基底上。所述多层结构中具有贯穿所述多层结构的孔洞。所述孔洞的截面具有长形轮廓,所述长形轮廓具有长度不同的长边与短边。长形插塞结构配置于所述孔洞中,其中所述长形插塞结构的截面具有所述长形轮廓。所述长形插塞结构包括绝缘柱、通道层与栅介电层。通道层环绕所述绝缘柱。栅介电层环绕所述通道层。栅极层环绕所述栅介电层。第一导体插塞设置于所述通道层与所述基底之间以及与所述绝缘柱与所述基底之间。第二导体插塞设置于所述绝缘柱上,且被所述通道层包覆。
Description
技术领域
本公开属于半导体技术领域,涉及一种存储器及制造方法,且特别是有关于一种具有环绕式栅极薄膜晶体管的非易失性存储器及制造方法。
背景技术
非易失性存储器元件(如,闪存存储器)由于具有使存入的数据在断电后也不会消失的优点,因此成为个人电脑和其他电子设备所广泛采用的一种存储器元件。
目前业界较常使用的闪存存储器阵列包括或非门(NOR)闪存存储器与与非门(NAND)闪存存储器。由于NAND闪存存储器的结构是使各存储单元串接在一起,其集成度与面积利用率较有效率。因此,NAND闪存存储器已经广泛地应用在多种电子产品中,特别是大量数据储存领域。
此外,为了进一步地提升存储器元件的储存密度以及集成度,发展出一种三维NAND闪存存储器。然而,在目前三维NAND闪存存储器,面临电场效应不足、存储裕度(memorywindow)小以及起始电压(Vt)的分布较广等问题。
发明内容
本公开实施例提出一种具有环绕式栅极薄膜晶体管的非易失性存储器的制造方法,包括以下步骤。在基底上形成堆叠结构。在所述堆叠结构上形成掩膜层,所述掩膜层具有截面为椭圆形的第一开口。以所述掩膜层为掩膜,对所述堆叠结构进行多个循环刻蚀工艺,以形成截面具有长形轮廓的第二开口,其中所述长形轮廓具有长度不同的长边与短边,且进行每一循环刻蚀工艺包括进行刻蚀工艺以及进行清除工艺。进行刻蚀工艺包括对所述堆叠结构进行第一阶段刻蚀工艺,以在所述堆叠结构中形成第一孔,并在所述第一孔的侧壁与底面形成聚合物。形成在所述第一孔的短边处的所述侧壁的所述聚合物的厚度大于形成在所述第一孔的长边处的所述侧壁的所述聚合物的厚度。进行刻蚀工艺还包括对所述第一孔进行第二阶段刻蚀工艺,以形成第二孔。所述第二孔的短边的长度大于所述第一孔的短边的长度。进行清除工艺,去除在所述第二孔的底面上的所述聚合物。
本公开的实施例通过循环刻蚀工艺的控制,可以在堆叠结构中形成截面具有长形轮廓的开口。借此,可将栅介电层(电荷储存层)以及栅极层构建为具有长形轮廓,以提升晶体管的电场增强效应,因此,可以增加编程与擦除的裕度(window),并且使得起始电压(Vt)的分布变窄。
为让本公开的上述特征和优点能更明显易懂,下文特举实施例,并配合所附附图作详细说明如下。
附图说明
图1A至图1G为本公开一些实施例的三维非易失性存储器的制造流程剖面图。
图2为本公开一些实施例的形成开口的步骤流程图。
图3A至图3G为形成三维非易失性存储器的制造流程的上视图。图3E、图3F以及图3G分别是图1B、图1C以及图1F的I-I’切线的上视图。
图4是本公开实施例的长形开口、参考开口的内切椭圆开口与参考开口的示意图。
图5A至图5H是本公开实施例的各种具有长形轮廓的开口的示意图。
图6是本公开实施例的长形环绕式栅极结构的立体图。
【符号说明】
10、12、14、16、18:步骤
54:第一孔
56:第二孔
60:聚合物
99:掺杂区
100:基底
101:堆叠结构
102:绝缘材料层
102a、117:绝缘层
111:多层结构
104:牺牲层
106、152:开口
118:开口/沟道
107:接触窗开口
108、116:导体插塞
109:绝缘层
114:通道层
114b:底部
115:介电层/绝缘柱
112:电荷储存结构/栅介电层
120、122、124、126、128、130:侧向开口
121:长形插塞结构
132、134、136、138、140、142、144:栅极层
146:绝缘层
148:导体层
150:掩膜层
C:顶角
SW1、SW2:侧壁
t1、t2:厚度
DO:虚拟最大内切椭圆
DR:轮廓外的虚拟最小外切矩形
DR:参考矩形
LA:长边处
SA:短边处
LLA1、LLA2、LLA3:长边的长度
LSA1、LSA2、LSA3:短边的长度
具体实施方式
为使本发明的目的、技术方案和优点更加清楚明白,以下结合具体实施例,并参照附图,对本发明进一步详细说明。
图1A至图1G为本公开一些实施例的三维非易失性存储器的制造流程剖面图。图2为本公开一些实施例的形成开口的步骤流程图。图3A至图3G为形成三维非易失性存储器的制造流程的上视图。
请参照图1A,在基底100上形成堆叠结构101。基底100例如是硅基底。在一些实施例中,可依据设计需求在基底100中形成掺杂区(如,N+掺杂区或N型阱区)99。堆叠结构101包括交替地堆叠的多个绝缘材料层102与多个牺牲层104。绝缘材料层102的材料包括介电材料,例如是氧化硅。牺牲层104的材料与绝缘材料层102不同,且与绝缘材料层102具有足够的刻蚀选择比。在一些实施例中,牺牲层104的材料例如是氮化硅。绝缘材料层102与牺牲层104例如是通过进行多次化学气相沉积工艺所形成。堆叠结构101中绝缘材料层102以及牺牲层104的层数可以分别大于16,例如是56、64、96。然而,本公开并不以此为限,堆叠结构101中绝缘材料层102以及牺牲层104的层数可取决于存储器元件的设计及密度。
接着,请参照图1B与图2,进行步骤8,在堆叠结构101上形成掩膜层150。掩膜层150具有开口152。开口152具有椭圆形的轮廓(如图3A所示)。之后,以掩膜层150为掩膜,对堆叠结构101进行多个循环刻蚀工艺10,以在堆叠结构101形成开口(或称孔洞)106。在本实施例中,开口106并未贯穿整个堆叠结构101。开口106的底面裸露出堆叠结构101的绝缘材料层102。在其他实施例中,开口106贯穿整个堆叠结构101,且开口106的底面裸露出基底100。此外,在图1B中,开口106具有垂直侧壁,且开口106的底角α为直角。然而,在其他实施例中,开口106可以是具有倾斜侧壁,且开口106的底角α为锐角,例如是85度至89度。换言之,开口106的宽度从堆叠结构101的顶面向堆叠结构101的底面渐缩。
请参照图1B与图2,在本实施例中,每个循环刻蚀工艺10包括刻蚀工艺12与清除工艺18。刻蚀工艺12包括第一阶段刻蚀工艺14以及第二阶段刻蚀工艺16。第一阶段刻蚀工艺14以及第二阶段刻蚀工艺16皆以掩膜层150为掩膜,对堆叠结构101进行刻蚀。图3A绘示出为掩膜层150的开口152的轮廓。图3B至图3E绘示出形成开口106的循环刻蚀工艺中,在各阶段的孔的轮廓。
请参照图1B、图2、图3A与图3B,以掩膜层150为掩膜,对堆叠结构101进行第一阶段刻蚀工艺14,以在堆叠结构101中刻蚀出具有椭圆形的第一孔(或称第一孔洞)54。在进行第一阶段刻蚀工艺14的过程中,也同时在第一孔54的侧壁与底面形成聚合物60。在进行第一阶段刻蚀工艺14后,形成在第一孔54的短边处SA的侧壁SW1的聚合物60的厚度t1大于形成在第一孔54的长边处LA的侧壁SW2的聚合物60的厚度t2。在一些实施例中,聚合物60的厚度,自第一孔54的短边处SA的侧壁SW1之处的厚度t1梯度递减至第一孔54的长边处LA的侧壁SW2之处的厚度t2。第一阶段刻蚀工艺14可以采用各向异性刻蚀工艺,例如是反应性离子刻蚀工艺。第一阶段刻蚀工艺14使用的刻蚀气体包括第一烃、氧气以及氩气。第一烃可以是未取代、部分被氟取代或全氟取代的碳数为1至4的烷、烯或炔,例如是CH4、CF4、C4F8、C4F6或其组合。进行第一阶段刻蚀工艺14的时间例如是80秒至160秒。
请参照图1B、图2、图3B与图3C,进行第二阶段刻蚀工艺16,以对第一孔54扩口,形成截面具有长形轮廓的第二孔(或称第二孔洞)56。由于形成在侧壁SW2的聚合物60的厚度t2小于形成在侧壁SW1的聚合物60的厚度t1,因此,在进行第二阶段刻蚀工艺16期间,当侧壁SW2的聚合物60被移除殆尽且裸露出堆叠结构101时,侧壁SW1的聚合物60虽有损耗,但侧壁SW1仍被聚合物60覆盖。因此,在侧壁SW2的堆叠结构101会比在侧壁SW1的堆叠结构101先裸露出来且较早被刻蚀,而在侧壁SW1的堆叠结构101则被聚合物60保护而未被刻蚀,或仅有少量被刻蚀。因此,进行第二阶段刻蚀工艺16结束后,第二孔56的短边的长度LSA2会大于第一孔54的短边的长度LSA1,而第二孔56的长边的长度LLA2会等于或略大于第一孔54的长边的长度LLA1。换言之,第二孔56的短边的长度LSA2与第一孔54的短边的长度LSA1之间的差值ΔLSA,大于第二孔56的长边的长度LLA2与所述第一孔54的长边的长度LLA1之间的差值ΔLLA。
第二阶段刻蚀工艺16可以采用各向异性刻蚀工艺,例如是反应性离子刻蚀工艺。第二阶段刻蚀工艺16使用的刻蚀气体包括第二烃以及NF3。第二烃可以是部分被氟取代的碳数1至碳数4的烷、烯或炔,例如是CH3F、C4F6、CH2F2或其组合。在一些实施例中,第一阶段刻蚀工艺14所使用的第一烃的碳数大于第二阶段刻蚀工艺16所使用的第二烃的碳数。换言之,第一阶段刻蚀工艺14所使用的第一烃比第二阶段刻蚀工艺16所使用的第二烃更容易产生聚合物。进行第二阶段刻蚀工艺16的时间是进行第一阶段刻蚀工艺14的时间的2倍至4倍。进行第二阶段刻蚀工艺16的时间例如是240秒至320秒。第二阶段刻蚀工艺16与第一阶段刻蚀工艺14的总时间例如是320秒至400秒。
请参照图1B、图2与图3D,进行清除工艺18,以去除沉积在第二孔56的底面上的聚合物60,使第二孔56下方未被刻蚀的堆叠结构101裸露出来。清除工艺18使用的刻蚀气体包括第三烃以及O2。第三烃可以是被氟取代的碳数为1至4的烷,例如是CF4、CH2F2、C4F6或其组合。进行清除工艺18的时间少于第一阶段刻蚀工艺14的时间,且少于第二阶段刻蚀工艺16的时间。进行清除工艺18的时间例如是10秒至15秒。
请参照图1B、图2与图3E,重复进行多次上述循环工艺10,以加深第二孔56的深度。在一些实例中,例如是进行6~25个循环,或是6~50个循环。
之后,请参照图2,进行步骤20,移除掩膜层150以及残留下来的聚合物60,以使堆叠结构101的最顶层的绝缘材料层102的顶面、开口106侧壁的堆叠结构101以及开口106底部的绝缘材料层102裸露出来,以形成图1B所示的开口106。图3E是图1B中I-I’切线的上视图。移除掩膜层150的方法可以采用干法刻蚀工艺,例如是氧电浆。移除聚合物60的方法可以采用湿法刻蚀,例如是采用刻蚀液(H2SO4∶H2O2=2∶1,体积比)以及清洗液(氢氧化氨/过氧化氢/去离子水)。
请参照图3A与图3E,在第一个循环刻蚀工艺10的第一阶段刻蚀工艺14形成的第一孔54的轮廓,与掩膜层150的开口152的轮廓大致接近。随着循环刻蚀工艺的次数增加,形成在堆叠结构101中的孔(开口)的深度逐渐增加,且孔(开口)的底部的轮廓与掩膜层150的开口152的轮廓的差异逐渐变大。在一些实施例中,开口106的顶端处至底端处的截面的轮廓呈长形,如图3E所示。在又一实施例中,开口106的顶端处的截面的轮廓呈椭圆形或类椭圆形,随着开口106深度的增加,开口106的截面的轮廓的长边的长度与短边的长度的比值逐渐变小,且在开口106的底端处的截面的轮廓呈长形,如图3E所示。
参照图3E,开口106的截面具有长形轮廓。长型轮廓具有长边LA3与短边SA3。长边的长度LLA3大于短边的长度LSA3。在此,短边的长度LSA3是表示两个长边LA3的切线AL、A’L之间最大的距离。长边的长度LLA3是表示两个短边SA3的切线BL、B’L之间最大的距离。切线AL与切线A’L平行,切线BL与切线B’L平行,且切线AL、A’L与切线BL、B’L垂直。
请参照图4,开口106底端的横截面具有长形轮廓。长形轮廓满足式1:
<式1>
A0<A1≤A2
其中:
A1:表示长形轮廓所围开口106的面积;
A2:表示参考矩形DR的面积,所述参考矩形具有开口106的所述长边LA3与所述短边SA3;以及
A0:表示参考矩形的最大内切椭圆DO的面积。
在一些实施例中,开口106的底面积与其参考矩形DR的面积的比值范围在0.8至1之间。开口106的底面积的范围介于3000nm2至20000nm2之间。开口106的短边的长度LSA3以及长边的长度LLA3范围在20nm至300nm之间。开口106的短边的长度LSA3的范围例如是在20nm至100nm之间。开口106的长边的长度LLA3的范围例如是在150nm至200nm之间。开口106的短边的长度LSA3与长边的长度LLA3的比例范围可以在0.1至1之间。开口106的短边的长度LSA3与长边的长度LLA3的比例范围例如在0.13至0.5之间。开口106的高宽比大于40,例如是40至96。
请参照图5A至图5H,开口106的顶角C可以是圆角、倒角或是直角。开口106的各个顶角C的形状可以是彼此相同或是彼此相异。开口106的边可以直的(如图5A至图5D所示)或是有微幅的弯曲或呈波浪状(如图5E至图5H所示)。开口106相对应的两个边的长度可以相等(如图5A所示)或是略有差异(如图5B至图5H所示)。
请同时参照图1B、图1C与图3F,在开口106的侧壁上形成电荷储存结构112。电荷储存结构112可以是共形层,顺应着开口106的形状,覆盖开口106侧壁上的绝缘材料层102与牺牲层104,而裸露出开口106的底面的绝缘材料层102。换言之,电荷储存结构112与开口106具有大致相同的形状与轮廓。电荷储存结构112可以是氧化物、氮化物或其组合。在一些实施例中,电荷储存结构112包括氧化物-氮化物-氧化物(ONO)复合层。在一示例实施例中,电荷储存结构112包括氧化硅层、氮化硅层以及氧化硅层。在一些实施例中,电荷储存结构112包括氧化物-氮化物-氧化物-氮化物-氧化物(ONONO)复合层。在一示例实施例中,电荷储存结构112包括氧化硅层、氮化硅层、氧化硅层、氮化硅层以及氧化硅层。
接着,请参照图1C,移除开口106底面所裸露的绝缘材料层102直至裸露出基底100,以形成接触窗开口107。之后,在接触窗开口107之中形成导体插塞108。导体插塞108的形成方法包括外延生长法(epitaxial growth)。导体插塞108可以是硅、砷化镓或是硅锗。
之后,请参照图1C与图3F,在电荷储存结构112上形成通道层114。具体地说,通道层114覆盖开口106的侧壁上的电荷储存结构112,并与导体插塞108接触。在一些实施例中,通道层114可作为位线。通道层114的材料例如是半导体材料,如多晶硅或掺杂多晶硅等。可通过原位掺杂来进行掺杂,或是通过离子注入工艺来进行掺杂。在一些实施例中,在通道层114形成之后,还进行回火工艺。回火工艺后,通道层114的底部114b结晶为单晶硅,而与导体插塞108合并在一起。导体插塞108可以作为源极接触窗,与基底100中的掺杂区99电性连接。通道层114可以是共形层,因此其与开口106具有大致相同的轮廓。
请参照图1C与图3F,在开口106中形成介电层115。介电层115的形成方法例如是利用化学气相沉积法或旋涂法形成填满开口106的介电材料层(未绘示),再对介电材料层进行回蚀工艺,以使所形成的介电层115的上表面低于堆叠结构101的顶表面。介电层115大致垂直于基底100的表面,其又可称为绝缘柱115。
接着,在介电层115上形成导体插塞116。导体插塞116与通道层114接触。在一些实施例中,导体插塞116的材料例如是多晶硅或掺杂多晶硅。导体插塞116的形成方法例如是先形成填满开口106的导体材料层(未绘示),再对导体材料层进行化学机械研磨工艺及/或回刻蚀工艺,以移除开口106外的导体材料层。
然后,在堆叠结构101上形成绝缘层117。绝缘层117覆盖电荷储存结构112、通道层114、导体插塞116以及堆叠结构101。在一些实施例中,绝缘层117的材料例如是氧化硅或其他绝缘材料。
请参照图1D,对绝缘层117以及堆叠结构101进行图案化工艺,以形成穿过绝缘层117、绝缘材料层102与牺牲层104的开口(亦称作沟道)118。在一些实施例中,在进行所述图案化工艺期间,也会同时移除部分基底100,使得开口118裸露出基底100中的掺杂区99。此外,在对绝缘材料层102进行图案化工艺之后,绝缘材料层102的剩余部分形成绝缘层102a。
接着,移除开口118所暴露的牺牲层104,以形成暴露出部分电荷储存结构112与绝缘层102a的侧向开口120、122、124、126、128、130。移除开口118所暴露的牺牲层104的方法例如是干法刻蚀或湿法刻蚀。干法刻蚀中使用的刻蚀剂例如是NF3、H2、HBr、O2、N2、He或其组合。湿法刻蚀使用的刻蚀剂例如是磷酸(H3PO4)溶液。
请参照图1E,进行表面处理工艺,以使侧向开口130所裸露出来的导体插塞108表面形成绝缘层109。表面处理工艺例如是热氧化工艺。绝缘层109例如是氧化硅层。之后,在开口118的表面上以及侧向开口120、122、124、126、128、130中填入栅极层132。栅极层132可以包括依序形成的缓冲材料层、势垒材料层以及栅极导体材料层。缓冲材料层形成于势垒材料层与电荷储存结构之间以及绝缘层102a的表面上。缓冲材料层的材料例如是介电常数大于7的高介电常数的材料,如氧化铝(Al2O3)、HfO2、La2O5、过渡金属氧化物、镧系元素氧化物或其组合等。缓冲材料层的形成方法例如是化学气相沉积法或原子层沉积法(ALD)。缓冲材料层可用以提升擦除以及编程特性。势垒材料层的材料例如是钛(Ti)、氮化钛(TiN)、钽(Ta)、氮化钽(TaN)或其组合。势垒材料层位于缓冲材料层与栅极导体材料层之间。势垒材料层的形成方法例如是化学气相沉积法。栅极导体材料层的材料例如是多晶硅、非晶硅、钨(W)、钴(Co)、铝(Al)、硅化钨(WSix)或硅化钴(CoSix)。栅极导体材料层的形成方法例如是化学气相沉积法。
请参照图1E、图1F与图3G,进行刻蚀工艺,以移除部分的栅极层132,留下位于侧向开口120、122、124、126、128、130中的栅极层134、136、138、140、142、144。刻蚀工艺可以是单一刻蚀工艺或多个刻蚀工艺。刻蚀工艺可以是湿法刻蚀工艺或干法刻蚀工艺。栅极层134、136、138、140、142、144与多个绝缘层102a形成交替地堆叠的多层结构111。在一些实施例中,栅极层134可作为串行选择线(string select line,SSL)。栅极层136、138、140、142可作为字线(word line,WL)。栅极层144可作为接地选择线(ground select line,GSL)。
请参照图1G,在开口118中形成绝缘层146。在一些实施例中,绝缘层146的材料例如是氧化硅。绝缘层146的形成方法例如是化学气相沉积法或原子层沉积法(ALD)沉积绝缘材料层。接着,进行各向异性刻蚀工艺,以移除位于开口118的底部的绝缘材料层。
接着,在开口118中填入导体层148。导体层148可以包括势垒层以及金属层。势垒层的材料例如是钛(Ti)、氮化钛(TiN)、钽(Ta)、氮化钽(TaN)或其组合。形成势垒层的方法例如是化学气相沉积法。金属层的材料例如是钨(W)、多晶硅、钴、硅化钨(WSix)或硅化钴(CoSix)。形成金属层的方法例如是化学气相沉积法。在一些实施例中,导体层148可作为共用源极线(common source line)。至此,完成本公开的三维非易失性存储器的制作。
请参照图1G,具有环绕式栅极薄膜晶体管的非易失性存储器,包括多层结构111、长形插塞结构121、导体插塞108与导体插塞116。多层结构111包括多个栅极层134、136、138、140、142、144,彼此通过绝缘层120a分隔而堆叠于基底100上。多层结构111中具有孔洞106。孔洞106贯穿多层结构111。孔洞106的截面具有长形轮廓(如图3E所示)。长形轮廓具有长度不同的长边LLA3与短边LSA3。长形插塞结构121配置于孔洞106中。长形插塞结构121的截面具有长形轮廓(如图3G所示)。长形插塞结构121包括绝缘柱115、通道层114与栅介电层112。绝缘柱115设置于基底100上。通道层114设置于基底100上,且环绕绝缘柱115。栅介电层112环绕于通道层114周围。栅极层132、134、136、138、140、142、144环绕于栅介电层112周围。导体插塞108设置于通道层114与基底100的间以及与绝缘柱115与基底100之间。导体插塞116设置于绝缘柱115上,且被通道层114包覆。
上述长形轮廓满足式1:
<式1>
A0<A1≤A2
其中,
A1表示长形轮廓所围的面积;
A2表示参考矩形的面积,所述参考矩形具有所述长边LA3与所述短边SA3;以及
A0表示在参考矩形的最大内切椭圆的面积。
在一些实施例中,A1/A2的比例范围介于0.8至1之间。在又一些实施例中,A1/A2的比例范围介于0.9至1之间。此外,栅介电层(电荷储存层)112的外轮廓的转角C可以是圆角、倒角或是直角。
本实施例的三维非易失性存储器的制造方法虽然是以上述方法为例进行说明,然而本公开的三维非易失性存储器的形成方法并不以此为限。
请参照图6,本公开实施例的三维非易失性存储器具有长形环绕式栅极(Gate AllAround)薄膜晶体管结构。长形栅极全环结构包括介电层(亦可称为绝缘柱)115、通道层114、电荷储存层(亦可称为栅介电层)112、栅极层142。绝缘柱115沿着Z轴方向设置在基底上。Z轴方向与基底表面的法线平行。绝缘柱115的截面可以是呈长形。通道层114环绕包覆绝缘柱115的侧壁。栅介电层(电荷储存层)112位于栅极层142与通道层114之间。栅极层142环绕在绝缘柱115的周围。通道层114、栅介电层(电荷储存层)112与栅极层142的截面各自分别呈长形环。
本公开上述实施例是以3D NAND闪存存储器来说明,然而,本公开实施例的具有矩形形状的高高宽比的孔(或称孔洞)的循环刻蚀工艺可用于ROM/NOR闪存存储器/Ultra-ROM的工艺。
综上所述,在上述实施例中,以具有椭圆形开口图案的掩膜层为掩膜,通过循环刻蚀工艺的控制,可以在堆叠结构中形成截面具有长形轮廓的开口。借此,可将电荷储存层构建为具有截面长形轮廓。具有长形的转角的电荷储存层处可以提升晶体管的电场增强效应,因此,可以增加编程与擦除的裕度(window),并且使得起始电压(Vt)的分布变窄。
虽然本发明已以实施例公开如上,然其并非用以限定本发明,任何所属技术领域中具有公知常识的技术人员,在不脱离本发明的精神和范围内,当可作些许的改动与润饰,故本发明的保护范围当视权利要求所界定的范围为准。
以上所述的具体实施例,对本发明的目的、技术方案和有益效果进行了进一步详细说明,所应理解的是,以上所述仅为本发明的具体实施例而已,并不用于限制本发明,凡在本发明的精神和原则之内,所做的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。
Claims (10)
1.一种具有环绕式栅极薄膜晶体管的非易失性存储器,其特征在于,包括:
多层结构,包括多个栅极层,彼此分隔堆叠于基底上,其中所述多层结构中具有孔洞,所述孔洞贯穿所述多层结构,所述孔洞的截面具有长形轮廓,所述长形轮廓具有长度不同的长边与短边;
长形插塞结构,配置于所述孔洞中,其中所述长形插塞结构的截面具有所述长形轮廓,所述长形插塞结构包括:
绝缘柱,设置于所述基底上;
通道层,设置于所述基底上,环绕所述绝缘柱;以及
栅介电层,环绕所述通道层,其中所述栅极层环绕所述栅介电层;
第一导体插塞,设置于所述通道层与所述基底之间以及与所述绝缘柱与所述基底之间;以及
第二导体插塞,设置于所述绝缘柱上,且被所述通道层包覆。
2.根据权利要求1所述的具有环绕式栅极薄膜晶体管的非易失性存储器,其中所述长形轮廓满足式1:
A0<A1≤A2 式1
其中,
A1表示所述长形轮廓所围的面积;
A2表示参考矩形的面积,所述参考矩形具有所述长边与所述短边;以及
A0表示在所述参考矩形的最大内切椭圆的面积。
3.根据权利要求2所述的具有环绕式栅极薄膜晶体管的非易失性存储器,其中A1/A2的比例范围介于0.9至1之间。
4.一种具有环绕式栅极薄膜晶体管的非易失性存储器的制造方法,其特征在于,包括:
在基底上形成堆叠结构;
在所述堆叠结构上形成掩膜层,所述掩膜层具有截面为椭圆形的第一开口;
以所述掩膜层为刻蚀掩膜,对所述堆叠结构进行多个循环刻蚀工艺,以形成截面具有长形轮廓的第二开口,其中所述长形轮廓具有长度不同的长边与短边,且进行每一循环刻蚀工艺包括:
进行刻蚀工艺,包括:
对所述堆叠结构进行第一阶段刻蚀工艺,以在所述堆叠结构中形成第一孔,并在所述第一孔的侧壁与底面形成聚合物,其中形成在所述第一孔的短边处的所述侧壁的所述聚合物的厚度大于形成在所述第一孔的长边处的所述侧壁的所述聚合物的厚度;以及
对所述第一孔进行第二阶段刻蚀工艺,以形成第二孔,其中所述第二孔的短边的长度大于所述第一孔的短边的长度;以及
进行清除工艺,去除在所述第二孔的底面上的所述聚合物。
5.根据权利要求4所述的具有环绕式栅极薄膜晶体管的非易失性存储器的制造方法,其中在进行所述第一阶段刻蚀工艺期间形成的所述聚合物的厚度,自所述第一孔的所述短边处的所述侧壁之处至所述第一孔的所述长边处的所述侧壁之处梯度递减。
6.根据权利要求4所述的具有环绕式栅极薄膜晶体管的非易失性存储器的制造方法,其中所述具有长形轮廓的第一开口满足式1:
A0<A1≤A2 式1
其中
A1表示所述具有长形轮廓所围的面积;
A2表示参考矩形的面积,所述参考矩形具有所述长边与所述短边;以及
A0表示在所述参考矩形的最大内切椭圆的面积。
7.根据权利要求6所述的具有环绕式栅极薄膜晶体管的非易失性存储器的制造方法,其中A1/A2的比例范围介于0.9至1之间。
8.根据权利要求4所述的具有环绕式栅极薄膜晶体管的非易失性存储器的制造方法,还包括:
在所述第一开口的侧壁形成电荷储存层;
在所述第一开口形成通道层,其中所述电荷储存层环绕所述通道层;以及
在所述第一开口中形成绝缘柱,其中部分所述通道层环绕所述绝缘柱。
9.根据权利要求8项所述的具有环绕式栅极薄膜晶体管的非易失性存储器的制造方法,还包括:
在所述第一开口的侧壁形成所述电荷储存层之后,且在形成所述通道层之前,移除所述第一开口下方的部分的所述堆叠结构,以形成裸露出所述基底的第一接触窗开口;
在所述第一接触窗开口中形成第一导体插塞;以及
在所述绝缘柱上形成第二导体插塞,其中另一部分所述通道层环绕所述第二导体插塞。
10.根据权利要求9项所述的具有环绕式栅极薄膜晶体管的非易失性存储器的制造方法,其中所述堆叠结构包括彼此堆叠的多个绝缘材料层与多个牺牲层,该制造方法还包括:
在所述堆叠结构中形成沟道,以裸露出所述多个绝缘材料层与所述多个牺牲层;
移除所述多个牺牲层,以形成多个侧向开口;以及
在所述多个侧向开口中形成多个栅极层。
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