CN112447712A - 集成电路 - Google Patents

集成电路 Download PDF

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Publication number
CN112447712A
CN112447712A CN202010277871.3A CN202010277871A CN112447712A CN 112447712 A CN112447712 A CN 112447712A CN 202010277871 A CN202010277871 A CN 202010277871A CN 112447712 A CN112447712 A CN 112447712A
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China
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width
gate
gates
region
drain
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Inventor
林义雄
邱奕勋
张尚文
蔡庆威
黄禹轩
程冠伦
王志豪
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本公开涉及集成电路。在一个实施例中，集成电路可以包含半导体基板；至少一个源极区，其包含第一掺杂半导体材料；至少一个漏极区，其包含第二掺杂半导体材料；至少一个栅极，形成于至少一个源极区及至少一个漏极区之间；以及纳米片，形成于半导体基板及至少一个栅极之间。纳米片可以配置为至少一个栅极的布线通道，且可以具有第一区域，其具有第一宽度、以及第二区域，其具有第二宽度。第一宽度可以小于第二宽度。

Description

集成电路
技术领域
本发明实施例涉及半导体技术，特别涉及一种包含纳米片(nanosheet)的半导体结构。
背景技术
晶体管技术，例如互补式金属氧化物半导体(complementary metal-oxide-semiconductor，CMOS)架构、鳍式场效晶体管(fin field-effect transistor，FinFET)架构等，大致上使用电压施加至栅极端子(gate terminal)以增加及减少源极区和漏极区之间的电流。因此，晶体管可以根据对于栅极的电压施加以作为开关运行。
这种晶体管技术也作为逻辑结构来运行。例如，可以制造一或多个晶体管以形成简单的(simple)栅极，例如及闸(AND gate，与门)、或闸(OR gate，或门)等，或合并以形成更复杂的栅极，例如反及闸(NAND gates，与非门)、互斥或闸(XOR gates，异或门)、XNOR闸(XNOR gates，XNOR门)等。这些结构大致上包括互连部件，其在晶体管的栅极、源极、及/或漏极之间延伸以连接晶体管。此连接允许电压控制通过晶体管的电流。
在这种晶体管技术中，通道的尺寸对于逻辑结构的处理速度以及功率效率具有直接的影响。例如，较大的通道可以实现较高的电流，因此与较大的通道相连的逻辑结构可以进行更快的处理。然而这种较大的通道可能需要更多电力。相反地，较小的通道可以促进逻辑结构进行更节能的处理，但是承载较少的电流，且相对于较大的通道，可因此提供较慢的处理速度。
发明内容
本发明实施例提供一种集成电路，包括：半导体基板；至少一个源极区，其包括第一掺杂半导体材料；至少一个漏极区，其包括第二掺杂半导体材料；至少一个栅极，形成于至少一个源极区及至少一个漏极区之间；以及纳米片(nanosheet)，形成于半导体基板及至少一个栅极之间，且配置为至少一个栅极的通道，其中纳米片具有第一区域，其具有第一宽度，以及第二区域，其具有第二宽度，其中第一宽度小于第二宽度。
本发明实施例提供一种集成电路的制造方法，包括：提供半导体基板；利用直接微影，沉积纳米片于基板上，纳米片在沿着其长度上具有各种宽度；沉积多个半导体材料于基板上以形成多个源极及多个漏极；以及沉积多个栅极于源极及栅极之间、以及所沉积的纳米片的多个部分上方。
本发明实施例提供一种鳍式场效晶体管，包括：半导体基板；至少一个源极区，其包括以掺杂形成n型区的半导体材料，至少一源极区具有一个高度，其大于半导体基板的高度；至少一个漏极区，其包括以掺杂形成p型区的半导体材料，至少一个漏极区具有一个高度，其大于半导体基板的高度；至少一个栅极，形成于至少一个源极区及至少一个漏极区之间，至少一个栅极具有一个高度，其大于半导体基板的高度；以及纳米片，形成于半导体基板及至少一个栅极之间、半导体基板及至少一个源极区之间、以及半导体基板及至少一个漏极区之间，其中纳米片具有在至少一个栅极下方的具有第一宽度的第一区域，以及在至少一个源极区及至少一个漏极区下方的具有第二宽度的第二区域，其中第一宽度和第二宽度不同。
附图说明
以下将配合附图详述本发明实施例。应注意的是，依据在业界的标准做法，各种特征并未按照比例绘制且仅用以说明例示。事实上，可任意地放大或缩小元件的尺寸，以清楚地表现出本发明实施例的特征。
图1根据一些实施例描绘了具有纳米片通道的鳍式场效晶体管。
图2A描绘了在晶体管的栅极下方的逻辑单元上的纳米片通道的排列。
图2B描绘了在晶体管的源极和漏极下方的逻辑单元上的纳米片通道的排列。
图3A根据一些实施例描绘了沿着晶体管宽度可变的纳米片。
图3B根据一些实施例描绘了另一个沿着晶体管宽度可变的纳米片。
图3C根据一些实施例描绘了又另一个沿着晶体管宽度可变的纳米片。
图4根据一些实施例描绘了多个鳍式场效晶体管栅极通过纳米片连接的逻辑结构。
图5A根据一些实施例描绘了沿着晶体管高度可变的纳米片。
图5B根据一些实施例描绘了另一个沿着晶体管高度可变的纳米片。
图6为根据一些实施例的形成鳍式场效晶体管和宽度可变的纳米片的制程的流程图。
其中，附图标记说明如下：
100：鳍式场效晶体管
102：漏极部件
104：源极部件
106：基板
108，204a，204b，204c，306a，306b，306c，306d，306e，306f：栅极
110：鳍片
112，202，233，302，304，OD(NS)：纳米片
201，201′：鳍式场效晶体管单元
212a，212b，302a-1，302a-2，302a-3，302a-4，302c-1，302c-2，304a-1，304a-2，304a-3，304a-4，304c-1，304c-2：边角
206：间隔物
208：源极
210：漏极，栅极
200，205，215，220，225：栅极
230，231：鳍片部件
230A，230B，230C，230D，230E，231A，231B，231C，231D，231E：鳍片组件
300，300′，300″，400，500，500′：逻辑单元(逻辑结构)
302a，304a：第一区域
302b，304b：第二区域
302c，304c：第三区域
308，CMG：切割金属栅极
502，504，506，508：纳米片通道
600：方法
602，604，606，608：步骤
NFET：NMOS场效晶体管
PFET：PMOS场效晶体管
T1，T2，T3，T4，T5，T6，T7，T8：晶体管
具体实施方式
以下公开提供了许多的实施例或范例，用于实施所提供的标的物的不同元件。各元件和其配置的具体范例描述如下，以简化本发明实施例的说明。当然，这些仅仅是范例，并非用以限定本发明实施例。举例而言，叙述中若提及第一元件形成在第二元件之上，可能包含第一和第二元件直接接触的实施例，也可能包含额外的元件形成在第一和第二元件之间，使得它们不直接接触的实施例。此外，本发明实施例可能在各种范例中重复参考数值以及/或字母。如此重复是为了简明和清楚的目的，而非用以表示所讨论的不同实施例及/或配置之间的关系。
再者，其中可能用到与空间相对用词，例如“在……之下”、“下方”、“较低的”、“上方”、“较高的”等类似用词，是为了便于描述附图中一个(些)部件或特征与另一个(些)部件或特征之间的关系。空间相对用词用以包括使用中或操作中的装置的不同方位，以及附图中所描述的方位。当装置被转向不同方位时(旋转90度或其他方位)，其中所使用的空间相对形容词也将依转向后的方位来解释。
如图1所示，鳍式场效晶体管100大致上包含源极部件104和漏极部件102于半导体基板106上。在一些实施例中，鳍式场效晶体管100可包含N型金属氧化物半导体(N-typemetal-oxide-semiconductor，NMOS)晶体管。例如，基板106可包含p型基板和一或多个n型部件(例如部件102及104)。在另一个范例中，基板106可包含n型基板，此n型基板包含p型部件或井(well)，井上可以形成n型部件(例如部件102及104)。在其他实施例中，鳍式场效晶体管100可包含P型金属氧化物半导体(P-type metal-oxide-semiconductor，PMOS)晶体管。例如，基板106可包含n型基板和一或多个p型部件(例如部件102及104)。在另一个范例中，基板106可包含p型基板，此p型基板包含n型部件或井，井上可以形成p型部件(例如部件102及104)。
又如图1所示，源极部件104和漏极部件102的上表面高于基板106且通过一或多个鳍片电性连接至栅极108(例如鳍片110连接源极104至栅极108)。这些鳍片也可以各自形成部分源极部件104和漏极部件102。
虽然没有描绘于图1，鳍式场效晶体管100可包含源极部件104对应的端子、漏极部件102对应的端子、以及体端子(body terminal)。在一些实施例中，体端子可以形成于与源极部件104和漏极部件102相同侧的基板。附加地或替代地，体端子亦可形成于基板106的相反侧。
栅极108可包含鳍式场效晶体管100的栅极介电部件。栅极108可包含介电层及金属层。栅极108可通过施加电压以变化源极部件104和漏极部件102之间的电流而允许鳍式场效晶体管100的使用。栅极108中使用的介电材料可以控制一或多种栅极108的性质。
栅极108的介电层可包含二氧化硅(silicon dioxide)、HfO2、LaO、AlO、ZrO、TiO、Ta2O5、Y2O3、SrTiO3(STO)、BaTiO3(BTO)、BaZrO、HfZrO、HfLaO、HfSiO、LaSiO、AlSiO、HfTaO、HfTiO、(Ba，Sr)TiO3(BST)、Al2O3、Si3N4、氮氧化硅(silicon oxynitrides，SiON)等。栅极108的金属层可包含Ti、Ag、Al、TiAlN、TaC、TaCN、TaSiN、Mn、Zr、TiN、TSN、TaN、Ru、Mo、Al、WN、Cu、W等。
又如图1所示，形成在栅极108、源极104、及漏极102之下的纳米片112可作为通过鳍式场效晶体管100的电流路径。例如，栅极108是用于提供输入电压(未显示)至鳍式场效晶体管100以作为逻辑门极来运行。图1中的纳米片112控制通过逻辑门极的电流。因此，在栅极108之下的部分的纳米片112是作为鳍式场效晶体管100的通道。纳米片可以是指任何具有100nm以下的厚度的材料。纳米片可包含二维材料(two-dimensional material)，例如石墨烯、MoS2等。替代地，纳米片可包含薄的(100nm以下)材料堆叠，例如MOS2、硅(silicon)等。虽然利用硅来描述，任何适当的半导体材料或金属可以用作鳍式场效晶体管100的纳米片112。
可以将鳍式场效晶体管，例如图1的鳍式场效晶体管100，建构在基板上以形成一或多个逻辑结构(例如及闸、或闸、反及闸、互斥或闸、XNOR闸等)。本公开的实施例，例如图2A、图2B、图3A、图3B、及图3C中所描绘的范例，提供了沿着逻辑结构且宽度不同的纳米片通道。
如图2A所示，鳍式场效晶体管单元201包含纳米片202，其在栅极204外比在栅极204下方具有更大的宽度。如图2A所示，纳米片202经过源极208和漏极210下方，也经过栅极204下方(此部分作为单元201的通道)。在其他实施例中，例如以下所述的图4中描绘，纳米片通道202可以只经过栅极204下方。
又如图2A所示，纳米片202的边角(corner)212a及212b可以位于部分栅极(例如栅极204a及204c)下方。间隔物206可包含氮化硅(silicon nitride)侧壁或任何其他介电质或部件于源极208和漏极210与所对应的栅极(例如栅极204a、204b、204c等)之间。
此外，虽然未描绘于图2A及图2B，多个隔离沟槽(例如浅或深沟槽)、利用硅局部氧化(local oxidation of silicon，LOCOS)技术形成的二氧化硅间隔物、或任何其他适当的部件可以将栅极204b从其他栅极(例如栅极204a及204c)电性分离。替代地，如图2B中的鳍式场效晶体管单元200′所示，纳米片202的边角212a及212b可以位于源极208及/或漏极210下方。
图2A及图2B描绘了在相同基板上提供虚置栅极(dummy gates)204a及204c于栅极204b及其他栅极(未显示)之间的实施例。例如，虚置栅极204a及204c可包含一或多种不同的材料于对应的栅极介电部件，使得虚置栅极204a及204c电性上的功能不像实际的栅极，例如栅极204b。附加地或替代地，虚置栅极204a及204c可缺乏一或多个端子(例如体端子等)，使得经过单元201或201′的电流不会受到栅极204a及204c改变。
如图2A及图2B所示，每个实际的栅极，例如栅极204b，可以在任一侧具有一或多个虚置栅极，因此在对应的基板上形成实际的栅极和虚置栅极的图案。此外，如图2A及图2B所示，设计者可以在至少部分虚置栅极宽度下方(如图2A所示)或在所有虚置栅极宽度下方(如图2B所示)、或在虚置栅极的任何部分下方增加纳米片202的宽度。例如，在虚置栅极下方增加的宽度可提供更高的电流通过单元的不改变电流的部分，例如虚置栅极。在一些实施例中，设计者可以包含一系列的程序指令(例如存储于非暂态(non-transitory)电脑可读取媒体(computer-readable medium))，此程序指令会使一或多个处理器执行指令以自动调整单元200或200′的设计，使得纳米片202和在实际的栅极(栅极204b)下方时的宽度相比，在虚置栅极(例如栅极204a及204c)下方时具有增加的宽度。
纳米片202的这些宽度增加的区域(例如在至少一或多个虚置栅极下方)可以以一或多个部分的单元200的结构为中心。例如，宽度增加的区域可以以虚置栅极的中点为中心，使得一或多个边角(例如边角212a、212b等)可沿着单元的一或多个维度和中点等距。因此，沿着以虚置栅极204a、204c等的中点为中心的长度上，纳米片202可具有宽度增加的区域。附加地或替代地，纳米片202可具有宽度增加的区域，且此宽度以虚置栅极204a、204c等的中点为中心。
在其他实施例中，纳米片202的宽度增加的区域(例如在至少一或多个虚置栅极下方)可以以其他部分的单元200的结构为中心。例如，宽度增加的区域可以以间隔物的中点为中心，使得一或多个边角(例如边角212a、212b等)沿着单元的一或多个维度和中点等距。因此，沿着以间隔物206等的中点为中心的长度上，纳米片202可具有宽度增加的区域。附加地或替代地，纳米片202可具有宽度增加的区域，且此宽度以间隔物206等的中点为中心。因此，设计者可借此置中纳米片202的宽度增加的区域。
相似地，宽度增加的区域可以以源极或漏极部件的中点为中心，使得一或多个边角(例如边角212a、212b等)沿着单元的一或多个维度和中点等距。因此，沿着以源极208、漏极210等的中点为中心的长度上，纳米片202可具有宽度增加的区域。附加地或替代地，纳米片202可具有宽度增加的区域，且此宽度以源极208、漏极210等的中点为中心。因此，设计者可借此将纳米片202的宽度增加的区域配置在中心。
在逻辑单元包含切割金属栅极(cut metal gate)(例如，如图3A及图3B所示并在以下进行说明)的实施例中，设计者可在切割金属栅极之前、之下、及/或之后减少纳米片202的宽度。在一些实施例中，设计工具可以根据邻近的层自动减少纳米片202的宽度。因此，相较于典型的栅极，切割金属栅极所提供的较小的处理面积(processing area)可自动地由设计工具调节。
在任何设计工具包含一系列程序指令(例如存储于非暂态电脑可读取媒体的程序指令)的实施例中，设计工具可以接收定义逻辑单元的数据结构，例如通过指定栅极以及源极和漏极(无论鳍部件、井等)的空间坐标。设计工具可以利用数据结构中的坐标以决定一或多个设定纳米片的边界的坐标。因此，一或多个生产装置(例如电子束微影(e-beamlithography)机台等)可以利用坐标在逻辑单元的生产时将纳米片沉积在决定的位置。设计工具可以利用任何上述的机制以决定位置。
图3A描绘了多个栅极(306a、306b、306c、306d、306e、及306f)排列在逻辑单元300中。纳米片302及304连接栅极306a、306b、306c、306d、306e、及306f以使电流信号通过栅极且允许栅极对信号进行处理。如图3A所示，纳米片通道302及304分别具有第一区域302a及304a，其各自具有第一宽度。此外，纳米片通道302及304分别具有第二区域302b及304b，其各自具有第二宽度。在图3A的范例中，第二宽度小于第一宽度，使得在栅极306c、306d、及306e中的电流信号处理比在栅极306b中更慢，但是功率效率比在栅极306b中更大。在一个替代的实施例中，第二宽度可以大于第一宽度。
又如图3A所示，纳米片通道302及304分别具有第3区域302c及304c，其各自具有第三宽度。在图3A的范例中，第三宽度大于第二宽度，使得栅极306f中的处理比在栅极306c、306d、及306e中更快，但是功率效率比在栅极306c、306d、及306e中更低。在一个替代的实施例中，第三宽度可以小于第二宽度。此外，虽然图3A的范例描绘了和第一宽度相同的第三宽度，其他的实施例可包含小于或大于第一宽度的第三宽度。
图3A描绘了纳米片通道302及304，其分别具有限制区域302a的四个边角302a-1、302a-2、302a-3、及302a-4，以及限制区域304a的四个边角304a-1、304a-2、304a-3、及304a-4。相似地，纳米片通道302及304分别具有限制区域302b的四个边角302a-4、302c-1、302a-3、及302c-2，以及限制区域304b的四个边角304a-4、304c-1、304a-3、及304c-2。在一个图3B中的逻辑结构300′所描绘的替代的实施例中，纳米片通道302及304可以代替地在区域之间包含两个边角。例如，图3B分别描绘了限制区域302a的两个边角302a-2及302a-3，以及限制区域304a的两个边角304a-1及302a-4。相似的，图3B分别描绘了限制区域302b的两个边角302a-3及302c-2，以及限制区域304b的两个边角304a-4及304c-1。
又如图3A及图3B所示，结构300或300′的一或多个栅极可包含切割金属栅极308。此外，如图3A及图3B所示，且如上所述，结构300或300′可以在切割金属栅极之前、下方、及之后分别包含纳米片302及304的较窄的部分302b及304b。和没有在图3A及图3B中被切割的栅极306a、306b、306c、306e、及306f相比，这样减少的宽度可以接纳由切割金属栅极308所提供的较小的处理范围(processing window)。
如图3A及图3B中所示，在不同的栅极306a-306f下方具有不同宽度的纳米片通道302及304可以增进装置的功率消耗、速度、及集成密度(integration density)。例如，具有不对称的部分的纳米片通道302及304可以增进装置速度，因为设计者可以选择使需要提升速度的部分具有较宽的纳米片。替代地或附加地，不对称的部分的纳米片302可通过分离装置以减少整体功率消耗来增进功率消耗。例如，如果具有较大的纳米片302宽度(例如21nm)的装置的速度比得上两个具有较小的纳米片302宽度(例如12nm)的装置，使用者可以具有设计两个装置而不是一个装置的弹性以最小化和较大的装置相关的功率消耗。此外，在纳米片302及304中具有多个宽度的可能性可以促进和其他制程的整合，例如切割金属栅极308的沉积。例如，纳米片通道302及304可在切割金属栅极308将要沉积的部分减少宽度，以利于制造步骤且最小化潜在的重叠。
替代地或附加地，纳米片通道302宽度的选择可以有密度上的考量。例如，当功率上的考量和特定配置不相关时，设计者可以选择具有一个宽的部分的纳米片302，其合并多个装置的功能。在这样的实施例中，大的纳米片通道302(例如宽度21nm)可视为二鳍片装置(2-fin devices)。这样的合并增加了可用的处理范围，因为比起大的单一装置，多个装置的空间及宽度大致上需要额外的图案化/布线空间。因此，额外的布线空间可用于减少和纳米片通道302一起制造的单元的单元高度。
总而言的，由所公开的纳米片宽度可变的装置所提供的弹性有益于面积、设计、及增益。所公开的装置可以为了特定部分的电路以及为了针对的应用而具有多个宽度。例如，纳米片302的宽度可以在2、2.1、3.5、4.25个节点的宽度之间，直到30nm节点。
图3A及图3B描绘了纳米片通道302及304，其至少相对于栅极306a、306b、306c、306d、306e、及306f所沿且定向的轴线具有对称变化的宽度。在图3C的逻辑结构300″所描绘的一个替代的实施例中，例如，至少相对于栅极306a、306b、306c、306d、306e、及306f所沿且定向的轴线，纳米片通道302及304可具有不对称变化的宽度。例如，图3C中的区域302b的第二宽度小于第一宽度，而图3C中的区域304b的第二宽度大于第一宽度。此外，图3C中的区域302c的第三宽度大于第二宽度，而图3C中的区域304c的第三宽度小于第二宽度。在一些实施例中，如图3C所示，不对称的实施例可以允许分别调整用于基板的NMOS场效晶体管(NMOSfield-effect transistor，NFET)部分的纳米片通道302，或者调整用于基板的PMOS场效晶体管(PMOS field-effect transistor，PFET)部分的纳米片通道304。
图3A、图3B、及图3C的实施例可以合并。例如，图3A的四边角的实施例可应用于图3C的非对称的实施例。在这样的范例中，图3C的纳米片302及304可分别具有四个边角于区域302a及302b之间以及区域304a及304b之间，及/或分别具有四个边角于区域302b及302c之间以及区域304b及304c之间。此外，虽然图3A、图3B、及图3C描绘了三个区域，任意数目的区域可用于纳米片通道302及304。
图4描绘了另一个逻辑结构400，包含如图1所描绘的鳍式场效晶体管。如图4所示，晶体管T1、T2、T3、T4、T5、T6、T7、及T8分别与栅极205、210、215、及220一同配置。还为结构400描绘了附加的栅极200及225。栅极200、205、210、215、220、及225可以各自包含介电层及金属层。例如，介电层可包含二氧化硅、HfO2、LaO、AlO、ZrO、TiO、Ta2O5、Y2O3、SrTiO3(STO)、BaTiO3(BTO)、BaZrO、HfZrO、HfLaO、HfSiO、LaSiO、AlSiO、HfTaO、HfTiO、(Ba，Sr)TiO3(BST)、Al2O3、Si3N4、氮氧化硅等。金属层可包含Ti、Ag、Al、TiAlN、TaC、TaCN、TaSiN、Mn、Zr、TiN、TSN、TaN、Ru、Mo、Al、WN、Cu、W等。
和图1相似，结构400还包含鳍片部件230及231。例如，鳍片部件230及231可以形成源极和漏极，其在多个栅极(例如栅极200、205、210、215、220、及225)之间共享。因此，鳍片组件230A可包含晶体管T1的第一源极或漏极，且鳍片组件230B可包含晶体管T1的第二源极或漏极。因此，鳍片组件230A、栅极205、及鳍片组件230B可一起包含晶体管T1。相似地，鳍片组件231B可包含晶体管T2的第一源极或漏极，且鳍片组件231A可包含晶体管T2的第二源极或漏极。因此，鳍片组件231B、栅极205、及鳍片组件231A可一起包含晶体管T2。相似地，鳍片组件230C可包含晶体管T3的第一源极或漏极，且鳍片组件230B可包含晶体管T3的第二源极或漏极。因此，鳍片组件230C、栅极210、及鳍片组件230B可一起包含晶体管T3。相似地，鳍片组件231B可包含晶体管T4的第一源极或漏极，且鳍片组件231C可包含晶体管T4的第二源极或漏极。因此，鳍片组件231B、栅极210、及鳍片组件231C可一起包含晶体管T4。相似地，鳍片组件230C可包含晶体管T5的第一源极或漏极，且鳍片组件230D可包含晶体管T5的第二源极或漏极。因此，鳍片组件230C、栅极215、及鳍片组件230D可一起包含晶体管T5。相似地，鳍片组件231D可包含晶体管T6的第一源极或漏极，且鳍片组件231C可包含晶体管T6的第二源极或漏极。因此，鳍片组件231D、栅极215、及鳍片组件231C可一起包含晶体管T6。相似地，鳍片组件230E可包含晶体管T7的第一源极或漏极，且鳍片组件230D可包含晶体管T7的第二源极或漏极。因此，鳍片组件230E、栅极215、及鳍片组件230D可一起包含晶体管T7。相似地，鳍片组件231D可包含晶体管T8的第一源极或漏极，且鳍片组件231E可包含晶体管T8的第二源极或漏极。因此，鳍片组件231D、栅极215、及鳍片组件231E可一起包含晶体管T8。
又如图4所示，纳米片233可因此将栅极200、205、210、215、220、及225电性连接至输入及输出(未显示)。在图3所示的实施例中，纳米片233位于栅极200、205、210、215、220、及225下方。因此，纳米片112在栅极200、205、210、215、220、及225下方的部分可用作单元400的那些栅极的通道。
图4描绘了纳米片233在沿着单元400的长度上具有三个不同的宽度。然而，可以使用任意数目的宽度。例如，纳米片233可以和每一对栅极具有一个对应的宽度(如图4所示)，或者可以和每一个单一的栅极具有一个对应的宽度(未显示)。其他实施例可包含交替的宽度。例如，对应至单一栅极的第一宽度、对应至一对栅极的第二宽度等。替代地，单元400可包含纳米片233，其具有对应至一对栅极的第一宽度、对应至三重(a triplet of)栅极的第二宽度等。替代地或附加地，纳米片233可包含对应至三重栅极的第一宽度、对应至单一栅极的第二宽度等，或类似组合。
又如图4所示，宽度可以伴随L型(如栅极215及220之间所示)或U型(如栅极205及210之间所示)的变化。因此，以上任何的图案的纳米片233的宽度变化可以还包含L型及U型界面之间的变动。
此外，如图4所示，纳米片233可以不延伸至鳍片230或231的任何部分下方。然而，在一些图4中没有描绘的实施例中，纳米片233可以替代地在至少一部分的鳍片、源极104、及/或漏极108的下方延伸。确实，和其他方法相比，变化纳米片233的宽度允许纳米片233在至少一部分的一些鳍片下方延伸，且不在其他鳍片下方延伸。相似地，和其他方法相比，变化纳米片233的宽度允许纳米片233沿着结构400的长度方向在不同部分的鳍片部件上方(或下方)延伸。
尽管针对纳米片进行了描述，本公开的实施例可以包含三维结构，例如纳米管或纳米线，用于穿过逻辑结构的栅极以传导电流。在这样的实施例中，例如纳米管的高度及半径的两个维度可以沿着其长度方向变化，而不像纳米片，只有一个维度(例如宽度)可以变化。
除了变化宽度，本公开的纳米片通道可以沿着基板的长度方向具有变化的高度。如图5A所示，例如，逻辑结构500包含纳米片通道502及504，其具有不同高度以对应至不同区域的逻辑结构500。例如，高度可以随着逻辑结构500的不同栅极而变化。
此外，可以堆叠本公开的逻辑结构。又如图5A所示，逻辑结构500可包含具有纳米片通道502及504的第一单元，其堆叠于具有纳米片通道506及508的第二单元上。和纳米片通道502及504相似，纳米片506及508可电性连接不同高度的单元，不同高度的单元对应至逻辑结构500的不同区域。例如，高度可以随着逻辑结构500的不同栅极而变化。
在一个范例中，相较于只具有一个鳍片的第二个鳍式场效晶体管的另一个栅极，可以在具有两个鳍片的鳍式场效晶体管(例如图1的鳍式场效晶体管100)的栅极处减少纳米片通道502的高度及/或纳米片通道504的高度，其中具有两个鳍片的鳍式场效晶体管的栅极相对于只具有一个鳍片的第二个鳍式场效晶体管的另一个栅极较宽。因此，可通过利用额外的鳍片所提供的附加的宽度以维持具有两个鳍片的鳍式场效晶体管的栅极处的处理速度，且减少通道的高度以增加利用逻辑结构的单元的堆叠密度。
在另一个范例中，纳米片通道502的高度及/或纳米片通道504的高度可在只具有一个鳍片的鳍式场效晶体管的栅极处增加。因此，可以不添加额外的鳍片而增加栅极处的处理速度，允许包含逻辑结构的堆叠单元具有较窄的宽度但较高的高度。取决于使用堆叠单元的硬件，较高但较窄的单元可以更轻易地放入现有硬件中。
此外，并非所有堆叠中的单元都必须具有变化的高度。在图5B的逻辑结构500′的范例中，第一单元的纳米片通道502及504具有恒定的高度，而第二单元的纳米片通道506及508具有对应至逻辑结构500的不同区域的不同的高度。和变化晶体管中的纳米片通道宽度所带来的优点相似，变化晶体管中的纳米片通道高度可以允许在第一单元及第二单元的不同栅极进行处理速度及功率效率的调整。
图6描绘了形成具有宽度可变的纳米片通道的鳍式场效晶体管(例如图1的鳍式场效晶体管100)或任何鳍式场效晶体管的阵列(例如分别属于图3A、图3B、或图3C的逻辑结构300、300′、或300″，或图4的逻辑结构400)的方法600。虽然参照图1的部分以描述，方法600不限于图1所描绘的实施例。
如图6所示，方法600可以包含提供半导体基板(例如基板106)。例如，半导体基板106可包含硅或其他半导体材料。在一些实施例中，半导体基板106可包含多个半导体于复合材料中。在其它实施例中，半导体基板106可包含一或多种聚合物，例如尼龙(nylon)等、层状硅-绝缘体-硅(silicon-insulator-silicon)基板(例如在使用绝缘体上覆硅(silicon-on-insulator，SOI)技术的实施例中)等。
在一些实施例中，基板106可包含浅沟槽隔离区(shallow trench isolationregion)于用于晶体管的区域之间。可以使用其他适合的微影技术以形成沟槽。附加地或替代地，如上所述，可以使用深沟槽隔离(deep trench isolation)、硅局部氧化、或其它隔离技术以附加或替代于浅沟槽隔离。
在一些实施例中，方法600还可包含利用直接微影以沉积纳米片(例如纳米片112)于基板106上。通过利用直接微影，纳米片可沿着纳米片的长度方向具有各种宽度，而不是恒定的宽度。例如，和依靠具有光阻的基于遮罩的技术的微影相比，通过利用电子束微影、直接激光写入(direct laserwriting)、或任何其他无遮罩微影以沉积纳米片可以对所沉积的纳米片厚度提供更大的控制。
然而，尽管利用直接微影来描述，基于遮罩的光微影技术可用于沉积半导体材料。例如，光罩可用于选择性沉积半导体材料。替代地，可以沉积光阻于基板106上且将其选择性移除(例如通过紫外光或其他辐射)，使得半导体材料可以被沉积且接着用留下的光阻选择性蚀刻。在一些实施例中，可以沉积牺牲层(例如二氧化硅、氮化硅等)且接着用光阻将其选择性蚀刻。
在上述任何实施例中，影像层(image layer)可以形成纳米片112的表面。例如，影像层可包含氧化物、氮氧化物、HfSiO等。在这样的实施例中，影像层可用于促进沉积的层(例如纳米片112)与基板106的粘着且/或提供亲水性，使得水不干扰纳米片112与基板106之间的接合。例如，影像层可包含六甲基二硅氮烷(Bis(trimethylsilyl)amine，HMDS)，六甲基二硅氮烷会促进与基板106的粘着且/或和基板106表面上的二氧化硅反应以形成三甲基化二氧化硅(tri-methylated silicon-dioxide)的疏水层。
方法600可以还包含沉积半导体材料于基板106上以形成源极(例如源极104)和漏极(例如漏极102)。例如，部件可以用旋转涂布技术、外延成长、或任何其他沉积技术来沉积。和纳米片112相似，源极104和漏极102可以利用直接微影来沉积。
替代地，基于遮罩的光微影技术可用于沉积半导体材料。例如，光罩可用于选择性沉积半导体材料。替代地，可以沉积光阻(例如氮化物等)于基板106上且将其选择性移除(例如通过紫外光或其他辐射)，使得半导体材料可以被沉积且接着用留下的光阻选择性蚀刻。在一些实施例中，可以沉积牺牲层(例如二氧化硅、氮化硅等)且接着用光阻将其选择性蚀刻。
在一些实施例中，方法600还可包含沉积栅极(例如栅极108)于源极(例如源极104)和漏极(例如漏极102)之间以及沉积于部分所沉积的纳米片112的上方。
在上述任何实施例中，影像层可以形成栅极108的表面。例如，影像层可包含氧化物、氮氧化物、HfSiO等。
因此，本公开的实施例可以提供一个逻辑结构，其具有包含沿着逻辑结构的基板宽度可变的通道的纳米片。例如，纳米片可以在一些栅极上具有较小的宽度且在其他栅极上具有较大的宽度。在一些实施例中，直接微影可用于足够精准地变化纳米片的宽度。通过利用宽度可变的纳米片，本公开的实施例可提供某些栅极的处理速度的可调性(tunability)(通过利用较大的宽度)，且提供其他栅极功率效率的可调性(通过利用较小的宽度)。此外，CMOS结构中的NMOS栅极和PMOS栅极的调整可以独立进行，允许更大的弹性以设计CMOS芯片。在一些情况中，和具有恒定宽度的纳米片通道的晶体管相比，通过调整通道纳米片的宽度来调整可提供2到20％的功率提升以及5到25％的处理速度提升。例如，可调式逻辑结构的一或多个栅极可具有较宽且/或较高的纳米片通道以增加处理速度，而可调式逻辑结构的其他栅极可具有较宽且/或较高的纳米片通道以增加功率效率。因此，通过调整逻辑结构的栅极，整个结构可以展现上述的功率提升及/或处理速度增加。
在一个实施例中，集成电路可以包含半导体基板；至少一个源极区，其包含第一掺杂半导体材料；至少一个漏极区，其包含第二掺杂半导体材料，以及至少一个栅极，形成于至少一个源极区和至少一个漏极区之间。集成电路可以还包含形成于半导体基板及至少一个栅极之间的纳米片。纳米片可以配置为至少一个栅极的通道，且可以具有第一区域，其具有第一宽度，以及第二区域，其具有第二宽度，其中第一宽度小于第二宽度。
在一个实施例中，制造集成电路的方法可以包含提供半导体基板以及利用直接微影以沉积纳米片于基板上。纳米片可以沿着纳米片的长度具有各种宽度。此方法可以还包含沉积半导体材料于基板上以形成源极和漏极，且沉积栅极于源极和漏极之间以及部分的所沉积的纳米片上方。
在一个实施例中，鳍式场效晶体管可以包含半导体结构；至少一个源极区，其包含以掺杂形成n型区的半导体材料；至少一个漏极区，其包含以掺杂形成p型区的半导体材料。至少一个源极区可以具有高于半导体基板的高度，且至少一个漏极区可以具有高于半导体基板的高度。晶体管可以还包含至少一个栅极，其形成于至少一个源极区和至少一个漏极区之间，且至少一个栅极可以具有高于半导体基板的高度。晶体管可以还包含纳米片，其形成于半导体基板及至少一个栅极之间、半导体基板及至少一个源极区之间、以汲半导体基板及至少一个漏极区之间。纳米片可以具有第一区域，其具有第一宽度于至少一个栅极下方，以及第二区域，其具有第二宽度于至少一个源极区和至少一个漏极区下方。第一宽度可以和第二宽度不同。
以上概述数个实施例的部件，以便在本发明所属技术领域中技术人员可更易理解本发明实施例的观点。在本发明所属技术领域中技术人员应理解，他们能以本发明实施例为基础，设计或修改其他制程和结构，以达到与在此介绍的实施例相同的目的及/或优势。在本发明所属技术领域中技术人员也应理解到，此类等效的制程和结构并无悖离本发明的精神与范围，且他们能在不违背本发明的精神和范围之下，做各式各样的改变、取代和替换。

Claims (1)

1.一种集成电路，包括：
一半导体基板；
至少一源极区，其包括一第一掺杂半导体材料；
至少一漏极区，其包括一第二掺杂半导体材料；
至少一栅极，形成于该至少一源极区及该至少一漏极区之间；以及
一纳米片，形成于该半导体基板及该至少一栅极之间，且配置为该至少一栅极的一通道，
其中，该纳米片具有一第一区域，其具有一第一宽度，以及一第二区域，其具有一第二宽度，其中该第一宽度小于该第二宽度。
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