CN112435969A - Packaging method and packaging structure - Google Patents
Packaging method and packaging structure Download PDFInfo
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- CN112435969A CN112435969A CN202011042495.6A CN202011042495A CN112435969A CN 112435969 A CN112435969 A CN 112435969A CN 202011042495 A CN202011042495 A CN 202011042495A CN 112435969 A CN112435969 A CN 112435969A
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- 238000000034 method Methods 0.000 title claims abstract description 35
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- 230000017525 heat dissipation Effects 0.000 claims abstract description 45
- 238000000151 deposition Methods 0.000 claims abstract description 20
- 229920002120 photoresistant polymer Polymers 0.000 claims description 33
- 239000000758 substrate Substances 0.000 claims description 17
- 239000003623 enhancer Substances 0.000 claims description 14
- 239000000463 material Substances 0.000 claims description 9
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 7
- 239000011248 coating agent Substances 0.000 claims description 7
- 238000000576 coating method Methods 0.000 claims description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 6
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- 229920000642 polymer Polymers 0.000 claims description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 5
- 229910052802 copper Inorganic materials 0.000 claims description 5
- 239000010949 copper Substances 0.000 claims description 5
- 229910000927 Ge alloy Inorganic materials 0.000 claims description 4
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- 229910001128 Sn alloy Inorganic materials 0.000 claims description 4
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- 238000000465 moulding Methods 0.000 claims description 3
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
The application provides a packaging method and a packaging structure, wherein the packaging method comprises the following steps: providing a packaging structure, wherein the packaging structure comprises at least one chip and a plastic package body wrapping the side face of the chip; depositing a heat-conducting metal layer at least on the back surface of the chip; and a heat dissipation piece is arranged on the heat conduction metal layer and is in heat conduction connection with the heat conduction metal layer. The method for forming the heat-conducting metal layer at least on the back of the chip improves the heat dissipation efficiency of the chip, and can solve the technical problem that the heat-conducting metal layer is not firmly connected with the plastic package body, thereby improving the reliability of the packaging structure.
Description
Technical Field
The present invention relates generally to the field of semiconductor packaging, and more particularly to a packaging method and a packaging structure.
Background
The fan-out type packaging structure is a packaging structure which is formed by cutting a plurality of wafer-level heterogeneous chips after plastic packaging into a single chip and then attaching the single chip to a substrate, but the current packaging structure has poor heat dissipation performance.
Disclosure of Invention
In view of the above-mentioned drawbacks and deficiencies of the prior art, it is desirable to provide a packaging method and a packaging structure.
In a first aspect, the present invention provides a packaging method, including:
providing a packaging structure, wherein the packaging structure comprises at least one chip and a plastic package body wrapping the side face of the chip;
depositing a heat-conducting metal layer at least on the back surface of the chip;
and a heat dissipation piece is arranged on the heat conduction metal layer and is in heat conduction connection with the heat conduction metal layer.
Optionally, depositing a heat conducting metal layer at least on the back surface of the chip specifically includes:
coating photoresist on the back surface of the chip, patterning the photoresist to form an opening exposing the plastic package body, and arranging a metal adhesion enhancer layer in the opening;
removing the photoresist;
and depositing the heat-conducting metal layer, wherein the heat-conducting metal layer covers the back surface of the chip and the plastic package body.
Further, the material of the metal adhesion force reinforcing agent layer comprises a high phosphate ester polymer and a titanate polymer.
Optionally, depositing a heat conducting metal layer at least on the back surface of the chip specifically includes:
coating photoresist on the back surface of the chip, patterning the photoresist to form an opening exposing the back surface of the chip, depositing the heat-conducting metal layer in the opening, and removing the photoresist.
Further, the material of the heat-conducting metal layer comprises at least one of gold, silver, copper, chromium, titanium, nickel and palladium.
Further, the depositing a heat conducting metal layer at least on the back surface of the chip and disposing a heat sink on the heat conducting metal layer includes:
and providing a substrate, and inversely installing the chip with the heat-conducting metal layer deposited on the back surface on the substrate.
Further, the disposing a heat sink on the heat conductive metal layer includes:
a metal bonding layer is arranged between the heat-conducting metal layer and the heat dissipation piece;
and carrying out heat treatment on the structure to ensure that the heat-conducting metal layer and the heat radiating piece are in heat conduction connection with the metal bonding layer.
Further, the metal bonding layer includes a gold alloy including a gold-silicon alloy, a gold-tin alloy, a gold-germanium alloy.
In a second aspect, the present application provides a package structure formed according to the above method, including:
the chip comprises at least one chip, wherein a plastic package body is surrounded on the side face of the chip;
a heat-conducting metal layer; the heat dissipation structure is at least formed on the back surface of the chip, a heat dissipation part is arranged on the heat conduction metal layer, and the heat dissipation part is in heat conduction connection with the heat conduction metal layer.
Furthermore, the heat-conducting metal layer further comprises a part located above the plastic-sealed body, and a metal adhesion force enhancer layer is further formed between the plastic-sealed body and the heat-conducting metal layer.
Advantageous effects
The application provides a packaging method and a packaging structure, wherein the packaging method comprises the following steps: providing a packaging structure, wherein the packaging structure comprises at least one chip and a plastic package body wrapping the side face of the chip; depositing a heat-conducting metal layer at least on the back surface of the chip; and a heat dissipation piece is arranged on the heat conduction metal layer and is in heat conduction connection with the heat conduction metal layer. The method for forming the heat-conducting metal layer at least on the back of the chip improves the heat dissipation efficiency of the chip, and can solve the technical problem that the heat-conducting metal layer is not firmly connected with the plastic package body, thereby improving the reliability of the packaging structure.
Drawings
Other features, objects and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:
FIG. 1 is a schematic flow chart illustrating a packaging method according to an embodiment of the present application;
fig. 2A-2D are schematic diagrams illustrating a manufacturing process of the package structure "providing a package structure including at least one chip and a molding compound encapsulating the side of the chip" in fig. 1;
FIG. 3 is a schematic structural diagram of "coating a photoresist on the back surface of the chip" in the embodiment of the present application;
FIGS. 4A-4D are schematic diagrams illustrating a manufacturing process of one embodiment of depositing a thermally conductive metal layer on at least the backside of the chip in FIG. 1;
FIGS. 4E-4G are schematic diagrams illustrating a manufacturing process of one embodiment of FIG. 1 "disposing a heat sink on the heat-conductive metal layer, the heat sink being in heat-conductive connection with the heat-conductive metal layer";
FIGS. 5A-5F are schematic views illustrating a manufacturing process of another embodiment of "depositing a heat-conducting metal layer at least on the back surface of the chip" in FIG. 1;
fig. 5G-5I are schematic diagrams illustrating a manufacturing process of another embodiment of "packaging a chip with a heat conductive metal layer deposited on at least a back surface of the chip" in fig. 1.
Detailed Description
The present application will be described in further detail with reference to the following drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant invention and not restrictive of the invention. It should be noted that, for convenience of description, only the portions related to the present invention are shown in the drawings.
It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.
In the prior art, the packaging structure of the fan-out chip mainly dissipates heat through thinning the chip or through a method of arranging a heat dissipation piece on the back of the chip, but the warpage of the chip is increased after thinning the chip, so that the chip can deviate when being attached to a substrate, the welding between a bonding pad of the chip and the substrate is poor, the chip fails or the performance is affected, the heat dissipation piece is arranged on the surface of the chip, the heat dissipation glue is arranged on the back of the chip at present and is connected with the heat dissipation piece, the heat dissipation glue has poor heat conduction performance, and the heat dissipation of the chip is affected.
In a first aspect, the present application provides a packaging method, comprising the steps of:
referring to fig. 1, S1, providing a package structure including at least one chip 1 and a plastic package body 10 wrapping the side of the chip; specifically, in the actual production process, the forming process of the fan-out chip mainly includes the following steps:
referring to fig. 2A, a carrier plate 2 is provided, and a chip is reassembled and mounted on the carrier plate 2, where the carrier plate 2 may be a glass carrier plate, a metal carrier plate, or the like, and the mounting of the chip 1 on the carrier plate can avoid the chip from being heated and warped in the subsequent plastic packaging process.
Referring to fig. 2B, the chip after being mounted is packaged in a plastic package by a packaging adhesive, the packaging adhesive is wrapped, then one surface of the packaging adhesive, which is far away from the carrier plate, is ground to obtain a first surface, which exposes the bonding pad of the chip 1, and then a wiring layer 11 is formed on the first surface.
Referring to fig. 2C, the carrier 2 is removed to obtain the package structure 100 as shown in fig. 2D, the back surface of the package structure 100 is ground to expose the back surface of the chip 1, where it should be noted that, in order to improve the processing efficiency, a plurality of chips 1 are often packaged in batch at one time, and then the package body is cut in the subsequent process to obtain a small-unit package structure, the package structure provided in the actual packaging process is a small-unit package structure of a cutting knife, and the small-unit package structure may include one or more chips 1.
Referring again to fig. 1, S2, depositing a heat conducting metal layer 19 at least on the back side of the chip 1; heat conduction metal layer 19 can distribute away chip 1 heat that the during operation produced well, thereby solve chip 1's heat dissipation problem, because the cladding has the plastic-sealed body around fan-out type chip or the multi-functional heterogeneous chip, the partial heat conduction metal layer adhesive force that lies in the plastic-sealed body top when the surface of chip forms the heat conduction metal layer is not enough, the phenomenon of heat conduction metal layer and plastic-sealed body separation can appear in the use, influence packaging structure's performance, the above problem can be solved to the method of setting up the heat conduction metal layer that this application provided, its embodiment does:
referring to fig. 3, a photoresist is coated on the back surface of the package structure 100, and the photoresist 12 completely covers the back surface of the package structure 100.
5A-5E are schematic views illustrating the manufacturing process of another embodiment of depositing a heat-conducting metal layer 19b on at least the back surface of the chip;
coating a photoresist 10 on the back surface of the packaging structure 100, so that the photoresist 12 covers the back surface of the chip 1 and the plastic package body 10; referring to fig. 5A, the photoresist 12 is patterned, specifically, the photoresist 12 is patterned by an exposure and development method to form a patterned photoresist layer 12B, an opening exposing the plastic package body 10 is formed on the photoresist layer 12B, the opening needs to completely expose the plastic package body 10, and in some cases, the back surface of the chip 1 can be properly exposed, so that it is ensured that a metal adhesion force enhancer 18 arranged subsequently can completely cover the plastic package body 10, the metal adhesion force enhancer 18 can increase the connection strength between the plastic package body 10 and a heat conductive metal layer 19B arranged subsequently, and the phenomenon that the heat conductive metal layer 19B is separated from the plastic package body 10 is avoided.
Referring to FIG. 5B, the adhesion force enhancer 18 is then disposed within the opening; specifically, the metal adhesion enhancer 18 may be disposed in the opening or disposed on the opening and the photoresist layer 12A by spraying.
Referring to fig. 5C, the photoresist is removed, specifically, the photoresist layer 12A is removed by a lift-off method, thereby exposing the back surface of the chip 1.
Referring to fig. 5D, the heat conducting metal layer 19b is deposited, the heat conducting metal layer 19b covers the back surface of the chip 1 and the plastic package body 10, specifically, the heat conducting metal layer 19b may be formed on the back surface of the chip 1 and the metal adhesion force enhancer 18 by existing deposition such as sputtering, evaporation, and the like, the problem of separation of the heat conducting metal layer 19b on the surface of the plastic package body 10 may be solved by the adhesion force enhancer 18, the metal adhesion force enhancer 18 may be selected from but not limited to a high phosphate polymer and a titanate polymer, and the material of the heat conducting metal layer 19b includes but not limited to at least one of gold, silver, copper, chromium, titanium, nickel, and palladium.
Referring to fig. 5E, in order to ensure that the heat conductive metal layer 19b is not damaged in the process of cutting the package structure 100 after forming the heat conductive metal layer 19b, a protective film 20 is adhered on the surface of the heat conductive metal layer 19b, and the package structure 100 is cut by a cutting tool 21 to obtain a module 110b with a heat dissipation metal layer 19b formed on the surface, where the module 110b may include one chip 1 or a plurality of chips 1.
Referring to fig. 4A-4D, the present application further provides a manufacturing process of depositing a heat conducting metal layer 19a at least on the back side of the chip, specifically:
coating a photoresist 10 on the back surface of the packaging structure 100, so that the photoresist 12 covers the back surface of the chip 1 and the plastic package body 10; referring to fig. 4A, the photoresist 12 is patterned to form an opening exposing the back surface of the chip 1, and specifically, a patterned photoresist layer 12A may be formed on the back surface of the package structure 100 by an exposure and development method, where the photoresist layer 12A is formed with an opening exposing the back surface of the chip 1, and specifically, the photoresist layer 12A must completely cover the plastic package body 10, and within a certain range, the photoresist layer 12A may properly cover the back surface of the chip 1, so as to ensure that the heat conductive metal layer 19a formed in the opening subsequently does not cover the plastic package body 10.
Referring to fig. 4B, the heat conductive metal layer 19a is deposited in the opening, and the photoresist 12A is removed. Specifically, the heat conducting metal layer 19a may be formed on the back surface of the chip 1 exposed in the opening by sputtering, evaporation, chemical plating, electroplating, or the like, and since the heat conducting metal layer 19a is not formed on the plastic package body 10, the problem of separation due to unreliable connection between the heat conducting metal layer 19a and the plastic package body 10 does not occur, and the heat conducting metal layer 19a is formed on the back surface of the chip 1, and can also transfer heat generated by the chip 1 out, and then the photoresist layer 12A is removed, so that the flatness of the heat conducting metal layer 19a can be ensured, and subsequent processing is facilitated.
Referring to fig. 4C, a schematic diagram of performing a dividing process on the package structure 100 having the heat conductive metal layer 19a formed on the surface thereof is shown, and the operation method is the same as that described above, and is not repeated here.
Referring to fig. 4D, in order to obtain the module 110a with the heat-conducting metal layer 19a formed on the back surface by the cutting process as shown in fig. 4C, the module 110a may include one chip 1, or may include a plurality of chips 1.
Referring again to fig. 1, S3, a heat sink is disposed on the heat conductive metal layer, the heat sink being in heat-conducting connection with the heat conductive metal layer.
Specifically, the specific forming process is as follows: referring to fig. 4F and 4G, a metal bonding layer 15 is disposed on the heat conducting metal layer 19a of the obtained module 110a, and then a heat sink 16 is disposed on the metal bonding layer 15, the material of the metal bonding layer 15 includes, but is not limited to, a gold-silicon alloy, a gold-tin alloy, and a gold-germanium alloy, the heat conducting metal layer and the heat sink 16 may be bonded by the metal bonding layer 15, the metal bonding layer 15 may be a prefabricated part, so as to reduce the processing cost, specifically, the formed metal sheet may be attached to the heat conducting metal layers 19a and 19b, then the heat sink 16 is attached to the metal sheet, and then the heat sink 16 and the heat conducting metal layer 19a are fixed and thermally connected by reflow soldering.
In some embodiments, referring to fig. 4E, after obtaining the module 110a, the chip 1 of the module 110a is flip-chip mounted on the substrate 14, the carrying surface of the substrate 14 is provided with connection points (not shown) communicating with the functional surfaces of the modules 110a and 110b, and the substrate is internally provided with circuit structures (not shown) communicating with solder balls on the back surface of the substrate. The heat sink 16 includes a first portion partially in contact with the metal bonding layer 15, wherein the surface area of the first portion is larger than that of the metal bonding layer 15, thereby improving heat dissipation efficiency; as a preferred embodiment, the heat dissipation member 16 may further include a second portion between the first portion and the substrate, the second portion may increase the surface area of the heat dissipation member 16 and increase the heat dissipation efficiency, and the second portion may protect the chip; in addition, an adhesive can be arranged at the contact part of the second part and the substrate, so that a fixing point is provided for the heat dissipation piece 16, and the connection strength of the heat dissipation piece 16 and the substrate is ensured; in an actual production process, the metal bonding layer 15 is arranged on the heat conducting metal layer 19a, then the heat dissipation element 16 is arranged on the metal bonding layer 15, a first part of the heat dissipation element 16 is in contact with the metal bonding layer 15, then the whole body is subjected to reflow soldering, the heat dissipation element 16 and the heat conducting metal layer 19a are both fixed and in heat conduction connection with the metal bonding layer 15, the heat dissipation element 10 is made of a metal piece, and the material of the heat dissipation element can be copper.
Referring to fig. 5F-5I, a structure diagram of disposing a heat sink on the surface of the module 110b obtained by the above division is shown, and a specific forming method thereof is the same as that described above, and is not repeated here.
Referring to fig. 4G and fig. 5I, in a second aspect, the present application further provides a package structure, including: at least one chip 1, wherein a plastic package body 10 is surrounded on the side surface of the chip 1; heat conductive metal layers 19a, 19 b; the heat dissipation member 16 is formed at least on the back surface of the chip 1, and is disposed on the heat conductive metal layers 19a and 19b, and the heat dissipation member 16 is connected to the heat conductive metal layers 19a and 19b in a heat conduction manner. In some embodiments, the chip 1 is flip-chip mounted on the substrate 14 and electrically connected to the connection points on the upper surface of the substrate 14.
Specifically, the heat-conducting metal layers 19a and 19b are arranged on at least the back surface of the chip 1, and the heat-conducting metal layers 19a and 19b are in heat-conducting connection with the heat sink 16, and the heat-conducting connection can be understood as that the heat-conducting metal layers 19a and 19b are in fixed contact connection with the heat sink 16, and a heat-conducting path is formed between the heat-conducting metal layers 19a and 19b and the heat sink 16.
Referring to fig. 4G, the heat-conducting metal layer 19a is only disposed on the back surface of the chip 1, so that the phenomenon of separation and peeling caused by the weak connection between the heat-conducting metal layer 19a and the plastic package body 10 can be avoided, and the requirement of heat dissipation can be met.
Referring to fig. 5I, the heat conductive metal layer 19b further includes a portion located above the plastic package body 10, and a metal adhesion enhancer layer 18 is further formed between the plastic package body 10 and the heat conductive metal layer 19b, specifically, the surface area of the heat conductive metal layer 19b can be increased by disposing the heat conductive metal layer 19b on the surface of the plastic package body 10, so as to improve the heat dissipation effect of the heat conductive metal layer 19b, on the other hand, the metal adhesion enhancer layer 18 disposed between the plastic package body 10 and the heat conductive metal layer 19b can be tightly connected to the heat conductive metal layer 19b and the plastic package body 10, so as to avoid the separation of the heat conductive metal layer 19b from the plastic package body 10, wherein the metal adhesion enhancer may be selected from but not limited to a high phosphate ester polymer and a titanate polymer.
Further, a metal bonding layer 15 is arranged between the heat sink 16 and the heat conducting metal layer 19, and both the heat conducting metal layer 19 and the heat sink 16 are in heat conduction connection with the metal bonding layer 15.
Specifically, in an actual production process, the heat sink 16 and the heat conducting metal layer 19 may be connected by disposing a metal bonding layer 15 between the heat sink 16 and the heat conducting metal layer 19, the material includes, but is not limited to, a gold-silicon alloy, a gold-tin alloy, and a gold-germanium alloy, the heat sink 16 and the heat conducting metal layer 19 are both fixed and thermally conductively connected to the metal bonding layer 15 by reflow soldering, and the heat sink 16 includes a first portion partially contacting the metal bonding layer 15, as a preferred embodiment, the heat sink 16 may further include and a second portion between the first portion and the substrate, and the second portion may increase the surface area of the heat sink 16 and increase the heat dissipation efficiency on one hand, and may protect the chip on the other hand; in an actual production process, the metal bonding layer 15 is arranged on the heat conducting metal layers 19a and 19b, the heat dissipation element 16 is arranged on the metal bonding layer 15, the first part of the heat dissipation element 16 is in contact with the metal bonding layer 15, then the whole body is subjected to reflow soldering, the heat dissipation element 16 and the heat dissipation metal layers 19a and 19b are both fixed and in heat conduction connection with the metal bonding layer 15, the heat dissipation element is made of metal pieces, and the material of the heat dissipation element can be copper.
The above description is only a preferred embodiment of the application and is illustrative of the principles of the technology employed. It will be appreciated by a person skilled in the art that the scope of the invention as referred to in the present application is not limited to the embodiments with a specific combination of the above-mentioned features, but also covers other embodiments with any combination of the above-mentioned features or their equivalents without departing from the inventive concept. For example, the above features may be replaced with (but not limited to) features having similar functions disclosed in the present application.
Claims (10)
1. A method of packaging, comprising:
providing a packaging structure, wherein the packaging structure comprises at least one chip and a plastic package body wrapping the side face of the chip;
depositing a heat-conducting metal layer at least on the back surface of the chip;
and a heat dissipation piece is arranged on the heat conduction metal layer and is in heat conduction connection with the heat conduction metal layer.
2. The method according to claim 1, characterized in that said depositing a layer of heat conducting metal at least on the back side of the chip, in particular:
coating photoresist on the back surface of the chip, patterning the photoresist to form an opening exposing the plastic package body, and arranging a metal adhesion enhancer layer in the opening;
removing the photoresist;
and depositing the heat-conducting metal layer, wherein the heat-conducting metal layer covers the back surface of the chip and the plastic package body.
3. The method of claim 2, wherein the material of the metal adhesion promoter layer comprises a high phosphate polymer, a titanate-based polymer.
4. The method according to claim 1, characterized in that said depositing a layer of heat conducting metal at least on the back side of the chip, in particular:
coating photoresist on the back surface of the chip, patterning the photoresist to form an opening exposing the back surface of the chip, depositing the heat-conducting metal layer in the opening, and removing the photoresist.
5. The method of any one of claims 1-4, wherein the material of the thermally conductive metal layer comprises at least one of gold, silver, copper, chromium, titanium, nickel, and palladium.
6. The method of claim 1, wherein between depositing a layer of thermally conductive metal at least on the back side of the chip and disposing a heat spreader on the layer of thermally conductive metal comprises:
and providing a substrate, and inversely installing the chip with the heat-conducting metal layer deposited on the back surface on the substrate.
7. The method of any of claims 1-4, wherein disposing a heat sink on the thermally conductive metal layer comprises:
a metal bonding layer is arranged between the heat-conducting metal layer and the heat dissipation piece;
and carrying out heat treatment on the structure to ensure that the heat-conducting metal layer and the heat radiating piece are in heat conduction connection with the metal bonding layer.
8. The method of claim 7, wherein the metal bonding layer comprises a gold alloy comprising a gold-silicon alloy, a gold-tin alloy, a gold-germanium alloy.
9. A package structure formed according to the method of any one of claims 1-8, comprising:
the chip comprises at least one chip, wherein a plastic package body is surrounded on the side face of the chip;
a heat-conducting metal layer; the heat dissipation structure is at least formed on the back surface of the chip, a heat dissipation part is arranged on the heat conduction metal layer, and the heat dissipation part is in heat conduction connection with the heat conduction metal layer.
10. The package structure of claim 9, wherein the heat conductive metal layer further comprises a portion located above the molding compound, and a metal adhesion enhancer layer is further formed between the molding compound and the heat conductive metal layer.
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| CN202011042495.6A CN112435969A (en) | 2020-09-28 | 2020-09-28 | Packaging method and packaging structure |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202011042495.6A CN112435969A (en) | 2020-09-28 | 2020-09-28 | Packaging method and packaging structure |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113327899A (en) * | 2021-04-22 | 2021-08-31 | 成都芯源系统有限公司 | Flip chip packaging unit and packaging method |
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| CN111312670A (en) * | 2020-02-26 | 2020-06-19 | 南通智通达微电子物联网有限公司 | Heat dissipation packaging method |
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