CN112397401A - 用于制造半导体封装的方法 - Google Patents

用于制造半导体封装的方法 Download PDF

Info

Publication number
CN112397401A
CN112397401A CN202010816812.9A CN202010816812A CN112397401A CN 112397401 A CN112397401 A CN 112397401A CN 202010816812 A CN202010816812 A CN 202010816812A CN 112397401 A CN112397401 A CN 112397401A
Authority
CN
China
Prior art keywords
layer
semiconductor chip
forming
carrier substrate
etch stop
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202010816812.9A
Other languages
English (en)
Inventor
金茶譓
金东奎
朴正镐
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of CN112397401A publication Critical patent/CN112397401A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76865—Selective removal of parts of the layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/32—Holders for supporting the complete device in operation, i.e. detachable fixtures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/162—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits the devices being mounted on two or more different substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68372—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support a device or wafer when forming electrical connections thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13109—Indium [In] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13113—Bismuth [Bi] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13116—Lead [Pb] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/13118—Zinc [Zn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/1312—Antimony [Sb] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H01L2224/21—Structure, shape, material or disposition of high density interconnect preforms of an individual HDI interconnect
    • H01L2224/214—Connecting portions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/83005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/85005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06572—Auxiliary carrier between devices, the carrier having an electrical connection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1041—Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

一种用于制造半导体封装的方法包括在第一载体基板上形成离型层。蚀刻停止层在离型层上形成。第一再分布层在蚀刻停止层上形成，并包括多条第一布线和围绕所述多条第一布线的第一绝缘层。第一半导体芯片在第一再分布层上形成。焊料球在第一再分布层与第一半导体芯片之间形成。第二载体基板在第一半导体芯片上形成。去除第一载体基板、离型层和蚀刻停止层。去除第二载体基板。

Description

用于制造半导体封装的方法
技术领域
本公开涉及用于制造半导体封装的方法。
背景技术
近年来，随着对高性能电子装置的消费者需求增加，半导体芯片和半导体封装的尺寸增加。然而，由于近来趋向于相对薄的电子装置的趋势，半导体封装的厚度减小。
开发半导体封装以提供改善的性能从而满足对多功能、高容量和小型化的需求。例如，多个半导体芯片可以集成到单个半导体封装中，因此，可以在显著地减小半导体封装的尺寸的同时实现高容量和多功能。
发明内容
本发明构思将实现的目的是提供用于制造半导体封装的方法，该方法在载体基板与再分布层之间形成包括金属的蚀刻停止层，从而防止再分布层在载体基板的剥离工艺中被损坏。
根据本发明构思的一示例性实施方式，一种用于制造半导体封装的方法包括在第一载体基板上形成离型层(release layer)。蚀刻停止层在离型层上形成。第一再分布层在蚀刻停止层上形成，并包括多条第一布线和围绕所述多条第一布线的第一绝缘层。第一半导体芯片在第一再分布层上形成。焊料球在第一再分布层与第一半导体芯片之间形成。第二载体基板在第一半导体芯片上形成。去除第一载体基板、离型层和蚀刻停止层。去除第二载体基板。
根据本发明构思的一示例性实施方式，一种用于制造半导体封装的方法包括在第一载体基板上形成离型层。包括金属的蚀刻停止层在离型层上形成。第一再分布层在蚀刻停止层上形成。第一再分布层包括多条第一布线和围绕所述多条第一布线的第一绝缘层。第一半导体芯片在第一再分布层上形成。焊料球在第一再分布层与第一半导体芯片之间形成。形成覆盖第一半导体芯片的模制层。去除第一载体基板、离型层和蚀刻停止层。离型层和第一绝缘层包括相同的材料。
根据本发明构思的一示例性实施方式，一种用于制造半导体封装的方法包括在第一载体基板上形成离型层。包括金属的蚀刻停止层在离型层上形成。第一再分布层在蚀刻停止层上形成。第一再分布层包括多条第一布线和围绕所述多条第一布线的第一绝缘层。第一半导体芯片在第一再分布层上形成。焊料球在第一再分布层与第一半导体芯片之间形成。形成覆盖第一半导体芯片的模制层。第二载体基板在模制层上形成。去除第一载体基板、离型层和蚀刻停止层。去除第二载体基板。离型层和第一绝缘层包括相同的材料。
旨在由本发明构思解决的目的不限于上述目的，并且以上未提及的其他目的可以基于以下提供的描述被本领域技术人员清楚地理解。
附图说明
通过参照附图详细描述本发明构思的示例性实施方式，本发明构思的以上及其他目的、特征和优点将对本领域普通技术人员变得更加明显，附图中：
图1是根据本发明构思的一示例性实施方式的半导体封装的剖视图；
图2至图8是示出根据本发明构思的示例性实施方式的用于制造半导体封装的方法的剖视图；
图9和图10是示出根据本发明构思的其他示例性实施方式的用于制造半导体封装的方法的剖视图；
图11至图14是示出根据本发明构思的示例性实施方式的用于制造半导体封装的方法的剖视图；
图15至图18是示出根据本发明构思的另一些示例性实施方式的用于制造半导体封装的方法的剖视图；
图19是根据本发明构思的一示例性实施方式的半导体封装的剖视图；以及
图20是根据本发明构思的一示例性实施方式的半导体封装的剖视图。
具体实施方式
根据本发明构思的一些示例性实施方式，用于制造半导体封装的方法可以包括制造扇出封装。例如，半导体芯片可以形成在再分布层上。半导体芯片可以通过再分布层和形成在再分布层上的焊料球电连接到外部装置。然而，本发明构思的示例性实施方式不限于此。在本说明书中，术语“形成在……上”和“设置在……上”意思是一元件直接形成在另一元件上或该元件间接形成在所述另一元件上且存在一个或更多个居间的元件/层。术语“直接形成在……上”意思是一元件直接形成在另一元件上而不存在居间的元件/层。
在下文中，将参照图1描述通过根据本发明构思的一些示例性实施方式的用于制造半导体封装的方法制造的半导体封装。
图1是提供为解释通过根据本发明构思的一示例性实施方式的用于制造半导体封装的方法制造的半导体封装的剖视图。
半导体封装可以包括第一再分布层130、第一半导体芯片140、第一底部填充材料141、第一模制层145、第一焊料球151和第二焊料球152。
第一再分布层130可以包括多条第一布线131、第一再分布通路132和第一绝缘层133。
如图1的示例性实施方式所示，多条第一布线131可以包括在水平方向(例如X方向)上彼此间隔开的多条布线。此外，多条第一布线131还可以包括在垂直方向(例如Y方向)上彼此间隔开的多条布线。例如，多条第一线131可以包括在水平方向上彼此间隔开并形成在不同高度上的多条布线。如图1的示例性实施方式所示，多条第一布线131可以包括水平地布置并形成在三个不同高度上的第一布线131。然而，本发明构思的示例性实施方式不限于此。多个第一再分布通路132在每个高度上形成在第一布线131上并垂直地(例如在Y方向上)延伸，以将在不同的高度上的第一布线131彼此连接。
包括在多条第一布线131中的每条布线可以包括导电材料。例如，包括在多条第一布线131中的每条布线可以包括铜(Cu)。在一示例性实施方式中，包括在多条第一布线131中的每条布线可以包括选自碳(C)、银(Ag)、钴(Co)、钽(Ta)、铟(In)、锡(Sn)、锌(Zn)、锰(Mn)、钛(Ti)、镁(Mg)、铬(Cr)、锗(Ge)、锶(Sr)、铂(Pt)、镁(Mg)、铝(Al)和锆(Zr)的至少一种材料。
第一再分布通路132可以电连接在形成于不同高度上的多条第一布线131之间。第一再分布通路132可以包括导电材料。例如，在一示例性实施方式中，第一再分布通路132可以包括与多条第一布线131的材料相同的材料。然而，本发明构思的示例性实施方式不限于此。
第一绝缘层133可以被布置为分别围绕多条第一布线131和第一再分布通路132。
在一示例性实施方式中，第一绝缘层133可以包括可光成像的电介质(PID)。例如，第一绝缘层133可以包括光敏绝缘材料。在一示例性实施方式中，第一绝缘层133可以包括选自环氧树脂和聚酰亚胺的至少一种化合物。然而，本发明构思的示例性实施方式不限于此。
在一示例性实施方式中，第一半导体芯片140可以是逻辑芯片或存储芯片。在第一半导体芯片140是逻辑芯片的实施方式中，第一半导体芯片140可以是例如中央处理单元(CPU)、控制器、专用集成电路(ASIC)等。然而，本发明构思的示例性实施方式不限于此。
在第一半导体芯片140是存储芯片的实施方式中，第一半导体芯片140可以是例如易失性存储芯片(诸如动态随机存取存储器(DRAM)或静态RAM(SRAM))或非易失性存储芯片(诸如相变RAM(PRAM)、磁阻RAM(MRAM)、铁电RAM(FeRAM)或电阻RAM(RRAM))。然而，本发明构思的示例性实施方式不限于此。
第一焊料球151可以布置在第一再分布层130与第一半导体芯片140之间。例如，如图1的示例性实施方式所示，第一焊料球151可以是(例如在X方向上)间隔开的多个离散的焊料凸块。第一焊料球151可以与暴露在第一再分布层130的上表面上的多条第一布线131接触。例如，如图1的示例性实施方式所示，第一焊料球151的底表面可以直接接触多条第一布线中的位于最高高度上的第一布线131的顶表面。第一焊料球151的顶表面可以接触第一半导体芯片140。例如，在一示例性实施方式中，第一焊料球151的顶表面可以与暴露在第一半导体芯片140的下表面上的导电端子直接接触。
第一半导体芯片140可以通过第一焊料球151与第一再分布层130电连接。然而，本发明构思的示例性实施方式不限于此。例如，在其他示例性实施方式中，第一半导体芯片140可以通过引线键合与第一再分布层130电连接。
在一示例性实施方式中，第一焊料球151可以包括选自锡(Sn)、铟(In)、铅(Pb)、锌(Zn)、镍(Ni)、金(Au)、银(Ag)、铜(Cu)、锑(Sb)、铋(Bi)及其组合的至少一种材料。然而，本发明构思的示例性实施方式不限于此。
第一底部填充材料141可以(例如在Y方向上)布置在第一再分布层130与第一半导体芯片140之间。第一底部填充材料141可以被布置为围绕第一焊料球151的侧表面(例如第一焊料球151的在X方向上的最外横向侧表面)。
第一底部填充材料141可以形成为在横向方向上从第一半导体芯片140的侧表面进一步突出。例如，在一示例性实施方式中，第一底部填充材料的最外横向表面中的至少一个比第一半导体芯片140(例如在X方向上)延伸得更远并且不与第一半导体芯片(例如在Y方向上)重叠。然而，本发明构思的示例性实施方式不限于此。
第一模制层145可以布置在第一再分布层130上。例如，在一示例性实施方式中，第一模制层145可以被布置为围绕第一再分布层130的面对第一半导体芯片140的上表面、第一底部填充材料141的侧表面和第一半导体芯片140的侧表面。
尽管图1的示例性实施方式将第一模制层145的上表面和第一半导体芯片140的上表面示出为(例如在Y方向上)彼此共面，但是本发明构思的示例性实施方式不限于此。例如，在另一示例性实施方式中，第一模制层145的上表面可以被布置为(例如在Y方向上)覆盖第一半导体芯片140的上表面。
在一示例性实施方式中，第一模制层145可以包括环氧模塑料(EMC)或两种或更多种的硅酮杂化材料。
第二焊料球152可以布置在第一再分布层130的下表面上。如图1的示例性实施方式所示，第二焊料球152可以是(例如在X方向上)间隔开的多个离散的焊料凸块。在一示例性实施方式中，第二焊料球152的离散的焊料凸块可以大于第一焊料球151的焊料凸块。然而，本发明构思的示例性实施方式不限于此。如图1的示例性实施方式所示，第二焊料球152的顶表面可以直接接触第一再分布层130的底表面。第二焊料球152可以与暴露在第一再分布层130的下表面上的多条第一布线131接触。第二焊料球152可以从第一再分布层130的下表面凸起地突出。第二焊料球152可以将第一再分布层130电连接到外部装置。例如，外部装置可以电连接到第二焊料球152的一部分(例如底表面或侧表面)，以将外部装置与第一再分布层130电连接。
在一示例性实施方式中，第二焊料球152可以包括例如选自锡(Sn)、铟(In)、铅(Pb)、锌(Zn)、镍(Ni)、金(Au)、银(Ag)、铜(Cu)、锑(Sb)、铋(Bi)及其组合的至少一种材料。然而，本发明构思的示例性实施方式不限于此。
在下文中，将参照图1至图8描述根据一些示例性实施方式的用于制造半导体封装的方法。
图2至图8是被提供为解释根据本发明构思的一些示例性实施方式的用于制造半导体封装的方法的示出制造的中间阶段的剖视图。
参照图2，可以在第一载体基板100上形成离型层110。
在一示例性实施方式中，第一载体基板100可以包括选自硅、金属、玻璃、塑料、陶瓷等的至少一种材料。然而，本发明构思的示例性实施方式不限于此。
离型层110可以与第一载体基板100接触。例如，在一示例性实施方式中，离型层110的底表面可以直接接触第一载体基板100的顶表面。离型层110可以共形地形成在第一载体基板100上。然而，本发明构思的示例性实施方式不限于此。
在一示例性实施方式中，离型层110可以包括与图1所示的第一绝缘层133的材料相同的材料。例如，离型层110可以包括光敏绝缘材料，诸如选自环氧树脂和聚酰亚胺的至少一种化合物。然而，本发明构思的示例性实施方式不限于此。例如，在另一示例性实施方式中，离型层110可以是用于引入稳定的可分离特性的无机离型层。在该实施方式中，离型层110可以是例如碳材料。然而，本发明构思的示例性实施方式不限于此。离型层可以具有第一蚀刻选择性。
此后，可以在离型层110上形成刻蚀停止层120。刻蚀停止层120可以与离型层110接触。例如，刻蚀停止层120的底表面可以直接接触离型层110的顶表面。蚀刻停止层120可以共形地形成在离型层110上。然而，本发明构思的示例性实施方式不限于此。
蚀刻停止层120可以具有第二蚀刻选择性。蚀刻停止层120的第二蚀刻选择性可以小于离型层110的第一蚀刻选择性。因此，可以在后续工艺中选择性地去除第一载体基板100和离型层110。
在一示例性实施方式中，蚀刻停止层120可以包括金属。例如，蚀刻停止层120可以包括钛(Ti)。然而，本发明构思的示例性实施方式不限于此。例如，在另一示例性实施方式中，蚀刻停止层120可以包括具有比离型层110的蚀刻选择性小的蚀刻选择性的其他金属。
在一示例性实施方式中，蚀刻停止层120在Y方向上的厚度t1可以是例如约100nm至约500nm。例如，蚀刻停止层120的厚度t1可以近似为约225nm至约375nm。然而，本发明构思的示例性实施方式不限于此。
参照图3，可以在蚀刻停止层120上形成第一再分布层130。例如，第一再分布层130的底表面可以直接接触蚀刻停止层120的顶表面。
第一再分布层130可以包括多条第一布线131、连接多条第一布线131中的每条的第一再分布通路132以及围绕多条第一布线131和第一再分布通路132的第一绝缘层133。
参照图4，可以在第一再分布层130上形成第一半导体芯片140。在一示例性实施方式中，第一半导体芯片140可以是例如逻辑芯片或存储芯片。第一半导体芯片140可以通过第一焊料球151与第一再分布层130电连接。
在图4的示例性实施方式中，第一半导体芯片140通过第一焊料球151与第一再分布层130电连接。然而，本发明构思的示例性实施方式不限于此。例如，在另一示例性实施方式中，第一半导体芯片140可以通过引线键合与第一再分布层130电连接。
参照图5，第一底部填充材料141可以被形成为在第一再分布层130与第一半导体芯片140之间围绕第一焊料球151的侧表面(例如第一焊料球151的在X方向上的最外横向侧表面)。
然后，可以形成第一模制层145以覆盖第一半导体芯片140。例如，在一示例性实施方式中，第一模制层145可以被布置为围绕第一半导体芯片140的(例如在X方向上的)侧表面和(例如在Y方向上的)上表面、第一底部填充材料141的(例如在X方向上的)侧表面以及第一再分布层130的(例如在Y方向上的)上表面。
第一半导体芯片140的上表面可以通过经由平坦化工艺蚀刻第一模制层145的一部分而暴露。在一示例性实施方式中，在平坦化工艺之后，第一模制层145的上表面可以与第一半导体芯片140的上表面共面。然而，本发明构思的示例性实施方式不限于此。例如，在另一示例性实施方式中，通过平坦化工艺，第一模制层145的顶表面可以形成在比第一半导体芯片140的顶表面(例如在Y方向上的)更高的高度处。因此，在平坦化工艺之后，第一模制层145的顶表面可以覆盖第一半导体芯片140的上表面。
参照图6，可以在第一半导体芯片140和第一模制层145上形成第二载体基板160。例如，如图6的示例性实施方式所示，第二载体基板160的底表面可以直接接触半导体芯片140的顶表面和第一模制层145的顶表面。在一示例性实施方式中，第二载体基板160可以包括选自硅、金属、玻璃、塑料、陶瓷等的至少一种材料。然而，本发明构思的示例性实施方式不限于此。
参照图7，在形成第二载体基板160之后，将装置上下颠倒。
然后，可以去除第一载体基板100和离型层110。例如，在一示例性实施方式中，可以通过激光剥离工艺去除第一载体基板100和离型层110。然而，本发明构思的示例性实施方式不限于此。
在去除第一载体基板100和离型层110的工艺中，由于具有比离型层110的蚀刻选择性小的蚀刻选择性的蚀刻停止层120，可以防止对第一再分布层130的损坏。
参照图8，然后，可以去除蚀刻停止层120以暴露第一再分布层130。在去除蚀刻停止层120之后，可以在暴露的第一再分布层130上形成第二焊料球152。
参照图1，在形成第二焊料球152之后，可以将装置上下颠倒，使得第二载体基板160设置于(例如在Y方向上的)顶部。然后，可以去除第二载体基板160。
然后，可以通过锯切工艺来制造图1所示的半导体封装。
在一示例性实施方式中，用于制造半导体封装的方法包括在第一载体基板100与第一再分布层130之间形成包括金属的蚀刻停止层120，从而防止第一再分布层130在第一载体基板100的剥离工艺中被损坏。
在下文中，将参照图9和图10描述根据另一些示例性实施方式的用于制造半导体封装的方法。将重点突出与图1至图8所示的用于制造半导体封装的方法的不同之处。
图9和图10是被提供为解释根据本发明构思的另一些示例性实施方式的用于制造半导体封装的方法的示出制造的中间阶段的剖视图。
参照图9，在根据另一些示例性实施方式的用于制造半导体封装的方法中，可以在第一载体基板100上依次形成离型层110、蚀刻停止层120和金属层270。
金属层270可以与蚀刻停止层120接触。例如，如图9的示例性实施方式所示，金属层270的底表面可以直接接触蚀刻停止层120的顶表面。金属层270可以共形地形成在蚀刻停止层120上。然而，本发明构思的示例性实施方式不限于此。
金属层270可以包括与蚀刻停止层120的材料不同的材料。例如，金属层270可以包括与图10所示的多条第一布线131的材料相同的材料。在一示例性实施方式中，金属层270可以包括选自碳(C)、银(Ag)、钴(Co)、钽(Ta)、铟(In)、锡(Sn)、锌(Zn)、锰(Mn)、钛(Ti)、镁(Mg)、铬(Cr)、锗(Ge)、锶(Sr)、铂(Pt)、镁(Mg)、铝(Al)和锆(Zr)的至少一种材料。
金属层270在第二方向Y上的厚度t2可以为例如约50nm至约350nm。然而，本发明构思的示例性实施方式不限于此。
参照图10，可以在金属层270上形成第一再分布层130。例如，如图10的示例性实施方式所示，第一再分布层130的底表面可以直接接触金属层270的顶表面。
第一再分布层130可以包括多条第一布线131、连接多条第一布线131中的每条的第一再分布通路132以及围绕多条第一布线131和第一再分布通路132的第一绝缘层133。
在一示例性实施方式中，可以通过使用金属层270作为籽晶层来形成与金属层270接触的多条第一布线131中的布线。
执行图4至图8所示的工艺之后，可以制造图1所示的半导体封装。
在下文中，将参照图11至图14描述根据另一些示例性实施方式的用于制造半导体封装的方法。将重点突出与图1至图8所示的用于制造半导体封装的方法的不同之处。
图11至图14是被提供为解释根据本发明构思的示例性实施方式的用于制造半导体封装的方法的示出制造的中间阶段的剖视图。
参照图11，在根据一些示例性实施方式的用于制造半导体封装的方法中，在执行图2至图5所示的工艺之后，可以形成在第二方向Y上穿透第一模制层145的通路380。例如，如图11的示例性实施方式所示，通路380可以包括在Y方向上延伸并在X方向上布置的多个离散的通路。通路380可以从第一再分布层130的顶部(例如，在第一再分布层130的顶部处暴露的第一布线131的顶表面)延伸到第一模制层145的顶表面。如图11的示例性实施方式所示，通路380可以与第一半导体芯片140的(例如在X方向上的)横向侧表面相邻地形成，并在平行于第一载体基板100的上表面的方向上与第一半导体芯片140和第一底部填充材料141间隔开。
通路380可以与暴露在第一再分布层130的上表面上的多条第一布线131电连接。
通路380可以包括导电材料。在一示例性实施方式中，通路380可以包括例如铜(Cu)。在另一示例性实施方式中，通路380可以包括选自碳(C)、银(Ag)、钴(Co)、钽(Ta)、铟(In)、锡(Sn)、锌(Zn)、锰(Mn)、钛(Ti)、镁(Mg)、铬(Cr)、锗(Ge)、锶(Sr)、铂(Pt)、镁(Mg)、铝(Al)和锆(Zr)的至少一种材料。
参照图12，可以在第一半导体芯片140上形成第二半导体芯片340。在一示例性实施方式中，第二半导体芯片340可以是存储芯片。例如，第二半导体芯片340可以是易失性存储芯片(诸如动态随机存取存储器(DRAM)或静态RAM(SRAM))或非易失性存储芯片(诸如相变RAM(PRAM)、磁阻RAM(MRAM)、铁电RAM(FeRAM)或电阻RAM(RRAM))。然而，本发明构思的示例性实施方式不限于此。
可以(例如在Y方向上)在通路380与第二半导体芯片340之间设置第三焊料球353。如图12的示例性实施方式所示，第三焊料球353可以是(例如在X方向上)间隔开的多个离散的焊料凸块。第三焊料球353可以与暴露在第一模制层145上的通路380接触。例如，如图12的示例性实施方式所示，第三焊料球353的底表面可以直接接触通路的顶表面，并且第三焊料球353的顶表面可以直接接触第二半导体芯片的底表面。在一示例性实施方式中，第三焊料球353可以直接接触暴露在第二半导体芯片340的下表面上的导电端子。
第二半导体芯片340可以通过第三焊料球353和通路380与第一再分布层130电连接。
参照图13，可以在第一模制层上形成第二模制层385以覆盖第二半导体芯片340。
第二模制层385可以形成为围绕第一模制层145的上表面、第一半导体芯片140的上表面、第三焊料球353以及第二半导体芯片340的上表面、侧表面和底表面。
第二模制层385可以包括例如环氧模塑料(EMC)或两种或更多种硅酮杂化材料。
然后，可以在第二模制层385上形成第二载体基板160。
参照图14，在依次执行图7和图8所示的工艺之后，可以制造图14所示的半导体封装。
例如，在形成第二载体基板160之后，可以将装置上下颠倒。然后，可以去除第一载体基板100、离型层110和蚀刻停止层120，然后，可以在第一再分布层130上形成第二焊料球152。
然后，可以将装置上下颠倒，然后，可以去除第二载体基板160。然后，可以通过锯切工艺来制造图14所示的半导体封装。
在下文中，将参照图15至图18描述根据本发明构思的另一些示例性实施方式的用于制造半导体封装的方法。将重点突出与图1至图8所示的用于制造半导体封装的方法的不同之处。
图15至图18是被提供为解释根据另一些示例性实施方式的用于制造半导体封装的方法的示出制造的中间阶段的剖视图。
参照图15，在根据另一些示例性实施方式的用于制造半导体封装的方法中，在执行图2至图5所示的工艺之后，可以形成在第二方向Y上穿透第一模制层145的通路480。如图15的示例性实施方式所示，通路480可以形成在第一半导体芯片140的(例如在X方向上的)横向侧上，并在X方向上与第一半导体芯片140和第一底部填充材料141间隔开。
然后，可以在第一半导体芯片140、第一模制层145和通路480上形成第二再分布层490。
第二再分布层490可以包括多条第二布线491、连接多条第二布线491中的每条的第二再分布通路492以及围绕多条第二布线491和第二再分布通路492的第二绝缘层493。虽然图15的示例性实施方式所示的第二布线491包括形成于(例如在Y方向上的)两个高度上的被水平布置的第二布线491，但是本发明构思的示例性实施方式不限于此。例如，在其他示例性实施方式中，第二布线491可以形成在三个或更多个高度上。
暴露在第二再分布层490的下表面上的多条第二布线491可以与通路480电连接。例如，第二布线491的底表面可以接触通路480的顶表面。
参照图16，可以在第二再分布层490上形成第二半导体芯片440。在一示例性实施方式中，第二半导体芯片440可以是存储芯片。
可以(例如在Y方向上)在第二再分布层490与第二半导体芯片440之间形成第三焊料球453。例如，第三焊料球453的底表面可以接触第二再分布层490的顶表面，并且第三焊料球453的顶表面可以接触第二半导体芯片440的底表面。在一示例性实施方式中，第三焊料球453可以与暴露在第二再分布层490上的导电端子接触。第三焊料球453也可以与暴露在第二半导体芯片440的下表面上的导电端子接触。
第二半导体芯片440可以通过第三焊料球453、第二再分布层490和通路480与第一再分布层130电连接。
参照图17，可以在第二再分布层490上形成第二模制层485以覆盖第二半导体芯片440。
第二模制层485可以形成为围绕第二再分布层490的上表面、第三焊料球453以及第二半导体芯片440的上表面、下表面和侧表面。
在一示例性实施方式中，第二模制层485可以包括环氧模塑料(EMC)或两种或更多种的硅酮杂化材料。然而，本发明构思的示例性实施方式不限于此。
然后，可以在第二模制层485上形成第二载体基板160。
参照图18，在依次执行图7和图8所示的工艺之后，可以制造图18所示的半导体封装。
例如，在形成第二载体基板160之后，将装置上下颠倒。
然后，可以去除第一载体基板100、离型层110和蚀刻停止层120，并且可以在第一再分布层130上形成第二焊料球152。
然后，可以将装置上下颠倒，然后，可以去除第二载体基板160。然后，可以通过锯切工艺来制造图18所示的半导体封装。
在下文中，将参照图19描述根据另一些示例性实施方式的用于制造半导体封装的方法。将重点突出与图1至图8所示的用于制造半导体封装的方法的不同之处。
图19是被提供为解释通过根据本发明构思的另一些示例性实施方式的用于制造半导体封装的方法制造的半导体封装的剖视图。
参照图19，在根据另一些示例性实施方式的用于制造半导体封装的方法中，在依次执行图2至图5、图11和图6至图8以及图1所示的工艺之后，可以在第一封装10上形成第二封装20。
在一示例性实施方式中，第二封装20可以包括基板21、第二半导体芯片22、第四焊料球23、第二底部填充材料24和第二模制层25。
在一示例性实施方式中，基板21可以是印刷电路板(PCB)或陶瓷基板。此外，基板21可以是中介层。然而，本发明构思的示例性实施方式不限于此。
在一示例性实施方式中，第二半导体芯片22可以是存储芯片。第四焊料球23可以(例如在Y方向上)形成在基板21与第二半导体芯片22之间。例如，如图19的示例性实施方式所示，第四焊料球23可以是(例如在X方向上)间隔开的多个离散的焊料凸块。如图19的示例性实施方式所示，第四焊料球23的底表面可以接触基板21的顶表面，并且第四焊料球23的顶表面可以接触第二半导体芯片22的底表面。例如，在一示例性实施方式中，第四焊料球23的底表面可以与暴露在基板21上的导电端子接触。第四焊料球23的顶表面可以与布置在第二半导体芯片22的下表面上的导电端子接触。
第二底部填充材料24可以形成为围绕基板21与第二半导体芯片22之间的第四焊料球23的侧表面(例如第四焊料球23的在X方向上的最外横向侧表面)。第二模制层25可以形成为围绕基板21的面对第二半导体芯片22的上表面、第二底部填充材料24的侧表面以及第二半导体芯片22的上表面和侧表面。
第三焊料球553可以(例如在Y方向上)形成在通路580与基板21之间。第三焊料球553(例如在Y方向上的底表面)可以与暴露在第一模制层145上的通路580接触。此外，第三焊料球553(例如在Y方向上的顶表面)可以与基板21的下表面(诸如暴露在基板21的下表面上的导电端子)接触。
第二封装20可以通过第三焊料球553与第一封装10电连接。
在下文中，将参照图20描述根据本发明构思的另一些示例性实施方式的用于制造半导体封装的方法。将重点突出与图1至图8所示的用于制造半导体封装的方法的不同之处。
图20是被提供为解释通过根据另一些示例性实施方式的用于制造半导体封装的方法制造的半导体封装的剖视图。
参照图20，在根据本发明构思的另一些示例性实施方式的用于制造半导体封装的方法中，在执行图2至图5、图15和图6至图8以及图1所示的工艺之后，可以在第二再分布层690上形成第二封装20。
第二再分布层690可以包括多条第二布线691、连接多条第二布线691中的每条的第二再分布通路692以及围绕多条第二布线691和第二再分布通路692的第二绝缘层693。虽然图20的示例性实施方式所示的第二布线691包括形成于(例如在Y方向上的)两个高度上的被水平布置的第二布线691，但是本发明构思的示例性实施方式不限于此。例如，在其他示例性实施方式中，第二布线691可以形成在三个或更多个高度上。
第二封装20可以包括基板21、第二半导体芯片22、第四焊料球23、第二底部填充材料24和第二模制层25。
在一示例性实施方式中，第二半导体芯片22可以是存储芯片。第四焊料球23可以(例如在Y方向上)形成在基板21与第二半导体芯片22之间。如图20的示例性实施方式所示，第四焊料球23的底表面可以接触基板21的顶表面，并且第四焊料球23的顶表面可以接触第二半导体芯片22的底表面。在一示例性实施方式中，第四焊料球23的底表面可以接触暴露在基板21的顶表面上的导电端子，并且第四焊料球23的顶表面可以接触暴露在第二半导体芯片22的下表面上的导电端子。
第二底部填充材料24可以形成为围绕基板21与第二半导体芯片22之间的第四焊料球23的侧表面(例如第四焊料球23的在X方向上的最外横向侧表面)。第二模制层25可以形成为围绕基板21的面对第二半导体芯片22的上表面、第二底部填充材料24的侧表面以及第二半导体芯片22的上表面和侧表面。
第三焊料球653可以(例如在Y方向上)形成在第二再分布层690与基板21之间。如图20的示例性实施方式所示，第三焊料球653的顶表面可以接触基板21的底表面，并且第三焊料球653的底表面可以接触第二再分布层的顶表面。例如，在一示例性实施方式中，第三焊料球653的底表面可以接触暴露在第二再分布层690上的导电端子，并且第三焊料球653的顶表面可以接触暴露在基板21的下表面上的导电端子。
第二封装20可以通过第三焊料球653和第二再分布层690与第一封装10电连接。
以上参照附图解释了根据本发明构思的示例性实施方式，但是应理解，本发明构思不限于前述示例性实施方式，而是可以以各种不同的形式制造，并且可以由本领域技术人员在不更改本发明构思的技术构思或基本特征的情况下以其他特定形式实现。因此，将理解，上述示例性实施方式仅是说明性的，并且不应被解释为限制性的。
本申请要求享有2019年8月14日在韩国知识产权局(KIPO)提交的韩国专利申请第10-2019-0099323号的优先权，该韩国专利申请的公开内容通过引用全文合并于此。

Claims (20)

1.一种用于制造半导体封装的方法，所述方法包括：
在第一载体基板上形成离型层；
在所述离型层上形成蚀刻停止层；
在所述蚀刻停止层上形成第一再分布层，所述第一再分布层包括多条第一布线和围绕所述多条第一布线的第一绝缘层；
在所述第一再分布层上形成第一半导体芯片；
在所述第一再分布层与所述第一半导体芯片之间形成焊料球；
在所述第一半导体芯片上形成第二载体基板；
去除所述第一载体基板、所述离型层和所述蚀刻停止层；以及
去除所述第二载体基板。
2.根据权利要求1所述的方法，其中：
所述离型层具有第一蚀刻选择性；
所述蚀刻停止层具有小于所述第一蚀刻选择性的第二蚀刻选择性；以及
所述蚀刻停止层包括金属。
3.根据权利要求2所述的方法，其中所述蚀刻停止层包括Ti。
4.根据权利要求1所述的方法，还包括：
在所述蚀刻停止层上形成金属层，所述金属层包括与所述蚀刻停止层的材料不同的材料。
5.根据权利要求4所述的方法，其中所述金属层和所述多条第一布线包括相同的材料。
6.根据权利要求1所述的方法，其中所述离型层和所述第一绝缘层包括相同的材料。
7.根据权利要求1所述的方法，其中所述蚀刻停止层的厚度在100nm至500nm的范围内。
8.根据权利要求1所述的方法，还包括：
在所述第一半导体芯片上形成第二半导体芯片，
其中所述第二载体基板形成在所述第二半导体芯片上。
9.根据权利要求8所述的方法，还包括：
形成通路，所述通路与所述第一半导体芯片相邻并且在平行于所述第一载体基板的顶表面的方向上与所述第一半导体芯片间隔开；
其中所述第二半导体芯片连接到所述通路。
10.根据权利要求1所述的方法，还包括：
在所述第一半导体芯片上形成第二再分布层，所述第二再分布层包括多条第二布线和围绕所述多条第二布线的第二绝缘层。
11.根据权利要求10所述的方法，还包括：
在所述第二再分布层上形成第二半导体芯片，
其中所述第二载体基板形成在所述第二半导体芯片上。
12.一种用于制造半导体封装的方法，所述方法包括：
在第一载体基板上形成离型层；
在所述离型层上形成包括金属的蚀刻停止层；
在所述蚀刻停止层上形成第一再分布层，所述第一再分布层包括多条第一布线和围绕所述多条第一布线的第一绝缘层；
在所述第一再分布层上形成第一半导体芯片；
在所述第一再分布层与所述第一半导体芯片之间形成焊料球；
形成覆盖所述第一半导体芯片的模制层；以及
去除所述第一载体基板、所述离型层和所述蚀刻停止层，
其中所述离型层和所述第一绝缘层包括相同的材料。
13.根据权利要求12所述的方法，其中所述蚀刻停止层包括Ti。
14.根据权利要求12所述的方法，还包括：
在所述蚀刻停止层上形成金属层，所述金属层包括与所述蚀刻停止层的材料不同的材料。
15.根据权利要求14所述的方法，其中所述金属层和所述多条第一布线包括相同的材料。
16.根据权利要求14所述的方法，其中所述金属层的厚度在50nm至350nm的范围内。
17.根据权利要求12所述的方法，还包括：
在所述第一半导体芯片上形成第二半导体芯片。
18.一种用于制造半导体封装的方法，所述方法包括：
在第一载体基板上形成离型层；
在所述离型层上形成包括金属的蚀刻停止层；
在所述蚀刻停止层上形成第一再分布层，所述第一再分布层包括多条第一布线和围绕所述多条第一布线的第一绝缘层；
在所述第一再分布层上形成第一半导体芯片；
在所述第一再分布层与所述第一半导体芯片之间形成焊料球；
形成覆盖所述第一半导体芯片的模制层；
在所述模制层上形成第二载体基板；以及
去除所述第一载体基板、所述离型层和所述蚀刻停止层；以及
去除所述第二载体基板，
其中所述离型层和所述第一绝缘层包括相同的材料。
19.根据权利要求18所述的方法，其中所述蚀刻停止层包括Ti。
20.根据权利要求18所述的方法，其中所述蚀刻停止层的厚度为100nm至500nm。
CN202010816812.9A 2019-08-14 2020-08-14 用于制造半导体封装的方法 Pending CN112397401A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020190099323A KR102609302B1 (ko) 2019-08-14 2019-08-14 반도체 패키지의 제조 방법
KR10-2019-0099323 2019-08-14

Publications (1)

Publication Number Publication Date
CN112397401A true CN112397401A (zh) 2021-02-23

Family

ID=74567515

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010816812.9A Pending CN112397401A (zh) 2019-08-14 2020-08-14 用于制造半导体封装的方法

Country Status (3)

Country Link
US (1) US11515260B2 (zh)
KR (1) KR102609302B1 (zh)
CN (1) CN112397401A (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023047946A1 (ja) 2021-09-22 2023-03-30 凸版印刷株式会社 支持体付き基板および半導体装置
KR20240039188A (ko) 2021-09-22 2024-03-26 도판 홀딩스 가부시키가이샤 배선 기판 유닛 및 그 설계 방법

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7268012B2 (en) 2004-08-31 2007-09-11 Micron Technology, Inc. Methods for fabrication of thin semiconductor assemblies including redistribution layers and packages and assemblies formed thereby
JP2007242888A (ja) 2006-03-08 2007-09-20 Sony Corp 半導体パッケージ製造方法
US9460951B2 (en) 2007-12-03 2016-10-04 STATS ChipPAC Pte. Ltd. Semiconductor device and method of wafer level package integration
CN103985826A (zh) * 2014-05-30 2014-08-13 深圳市华星光电技术有限公司 Oled基板的封装方法及oled结构
US9520437B2 (en) * 2014-08-14 2016-12-13 Cbrite Inc. Flexible APS X-ray imager with MOTFT pixel readout and a pin diode sensing element
US9646918B2 (en) 2014-08-14 2017-05-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US9543170B2 (en) * 2014-08-22 2017-01-10 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and methods of forming the same
US9899248B2 (en) 2014-12-03 2018-02-20 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming semiconductor packages having through package vias
US9899285B2 (en) * 2015-07-30 2018-02-20 Semtech Corporation Semiconductor device and method of forming small Z semiconductor package
US9620465B1 (en) 2016-01-25 2017-04-11 Taiwan Semiconductor Manufacturing Company, Ltd. Dual-sided integrated fan-out package
KR102582421B1 (ko) 2016-01-29 2023-09-25 삼성전자주식회사 인쇄회로기판 및 이를 구비한 전자소자 패키지
US9991189B2 (en) * 2016-07-29 2018-06-05 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having a dual material redistribution line
US11177201B2 (en) * 2017-11-15 2021-11-16 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages including routing dies and methods of forming same
US20190182955A1 (en) * 2017-12-13 2019-06-13 Intel Corporation Replaceable on-package memory devices
US11227767B2 (en) * 2018-05-03 2022-01-18 Tokyo Electron Limited Critical dimension trimming method designed to minimize line width roughness and line edge roughness

Also Published As

Publication number Publication date
KR20210020275A (ko) 2021-02-24
US11515260B2 (en) 2022-11-29
KR102609302B1 (ko) 2023-12-01
US20210050298A1 (en) 2021-02-18

Similar Documents

Publication Publication Date Title
US11901348B2 (en) Semiconductor package and method of manufacturing the semiconductor package
US11798906B2 (en) Semiconductor chip
US20190214358A1 (en) Semiconductor device, semiconductor package including semiconductor device, and method of manufacturing semiconductor device
US11955464B2 (en) Semiconductor package having pads with stepped structure
CN113451257A (zh) 半导体封装件
CN112397401A (zh) 用于制造半导体封装的方法
KR20220126883A (ko) 반도체 패키지
KR102517379B1 (ko) 반도체 패키지의 제조 방법
KR20210138223A (ko) 반도체 패키지
KR102283061B1 (ko) 반도체 패키지 및 그 제조 방법
US10804218B2 (en) Semiconductor package
KR102655804B1 (ko) 반도체 패키지
KR102550141B1 (ko) 반도체 패키지
US20220392859A1 (en) Semiconductor chip, semiconductor package including the semiconductor chip, method for manufacturing the semiconductor package
KR102550142B1 (ko) 반도체 패키지
KR102578885B1 (ko) 반도체 패키지
US20230420403A1 (en) Semiconductor package including a plurality of semiconductor chips
US20230090461A1 (en) Semiconductor package
US20240006362A1 (en) Semiconductor device
US20230134541A1 (en) Semiconductor package
US20240136332A1 (en) Semiconductor package and method of manufacturing the same
US20240071996A1 (en) Semiconductor package and method of manufacturing the semiconductor package
US20240112974A1 (en) Semiconductor package
KR20230122719A (ko) 반도체 패키지
KR20240056317A (ko) 반도체 패키지 및 이의 제조 방법

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination