CN112310004A - 半导体封装结构及其制造方法 - Google Patents

半导体封装结构及其制造方法 Download PDF

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CN112310004A
CN112310004A CN202010724266.6A CN202010724266A CN112310004A CN 112310004 A CN112310004 A CN 112310004A CN 202010724266 A CN202010724266 A CN 202010724266A CN 112310004 A CN112310004 A CN 112310004A
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semiconductor device
conductive
semiconductor
package structure
redistribution structure
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马克·杰柏
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Abstract

公开一种半导体封装结构及其制造方法。所述半导体封装结构包括第一半导体装置、重新分布结构、第二半导体装置及多个导电组件。所述第一半导体装置具有有源表面。所述重新分布结构与所述第一半导体装置电连接。所述第二半导体装置结合到所述第一半导体装置的所述有源表面及安置于所述第一半导体装置与所述重新分布结构之间。所述导电组件位于所述第一半导体装置的所述有源表面上及所述第二半导体装置之外，其中所述第一半导体装置通过所述导电组件电连接所述重新分布结构。

Description

半导体封装结构及其制造方法
相关申请交叉引用
本申请要求2019年7月25日提交的第62/878,593号美国临时申请的优先权，所述申请以全文引用的方式并入本文中。
技术领域
本公开大体上涉及半导体封装，且具体来说，涉及一种半导体封装结构及制造所述半导体封装结构的方法。
背景技术
随着装置电气性能继续推动更高效的封装解决方案，将需要解决速度/性能挑战的方法。举例来说，半导体芯片与越来越多的电子组件集成以实现改进的电气性能及附加功能。因此，为了在这些芯片及组件之间进行电连接及信号传输，需要更多中间衬底、重新分布结构、输入/输出(I/O)焊盘及焊料球。所有这些各种信号“接口(interface)”可能形成电损耗(electrical losses)。因此，需要具有可减少这些损耗的封装结构。
发明内容
本公开的实施例提供一种半导体封装结构。所述半导体封装结构包含：第一半导体装置，其具有有源表面；重新分布结构，其与所述第一半导体装置电连接；第二半导体装置，其结合到所述第一半导体装置的所述有源表面及安置于所述第一半导体装置与所述重新分布结构之间；及多个导电组件，其位于所述第一半导体装置的所述有源表面上及所述第二半导体装置之外，其中所述第一半导体装置通过所述导电组件电连接所述重新分布结构。
本公开的实施例提供一种制造半导体封装结构的方法。所述方法包括：提供具有有源表面的第一半导体装置；形成多个导电组件于所述第一半导体装置的所述有源表面上；将第二半导体装置结合到所述第一半导体装置的所述有源表面，其中所述导电组件位于所述第二半导体装置之外；及形成重新分布结构，所述重新分布结构通过所述导电组件与所述第一半导体装置电连接，其中所述第二半导体装置安置于所述第一半导体装置与所述重新分布结构之间。
附图说明
当结合附图阅读时，根据以下详细描述容易地理解本公开的一些实施例的各方面。应注意，各种结构可能未按比例绘制，且出于论述的清楚起见，各种结构的尺寸可任意增大或减小。
图1是根据本公开的实施例的半导体封装结构的截面图。
图1A是根据本公开的实施例的半导体封装结构的截面图。
图2A是展示为图1中所说明的半导体封装结构中的第一及第二半导体装置供电的相对较短路径的示意图。
图2B是相比而言展示为不同半导体封装结构中的第一及第二半导体装置供电的相对较长路径的示意图。
图3A是根据本公开的另一实施例的半导体封装结构的截面图。
图3B是根据本公开的又另一实施例的半导体封装结构的截面图。
图3C是根据本公开的又另一实施例的半导体封装结构的截面图。
图3D是根据本公开的又另一实施例的半导体封装结构的截面图。
图4A及4B是根据本公开的实施例的在图3A中所说明的半导体封装结构中的衬底的示意性俯视图。
图5A是根据本公开的实施例的半导体封装结构的截面图。
图5B是根据本公开的另一实施例的半导体封装结构的截面图。
图6是根据本公开的再另一实施例的半导体封装结构的截面图。
图7A到图7F是各自说明根据本公开的实施例的制造如图1描述及说明的半导体封装结构的方法的一或多个阶段的截面图。
图8A到图8H是各自说明在半导体封装结构中的第一半导体装置与第二半导体装置之间形成结合接头的示例性方法的一或多个阶段的截面图。
图9A是说明根据本公开的另一实施例在半导体封装结构中的第一半导体装置与第二半导体装置之间形成结合接头的方法的截面图。
图9B是说明根据本公开的又另一实施例在半导体封装结构中的第一半导体装置与第二半导体装置之间形成结合接头的方法的截面图。
图9C是说明根据本公开的再另一实施例在半导体封装结构中的第一半导体装置与第二半导体装置之间形成结合接头的方法的截面图。
图10A到图10E是各自说明根据本公开的另一实施例在半导体封装结构中的第一半导体装置与第二半导体装置之间形成结合接头的方法的一或多个阶段的截面图。
图11A到图11E是各自说明根据本公开的又另一实施例的制造半导体封装结构的方法的一或多个阶段的截面图。
图12A到图12C是各自说明根据本公开的另一实施例的制造半导体封装结构的方法的一或多个阶段的截面图。
图13A到图13D是各自说明根据本公开的又另一实施例的制造半导体封装结构的方法的一或多个阶段的截面图。
图14A到图14J是各自说明根据本公开的实施例的制造半导体封装结构的方法的一或多个阶段的截面图。
图15A到图15H是各自说明根据本公开的实施例的制造半导体封装结构的方法的一或多个阶段的截面图。
具体实施方式
贯穿图式及详细描述使用共同参考标号来指示相同或相似元件。根据以下结合附图进行的详细描述将容易地理解本公开的实施例。
相对于某一组件或组件群组或组件或组件群组的某一平面而指定空间描述，例如“上方”、“下方”、“向上”、“左”、“右”、“向下”、“顶部”、“底部”、“垂直”、“水平”、“侧面”、“较高”“较低”、“上部”、“之上”、“之下”等，以用于定向如相关联图中所示的组件。应理解，本文中所使用的空间描述仅出于说明的目的，并且本文中所描述的结构的实际实施方案可以任何取向或方式在空间上布置，其限制条件为本公开的实施例的优点是不会因此布置而有偏差。
以下公开内容提供用于实施所提供主题的不同特征的许多不同实施例或实例。下文描述组件及布置的具体实例以解释本公开的某些方面。当然，这些组件及布置仅为实例且并不意欲进行限制。举例来说，在以下描述中，第一特征在第二特征上方或在第二特征上形成可包含第一特征及第二特征直接接触地形成或安置的实施例，且还可包含附加特征可在第一特征与第二特征之间形成或安置，使得第一特征及第二特征可不直接接触的实施例。另外，本公开内容可在各种实例中重复附图标记及/或字母。这种重复是出于简化及清楚的目的且本身并不指示所论述的各种实施例及/或配置之间的关系。
在根据本公开的半导体封装结构中，例如解耦电容器(decoupling capacitor)、电感器(inductor)等的第二半导体装置直接结合到例如数字处理器(digital processor)的第一半导体装置。通过此种结合配置，减小或最小化通过半导体封装结构的电损耗及阻抗。相比而言，在一些现有方法中，可包含焊料及重新分布结构(redistributionstructures)的中间层或互连层存在于数字处理器与解耦电容器之间。因此可能出现与穿过这些层的传输路径相关联的相对较高损耗及阻抗。在根据本公开的一些实施例中，通过将例如解耦电容器及互连结构的离散组件更靠近数字处理器放置，缩短传输路径同时减小或最小化材料的电阻率，由此增强性能。因此，通过结合配置及紧密布置欲解耦组件(componnets to be decoupled)，可在相对较短的路径中实现第一半导体装置及第二半导体装置的供电及接地，从而导致更少的电损耗。
图1是根据本公开的实施例的半导体封装结构100的截面图。
参考图1，半导体封装结构100包含密封在包封层31中的第一半导体装置11及第二半导体装置12。第一半导体装置11具有第一表面11a(“有源表面”)及与第一表面11a相对的第二表面11b(“背侧表面”)，且包含在第一表面11a处的多个导电焊盘119、多个导电支柱(conductive pillars)112(“导电组件”(conductive elements))及多个导电柱(conductive studs)115。用于电连接的导电支柱112及导电柱115安置于导电焊盘119上。所述导电支柱112(“导电组件”)位于所述第一半导体装置11的所述第一表面11a(“有源表面”)上及所述第二半导体装置12之外。因此，所述第一半导体装置11通过所述导电支柱112(“导电组件”)电连接所述重新分布结构40。第二半导体装置12包含结合到第一半导体装置11的导电柱115上的导电柱125，从而形成第一半导体装置11与第二半导体装置12之间的结合接头(bonded joints)135。半导体封装结构100还包含重新分布结构(redistributionstructure)40，所述重新分布结构40进一步包含介电层42及导电层45。另外，电触点(electrical contacts)81安装在重新分布结构40的表面42a上。如圖1所示，电触点81位在所述重新分布结构40的导电层45上。重新分布结构40及电触点81用于提供第一半导体装置11与外部结构的电连接，所述外部结构可包含其它半导体装置或组件。举例来说，半导体封装结构100可通过电触点81附接到衬底、中介层(interposer)或印刷电路板(printedcircuit board,PCB)。
在一实施例中，第一半导体装置11包含数字处理装置(digital processingdevice)，而第二半导体装置12包含解耦电容器。此外，数字处理装置可包含一或多个通用处理装置，例如，应用程序处理器(application processor)、微处理器(microprocessor)、中央处理单元(central processing unit)或控制器(controller)。或者，数字处理装置可包含一或多个专用处理装置，例如，数字信号处理器(digital signal processor,DSP)、图形处理单元(graphics processing unit)、专用集成电路(application specificintegrated circuit,ASIC)或现场可编程门阵列(field programmable gate array,FGA)。此外，数字处理装置可包含网络处理器(network processor)，所述网络处理器进一步包含核心单元及多个微引擎。另外，数字处理装置可包含通用处理装置及专用处理装置的任何组合。
此外，解耦电容器用于减少噪声(noise)。解耦电容器是用于将电气网络或电路的一部分与另一部分解耦的电容器。由其它电路元件引起的噪声通过电容器分流，从而减小其对其余电路的影响。在根据本公开的实施例中，解耦电容器的Q值与所使用材料及其厚度(体积)有关。当厚度随着尺寸减小趋势而减小时，通过例如减小数字处理器(第一半导体装置11)及解耦电容器(第二半导体装置12)与要通过解耦电容器解耦的电路的部分之间的路径来减小阻抗。
电触点81可包含可布置在球栅阵列(ball grid array,BGA)中的焊料球。或者，电触点81可包含布置在栅格阵列(land grid array,LGA)中的金属焊盘。另外，电触点81可包含布置在针栅阵列(pin grid array,PGA)中的引脚(leads)。此外，电触点81可包含可控塌陷芯片连接(controlled collapse chip connection,C4)凸块，所述C4凸块包含基于铅或无铅的凸块或球。
当半导体封装结构100附接到例如PCB的外部结构时，第一半导体装置11通过其有源表面11a面向PCB而“面向下(face-down)”定向。在此配置中，围绕第二半导体装置12的包封层31的大量部分安置于第一半导体装置11与PCB之间，这提供所需的机械可靠性。此外，通过结合第一半导体装置11及第二半导体装置12，缩短传输路径，同时减小或最小化由于在一些现有方法中存在的中间层而引起的材料电阻率(resitivity of materials)。另外，如下文将参考图2A及2B所论述，通过结合接头135的第一半导体装置11与第二半导体装置12之间的直接连接有助于减少寄生效应(parasitic effects)并因此减少电损耗。
图1A是根据本公开的实施例的半导体封装结构100a的截面图。
参考图1A，半导体封装结构100a类似于图1描述及说明的半导体封装结构100，不同之处在于，举例来说，第二半导体装置12a进一步包含多数个导电通孔(conductivevias)126。所述导电通孔126安置于第二半导体装置12a内，且电连接所述导电柱125和所述导电层45。在一些实施例中，所述导电通孔126可以是硅穿通孔(through silicon vias,TSVs)。
图2A是展示为图1中所说明的半导体封装结构100中的第一半导体装置11及第二半导体装置12供电的相对较短路径的示意图。
参考图2A，当半导体封装结构100附接到例如PCB的外部结构时，通过电触点81中的一个(标记为“81P”)、RDL结构40中的布线路线(未展示)、第一导电支柱112、第一半导体装置11与第二半导体装置12之间的第一结合接头“135P”，及随后第二结合接头135P将来自PCB的用作操作电压的电压V提供给第一半导体装置11，从而形成供电路径(以实线展示)。第一结合接头135P由导电柱125及对应导电柱115形成，因此为第一半导体装置11及第二半导体装置12共有。用于为PCB上的半导体封装结构100中的第一半导体装置11及第二半导体装置12供电的供电路径相对较短。
图2B是相比而言展示为不同半导体封装结构150中的第一及第二半导体装置供电的相对较长路径的示意图。在根据本公开的半导体封装结构100中，第一半导体装置11及第二半导体装置12安置于重新分布结构40的同一侧上。具体来说，第二半导体装置12安置于第一半导体装置11与重新分布结构40之间。参考图2B，半导体封装结构150包含与半导体封装结构100的半导体装置及组件类似的半导体装置及组件。然而，在半导体封装结构150中，第一半导体装置211及第二半导体装置212安置于重新分布结构240的不同侧上。具体来说，重新分布结构240安置于第一半导体装置211与第二半导体装置212之间。
关于供电路径，通过第一电触点81P、RDL结构240上的第一布线路线(未展示)、第一导体125P、第二半导体装置212，及随后第二导体125P、RDL结构240中的第二布线路线(未展示)及第一导电柱115P从PCB朝向第一半导体装置211提供电压V，从而形成供电路径。相较于图2A中所描述及所说明的供电路径，用于为PCB上的半导体封装结构150中的第一半导体装置211供电的供电路径相对较长。
参考图2B描述及说明的半导体封装结构150可采用一种先进的解决方案：使用晶片重新分布(RDL)线制造工艺(wafer redistribution(RDL)line fabrication process)来创建应用程序处理器衬底(application processor substrate)，所述应用程序处理器衬底由于较小通孔尺寸、较低介电材料及较薄层而可能具有较低损耗。挑战在于，底部解耦电容器可能仍具有焊料球且I/O仍必须行进穿过RDL层才能到达安置于底部解耦电容器的顶部上的应用程序处理器裸片。此路径上会发生很多损耗，从而降低性能。另外，底部/顶部附加封装之间的连接可能由于间距而受限。
从电路的角度来看，解耦电容器放置于例如处理器的负载的电力输入节点前方，并且用于绕过噪声(bypass noise)及减少相关电源轨(power supply rail)中的电流尖峰或不足的情况。更远离相关电源或接地引脚放置解耦电容器可能会导致不希望的电感及电阻，因此导致电损耗。相反，更靠近相关电源或接地引脚放置解耦电容器可绕过更多电感，因此导致较低电损耗。在根据本公开的半导体封装结构100中，第二半导体装置12(起解耦电容器的作用)直接结合到第一半导体装置11(处理器)，而无需用于通过另外在一些现有方法(包含半导体封装结构150)中所需的附加中间半导体结构或组件相互电连接的布线。本领域普通技术人员可容易地理解，与图2A中所说明的半导体封装结构100中的相对较短路径相比，图2B中所说明的半导体封装结构150中的相对较长路径可引发更多寄生效应。因此，电损耗在半导体封装结构100中可显著减小。
图3A是根据本公开的另一实施例的半导体封装结构200的截面图。
参考图3A，半导体封装结构200包含都密封在包封层31中的第一半导体装置11、第二半导体装置12及衬底50(“中介层”)。包封层31具有第一表面31a及与第一表面31a相对的第二表面31b。衬底50基本上围绕第一半导体装置11及第二半导体装置12，并且维持(supports)半导体封装结构200中的信号传输。在实施例中，衬底50包含无核心衬底51。或者，衬底50可包含基于晶片的重新分布结构(wafer-based redistribution structure)而不是无核心衬底以适应不同设计规则，并且可使用用于铜通孔的直接重新分布层(RDL)电镀技术。在如本实施例中的无核心衬底的情况下，无核心衬底51包含布线层及与布线层电连接的微通孔。此外，无核心衬底51的第一导电焊盘55(上部焊盘)及第二导电焊盘58(下部焊盘)充当用于将布线层电连接到其它半导体装置、组件或结构的输入/输出(input/output,I/O)焊盘。如图1所示，所述第一导电焊盘55邻近所述包封层31的第一表面31a且与所述重新分布结构40电连接。整个布线层中的通信(communication)是通过微通孔而不是通过电镀穿通孔(plated through holes)实现。信号传输可在无核心衬底51基本上垂直方向上直接穿过。此外，无核心衬底51可有助于额外布线以用于在基本上横向方向上通过不同布线层进行信号传输。此外，无源装置可嵌入无核心衬底51的布线层中，使得可以所需区域效率使用无核心衬底51。
在一些实施例中，无核心衬底51采用连续环或连续矩形的形式。图4A是具有连续矩形形状的示例性无核心衬底51的示意性俯视图。可通过在单独制造工艺中制备完整的矩形无核心衬底，然后通过使用例如激光切割工艺去除其中心部分以容纳第一半导体装置11来形成连续矩形。
在其它实施例中，无核心衬底51包含共同形成环或矩形轮廓的单独部分。图4B是包含离散部分501、502、503的示例性无核心衬底51的示意性俯视图。这些部分501、502、503可在单独制造工艺中形成，然后单独地附接到载体21(图7)上。
返回参考图3A，半导体封装结构200还包含安置于包封层31的第一表面31a上的第一重新分布结构40(“重新分布结构”)，及安置于包封层31的第二表面31b上的第二重新分布结构60(“第一附加重新分布结构”(first additional redistribution structure))。第一重新分布结构40可包含若干介电层及导电层。为方便起见，仅展示介电层42及导电层45。同样，第二重新分布结构60包含介电层62及导电层65，即使其可包含若干介电层及导电层。
半导体封装结构200进一步包含附接到第一重新分布结构40的一或多个第三半导体装置70。第三半导体装置70中的每一个包含用于信号传输的导电通孔(conductivevias)75及I/O焊盘78。在本实施例中，第三半导体装置70布置成堆叠。在实施例中，第三半导体装置70包含存储器(memory)，例如，例如高带宽存储器(high bandwidth memory,HBM)的宽I/O存储器。宽I/O存储器可包含多于六百(600)个I/O数，例如2,000至5,000个I/O数。第一半导体装置11与第三半导体70之间的通信通过经由导电支柱112、第一重新分布结构40中的导电层45及I/O焊盘78从第一半导体装置11朝向第三半导体装置70路由的电路径实现，且反之亦然。
半导体封装结构200还包含电触点82，其安装在第二重新分布结构60上，以电连接到例如外部装置、例如衬底的组件或结构、中介层、PCB等。第一半导体装置11与外部装置之间的通信通过经由导电支柱112、第一重新分布结构40中的导电层45、与导电层45电连接的无核心衬底51的上部焊盘55、无核心衬底51中的布线层、第二重新分布结构60中的导电层65、电触点82，及与导电层65的电连接从第一半导体装置11朝向PCB路由的电路径实现，且反之亦然。
在半导体封装结构200中，第二半导体装置12直接结合到第一半导体装置11。类似于图1描述及说明的半导体封装结构100，通过结合第一半导体装置11及第二半导体装置12，缩短传输路径，同时最小化由于在一些现有方法中存在的中间层而引起的材料电阻率。此外，通过将包含第一重新分布结构40及第三半导体装置70的组件更靠近第一半导体装置11放置，所述组件(包含第一重新分布结构40及第三半导体装置70)将由第二半导体装置12(解耦电容器)服务(将由其解耦)，同样缩短传输路径并减小阻抗。另外，在相对较短路径中实现为第一半导体装置11及第二半导体装置12供电。因此，半导体封装结构200也受益于结合配置并且可确保较低电损耗。
此外，在半导体封装结构200中，第一半导体装置11通过第一表面11a(有源表面)面向第三半导体装置70而“面向上(face-up)”放置。借助于导电支柱112，此配置有助于第一半导体装置11与安置于第一半导体装置11上方的第三半导体装置70之间的路由(routing)。面向上第一半导体装置11通过结合接头135直接与第二半导体装置12通信，及通过第一重新分布结构40与第三半导体装置70通信。
图3B是根据本公开的又另一实施例的半导体封装结构300的截面图。
参考图3B，半导体封装结构300类似于参考图3A描述及说明的半导体封装结构200，不同之处在于，举例来说，第一半导体装置11通过第一表面11a(有源表面)面向电触点82而“面向下(face-down)”放置。当半导体封装结构300通过电触点82附接到例如PCB的外部结构时，围绕第二半导体装置12的包封层31的大量部分安置于第一半导体装置11与PCB之间，这提供所需的机械可靠性。另外，通过结合接头135的第一半导体装置11与第二半导体装置12之间的直接连接有助于减少寄生效应并因此减少电损耗。
图3C是根据本公开的又另一实施例的半导体封装结构200a的截面图。
参考图3C，半导体封装结构200a类似于参考图3A描述及说明的半导体封装结构200，不同之处在于，举例来说，无核心衬底51由预模制载体(pre-molded carrier)51a替代。预模制载体51a包含主体52a、多个导通孔53a及至少一个路由层(routing layer)54a。主体52a的材料可为模制化合物(molding compound)。导通孔53a延伸穿过主体52a。导通孔53a的底部部分可电连接到第二导电焊盘58。路由层54a可安置于主体52a上，并且可电连接导通孔53a及第一导电焊盘55。由于包封层31及预模制载体51a的主体52a的材料都可为模制化合物，因此其热膨胀系数(coefficients of thermal expansion,CTE)可相同或非常接近，因此当预模制载体51a密封在包封层31中时，减少包封层31的翘曲。另外，改进Dk/Df电特性。
图3D是根据本公开的又另一实施例的半导体封装结构300a的截面图。
参考图3D，半导体封装结构300a类似于图3B描述及说明的半导体封装结构300，不同之处在于，举例来说，无核心衬底51由预模制载体51a替代。预模制载体51a包含主体52a、多个导通孔53a及至少一个路由层54a。主体52a的材料可为模制化合物。导通孔53a延伸穿过主体52a。导通孔53a的底部部分可电连接到第二导电焊盘58。路由层54a可安置于主体52a上，并且可电连接导通孔53a及第一导电焊盘55。由于包封层31及预模制载体51a的主体52a的材料都可为模制化合物，因此其热膨胀系数(CTE)可相同或非常接近，因此当预模制载体51a密封在包封层31中时，减少包封层31的翘曲。另外，改进Dk/Df电特性。
图5A是根据本公开的实施例的半导体封装结构400的截面图。
参考图5A，半导体封装结构400包含第一半导体装置11、结合到第一半导体装置11的第二半导体装置12、无核心衬底51、第一重新分布结构40(“第二附加重新分布结构”(second additional redistribution structure))、第二重新分布结构60(“第一附加重新分布结构”(first additional redistribution structure))及第三重新分布结构90。第一半导体装置11及无核心衬底51密封在第一包封层31(“附加包封层”(additionalencapsulating layer))中。此外，第一半导体装置11、第一包封层31(“附加包封层”)、导电支柱(包含第一导电支柱812及第一导电支柱812)及第二半导体装置12密封在第二包封层32(“包封层”)中。第一半导体装置11包含在第一表面11a处的导电焊盘119。第一重新分布结构40包含导电层45，所述导电层45进一步包含安置于第一半导体装置11的导电焊盘119上的第一部分451，及安置于无核心衬底51的第二导电焊盘58上的第二部分452。第一导电焊盘55及第二导电焊盘58分别与第一半导体装置11的第一表面11a及第二表面11b基本上齐平。
在本实施例中，第一半导体装置11可包含具有相对紧密间隔的密集地间隔开的I/O。举例来说，第一半导体装置11的导电焊盘119以比第二半导体装置12的导电柱125更小的间距布置，或以比在第三重新分布结构90中的导电层95更小的间距布置。导电层45的第一部分451安置于第一半导体装置11的导电焊盘119上，以促进导电焊盘119上的I/O的扇出。此外，第一导电支柱812安置于第一部分451上以有助于扇出。另外，半导体封装结构400包含安置于第二部分452上的第二导电支柱822，以提供第一重新分布结构40与第三重新分布结构90之间的电连接。第二导电支柱822可有助于信号扇出，这对于具有相对紧密间隔的第一半导体装置11是所需的。
半导体封装结构400进一步包含附接到第三重新分布结构90的一或多个第三半导体装置70。第一半导体装置11与第三半导体装置70之间的通信通过经由第一重新分布结构40中的导电层45的第一部分451、第一部分451上的第一导电支柱812、第三重新分布结构90中的导电层95及I/O焊盘78从第一半导体装置11朝向第三半导体装置70路由的电路径实现，且反之亦然。
安置于第一半导体装置11的第二表面11b上的第二重新分布结构60包含介电层62及导电层65。例如焊料球的电触点82安置于第二重新分布结构60上，以将第一半导体装置11电连接到例如PCB的外部装置。第一半导体装置11与PCB之间的通信通过经由第一重新分布结构40中的导电层45的第一部分451、第一部分451上的第一导电支柱812、第三重新分布结构90中的导电层95、无核心衬底51上的第二导电支柱822、无核心衬底51上的导电层45的第二部分452、无核心衬底51中的布线层、无核心衬底51的第一焊盘55、第二重新分布结构60中的导电层65，及电触点82从第一半导体装置11朝向PCB路由的电路径实现，且反之亦然。
在半导体封装结构400中，第二半导体装置12直接结合到第一半导体装置11。类似于图1描述及说明的半导体封装结构100，通过结合第一半导体装置11及第二半导体装置12，缩短传输路径，同时最小化由于在一些现有方法中存在的中间层而引起的材料电阻率。此外，通过将包含第一重新分布结构40、第三半导体装置70及第三重新分布结构90的组件更靠近第一半导体装置11放置，所述组件(包含第一重新分布结构40、第三半导体装置70及第三重新分布结构90)将由第二半导体装置12(解耦电容器)服务(将由其解耦)，同样缩短传输路径并减小阻抗。另外，在相对较短路径中实现为第一半导体装置11及第二半导体装置12供电。因此，半导体封装结构400也受益于直接结合配置并且可确保较低电损耗。
此外，在半导体封装结构400中，第一半导体装置11通过第一表面11a(有源表面)面向第三半导体装置70而“面向上”放置。借助于第一导电支柱812及第二导电支柱822，此配置有助于第一半导体装置11与安置于第一半导体装置11上方的第三半导体装置70之间的路由。面向上第一半导体装置11通过结合接头135直接与第二半导体装置12通信，及通过第一重新分布结构40及第三重新分布结构90与第三半导体装置70通信。
图5B是根据本公开的实施例的半导体封装结构500的截面图。
参考图5B，半导体封装结构500类似于图5A描述及说明的半导体封装结构400，不同之处在于，举例来说，第一半导体装置11通过第一表面11a(有源表面)面向电触点82而“面向下”放置。当半导体封装结构500通过电触点82附接到例如PCB的外部结构时，围绕第二半导体装置12的第二包封层32的大量部分安置于第一半导体装置11与PCB之间，这提供所需的机械可靠性。另外，通过结合接头135的第一半导体装置11与第二半导体装置12之间的直接连接有助于减少寄生效应并因此减少电损耗。
图6是根据本公开的再另一实施例的半导体封装结构600的截面图。
参考图6，半导体封装结构600包含第一半导体装置11、第二半导体装置12、第一重新分布结构40及第二重新分布结构60。第一半导体装置11密封在第一包封层31中。另外，第二半导体装置12及第一包封层31密封在第二包封层32中。第一半导体装置11包含在第一表面11a处的导电焊盘119。安置于第一半导体装置11的第一表面11a及第一包封层31的第一表面31a上的第一重新分布结构40包含导电层45。导电层45的第一部分451安置于第一半导体装置11的第一表面11a处的导电焊盘119上。导电层45的第二部分452安置于第一包封层31的第一表面31a上并且与第一部分451分离。第二半导体装置12结合到第一半导体装置11，从而在其间形成结合接头135。
类似于参考图5A描述及说明的实施例，在本实施例中，第一半导体装置11可包含以相对紧密间隔密集地间隔开的I/O。具体来说，第一半导体装置11的导电焊盘119以比第二半导体装置12的导电焊盘更小的间距布置。导电层45的第一部分451安置于第一半导体装置11的导电焊盘119上，以促进导电焊盘119上的I/O的扇出。此外，半导体封装结构600包含第一导电支柱812，所述第一导电支柱812安置于第一部分451上及在第一重新分布结构40与第二重新分布结构60之间延伸，从而为第一半导体装置11提供电连接。半导体封装结构600还包含第二导电支柱822，所述第二导电支柱822安置于第二部分452上及在第一重新分布结构40与第二重新分布结构60之间延伸以有助于扇出。
在半导体封装结构600中，第二半导体装置12直接结合到第一半导体装置11。类似于图1描述及说明的半导体封装结构100，通过结合第一半导体装置11及第二半导体装置12，缩短传输路径，同时最小化由于在一些现有方法中存在的中间层而引起的材料电阻率。此外，在相对较短路径中实现为第一半导体装置11及第二半导体装置12供电。因此，半导体封装结构600受益于直接结合配置并且可确保较低电损耗。此外，围绕第二半导体装置12的第二包封层32的大量部分安置于第一半导体装置11与例如PCB的外部装置之间，这提供所需机械可靠性。
图7A到图7F是各自说明根据本公开的实施例的制造如图1描述及说明的半导体封装结构100的方法的一或多个阶段的截面图。
参考图7A，第一半导体装置11形成于晶片上，所述第一半导体装置11具有第一表面11a及与第一表面11a相对的第二表面11b。用于电连接到其它装置、组件或结构的导电支柱112及导电柱115在第一表面11a(“有源表面”)处形成于导电焊盘119上。因此，导电组件112形成于所述第一半导体装置11的所述有源表面11a上。如先前所描述，第一半导体装置11包含数字处理装置。导电支柱112及导电柱115的合适材料可包含铜(Cu)、金(Au)、铝(Al)、钯(Pd)或焊料，或其合金。
参考图7B，提供第二半导体装置12。在另一制造工艺中制备的第二半导体装置12包含形成于其第一表面121上的导电柱125。第二半导体装置12朝向第一半导体装置11的第一表面11a面向下放置，因此导电柱125在位置上对应于导电柱115。随后，第二半导体装置12结合到第一半导体装置11(如箭头所展示的移动)。如先前所描述，第二半导体装置12包含解耦电容器。导电柱125的合适材料可包含铜(Cu)、金(Au)、铝(Al)、钯(Pd)或焊料，或其合金。
在一些实施例中，导电柱115及导电柱125直接彼此接触。举例来说，如图8A到8H详细地论述，导电柱115及导电柱125在铜对铜(copper-to-copper,Cu to Cu)直接结合工艺中彼此结合。或者，如图10A到10E详细地论述，导电柱115及导电柱125可在焊料-接头结合工艺中彼此结合。
随后在晶片切割工艺中，将与第二半导体装置12结合的第一半导体装置11与其它半导体装置分离。现在参考图7C，提供具有离型膜210的载体21。第一半导体装置11(目前是半导体裸片的形式，或是在芯片切割之后变成芯片形式)在其第二表面11b处附接到离型膜210上。载体21用于支持随后形成或安置于其上的半导体组件、装置或结构。在实施例中，载体21包含有机材料，例如，双马来酰亚胺三嗪(Bismaleimide Triazine,BT)、聚酰亚胺(polyimide,PI)、味之素堆积膜(Ajinomoto build-up film,ABF)，或其它合适的材料。或者，载体21包含无机材料，例如，硅、玻璃，或其它合适的材料。离型膜210用于促使载体21从由载体21临时地固持的半导体结构离型。在实施例中，离型膜210包含非金属材料，例如，PI、ABF、环氧树脂、模制化合物、阻焊剂油墨，或其它合适的材料。另外，离型膜210是任选的且因此可忽略。
参考图7D，包封层310形成于载体21上，从而覆盖第一半导体装置11及第二半导体装置12。包封层310可包含模制化合物。
参考图7E，随后通过例如研磨工艺，例如机械抛光工艺减小包封层310的高度，从而产生减小的包封层(reduced encapsulating layer)31。减小的包封层31暴露导电支柱112。随后移除载体21以及离型膜210。在一些实施例中，载体21包含玻璃载体，其可在激光剥离工艺中去除。
接下来，参考图7F，重新分布结构40形成于减小的包封层31上。重新分布结构40用于提供互连并且可包含介电层42及导电层45。所述重新分布结构40通过所述导电组件(导电支柱112)与所述第一半导体装置11电连接。在实施例中，介电层42包含有机材料，例如，模制化合物、聚酰胺(polyamide,PA)、聚酰亚胺(PI)、聚苯并恶唑(polybenzoxazole,PBO)，或环氧基材料。在另一实施例中，介电层42包含无机材料，例如，氧化硅(SiOx)、氮化硅(SiNx)或氧化钽(TaOx)。另外，导电层45包含钛(Ti)、钛钨合金(TiW)、镍(Ni)、铜(Cu)、钛铜合金(TiCu)、银(Ag)、金(Au)，或其它合适的导电材料。
随后返回参考图1，电触点81安装在减小的包封层31上方的重新分布结构40的表面42a上。电触点81提供第一半导体装置11与外部结构(未展示)之间的电连接。在实施例中，电触点81可包含可布置在球栅阵列(BGA)中的焊料球。在另一实施例中，电触点81可包含布置在栅格阵列(LGA)中的金属焊盘。在又另一实施例中，电触点81可包含布置在针栅阵列(PGA)中的引脚。此外，电触点81可包含可控塌陷芯片连接(C4)凸块，所述C4凸块包含基于铅或无铅的凸块或球。
图8A到图8H是各自说明如图1描述及说明的在半导体封装结构100中的第一半导体装置11与第二半导体装置12之间形成结合接头135的示例性方法的一或多个阶段的截面图。如下文将论述，示例性方法包含在铜对铜(Cu-to-Cu)直接结合工艺中在第一半导体装置11的输入/输出(I/O)焊盘上形成导电柱，及在混合结合工艺中在第二半导体装置12的I/O焊盘上单独地形成导电柱。
参考图8A，对于第一半导体装置11，最初介电层161通过例如化学气相沉积(chemical vapor deposition,CVD)工艺形成于第一半导体装置11的衬底160的第一表面11a上。第一半导体装置11包含在衬底160的表面11a处的I/O焊盘119。介电层161可包含氧化物，例如氧化硅(SiOx)。接下来，图案化光致抗蚀剂层162形成于介电层161上，从而通过开口168暴露介电层161的部分。这些暴露部分在位置上对应于第一半导体装置11的I/O焊盘119。
参考图8B，介电层161的暴露部分通过例如蚀刻工艺去除，从而产生图案化介电层171。图案化介电层171通过开口168暴露I/O焊盘119。然后去除图案化光致抗蚀剂层162。
参考图8C，第一导电层163例如在溅镀工艺中形成于图案化介电层171及所暴露I/O焊盘119上。第一导电层163基本上与图案化介电层171的拓扑结构(topology)共形，并且用作在其上形成的后续导电层的种子层。在实施例中，第一导电层163包含钛(Ti)层及堆叠在钛层上的铜层。
接下来，参考图8D，通过使用例如电镀工艺在第一导电层163上依次形成第二导电层164、第三导电层165及第四导电层166。具体来说，第二导电层164共形地形成于第一导电层163上，第三层165共形地形成于第二导电层164上，并且第四导电层166填满开口168，同时形成于第三导电层165上。在实施例中，第二导电层164包含铜，第三导电层165包含镍(Ni)，及第四导电层166包含焊料，例如，锡及银的合金(SnAg)。因此，第二导电层164，即铜层确保所需导电性。另外，第四导电层166，即SnAg层提供有助于形成结合的所需可熔性。此外，第三导电层165，即镍层防止铜层164与SnAg层166之间的电化腐蚀(electrochemicalcorrosion)，以确保所需导电性及稳固结合。
现在参考图8E，第一导电层163、第二导电层164、第三导电层165及第四导电层166通过使用例如化学机械抛光(CMP)工艺等研磨工艺图案化，从而产生一起构成图1中所说明的导电柱115的图案化第一导电层173、第二导电层174、第三导电层175及第四导电层176。图案化介电层171在研磨工艺之后暴露及平面化，这有助于导电柱115与对应导电柱125之间的结合。
关于第二半导体装置12，参考图8F，一起构成如图1中所说明的导电柱125的图案化第一导电层273、第二导电层274、第三导电层275及第四导电层276以如参考图8A到8E所描述及说明的类似方式在第二半导体装置12的衬底260的第一表面121处形成于I/O焊盘129上。因此，暴露及平面化衬底260上的图案化介电层271。
参考图8G，第二半导体装置12结合到第一半导体装置11。具体来说，第二半导体装置12的导电柱125在“混合结合(hybrid bonding)”工艺中结合到第一半导体装置11的其对应导电柱115。“混合结合”将介电接合(dielectric bond)与嵌入金属组合以形成互连。最初，如图8H中所说明，当彼此接触时，介电层271及171之间的介电接合在室温下通过范德华力(Van der Waals force)形成，从而产生结合的介电层371。接下来，进行热工艺以迫使图案化第二导电层274及174产生结合接头135。如图8A到8H描述及说明的示例性结合工艺可在晶片级阶段进行。随后，在晶片切割工艺中将第一半导体装置11单体化，其中第二半导体装置12结合在其上。
图9A是说明根据本公开的另一实施例的如图1描述及说明的在半导体封装结构100中的第一半导体装置11与第二半导体装置12之间形成结合接头的方法的截面图。所述方法类似于参考图8A到8H描述及说明的方法，不同之处在于例如，第二半导体装置12的导电柱525。具体来说，第一半导体装置11的导电柱515与图8G的导电柱115相同或相似。第二半导体装置12的导电柱525可仅包含图案化第一导电层273及图案化第二导电层574。为了形成结合接头，类似地，介电层271及171之间的介电结合在室温下形成，及随后金属结合通过使用热工艺由图案化第二导电层174及574形成。
图9B是说明根据本公开的又另一实施例的如图1描述及说明的在半导体封装结构100中的第一半导体装置11与第二半导体装置12之间形成结合接头的方法的截面图。所述方法类似于参考图8A到8H描述及说明的方法，不同之处在于例如，第一半导体装置11的导电柱515。具体来说，第二半导体装置12的导电柱525与图8G的导电柱125相同或相似。第一半导体装置11的导电柱515可仅包含图案化第一导电层173及图案化第二导电层674。为了形成结合接头，类似地，介电层271及171之间的介电结合在室温下形成，及随后金属结合通过使用热工艺由图案化第二导电层674及274形成。
图9C是说明根据本公开的再又另一实施例的如图1描述及说明的在半导体封装结构100中的第一半导体装置11与第二半导体装置12之间形成结合接头的方法的截面图。参考图9C，第一半导体装置11的导电柱515可仅包含图案化第一导电层173及图案化第二导电层674。另外，第二半导体装置12的导电柱525可仅包含图案化第一导电层273及图案化第二导电层574。为了形成结合接头，类似地，介电层271及171之间的介电结合在室温下形成，及随后金属结合通过使用热工艺由图案化第二导电层574及674形成。
图10A到图10E是各自说明如图1描述及说明的在半导体封装结构100中的第一半导体装置11与第二半导体装置12之间形成结合接头135的另一方法的一或多个阶段的截面图。
参考图10A，通过使用例如光刻工艺(photolithographic process)，图案化介电层181形成于第一半导体装置11的第一表面11a上，从而从开口188暴露I/O焊盘119。图案化介电层181可包含聚酰亚胺。
参考图10B，通过使用电镀工艺，随后进行蚀刻工艺，图案化导电层115形成于图案化介电层181及导电焊盘119上。图案化导电层115包含导电柱以与第二半导体装置12的导电柱结合。随后，参考图10C，导电支柱112以类似于形成导电柱115的方式形成于I/O焊盘119上。
参考图10D，提供第二半导体装置12。第二半导体装置12包含形成于图案化介电层281及I/O焊盘129上的图案化导电层125。图案化导电层125包含导电柱以与第一半导体装置11的导电柱115结合。接下来，借助于例如焊料681，第二半导体装置12的导电柱125结合到第一半导体装置11的导电柱115，从而产生如图10E所说明的结合接头135。
图11A到图11E是各自说明根据本公开的又另一实施例的如图3A描述及说明的制造半导体封装结构200的方法的一或多个阶段的截面图。
参考图11A，类似于参考7C描述及说明的操作，提供具有离型膜210的载体21。随后，与第二半导体装置12结合的第一半导体装置11在其第二表面11b处附接到离型膜210上。此外，衬底50附接到离型膜210。衬底50可包含无核心衬底51。
参考图11B，包封层310形成于载体21上，从而覆盖第一半导体装置11、第二半导体装置12及无核心衬底51。之后，参考图11C，通过例如机械抛光工艺等研磨工艺减小包封层310的高度，从而产生减小的包封层31。减小的包封层31从其第一表面31a暴露第一半导体装置11的导电支柱112及无核心衬底51的上部焊盘55。
参考图11D，随后去除载体21以及离型膜210，从而从减小的包封层31的第二表面31b暴露第一半导体装置11的第二表面11b及无核心衬底51的下部焊盘58。第二表面31b与减小的包封层31的第一表面31a相对。随后，第一重新分布结构40形成于减小的包封层31的第一表面31a上。第一重新分布结构40用于提供电连接并且可包含若干介电层及导电层。为方便起见，仅展示介电层42及导电层45。
参考图11E，第二重新分布结构60形成于减小的包封层31的第二表面31b及第一半导体装置11的第二表面11b上。类似地，第二重新分布结构60用于提供电连接并且可包含若干介电层及导电层。为方便起见，仅展示介电层62及导电层65。如图7F所描述，用于第二介电层62及第二导电层65的合适材料分别与介电层42及导电层45的材料相似或相同，且因此不再进一步讨论。
接下来，返回参考图3A，第三半导体装置70的堆叠附接在第一重新分布结构40上。第三半导体装置70包含高带宽存储器(HBM)。另外，电触点82安装在第二重新分布结构60上。如参考图1所描述，用于电触点82的合适材料及部署类似于电触点81，且因此不再进一步讨论。
图3B的半导体封装结构300可通过与参考图11A到11E描述及说明的方法类似的方法制造，不同之处在于例如，在图11E的操作中，第三半导体装置70的堆叠附接在第二重新分布结构60上，及电触点82安装在第一重新分布结构40上。
图12A到图12C是各自说明根据本公开的另一实施例的如图3A描述及说明的制造半导体封装结构200的方法的一或多个阶段的截面图。
参考图12A，第一半导体装置11类似于参考图3A描述及说明的第一半导体装置11，不同之处在于例如，导电支柱512高于导电支柱112。因此，通过将导电支柱512设置为研磨止动件，在如图11C中进行的用于减小包封层310的研磨工艺之后，导电支柱512从减小的包封层31暴露，同时无核心衬底51仍由减小的包封层31覆盖。
接下来，参考图12B，减小的包封层31通过例如激光钻孔工艺图案化，从而通过开口57暴露无核心衬底51的上部焊盘55。
随后，参考图12C，第一重新分布结构40形成于图案化的减小的包封层31的第一表面31a上。在形成第一重新分布结构40期间，导电层45填满在开口57中及电连接上部焊盘55及导电支柱512。其余操作与参考图11E及3A描述及参考的操作相似或相同，且因此不再进一步讨论。
图13A到图13D是各自说明根据本公开的又另一实施例的如图3A描述及说明的制造半导体封装结构200的方法的一或多个阶段的截面图。
参考图13A，结构类似于参考图11A描述及说明的结构，不同之处在于例如，附加支柱522形成于无核心衬底51的上部焊盘55上。无核心衬底51的附加支柱522与第一半导体装置11的导电支柱112基本上齐平。
参考图13B，包封层310形成于载体21上，从而覆盖第一半导体装置11的导电支柱112、第二半导体装置12，及无核心衬底51的附加支柱522。之后，参考图13C，通过例如机械抛光工艺等研磨工艺减小包封层310的高度，从而产生减小的包封层31。减小的包封层31从其第一表面31a暴露第一半导体装置11的导电支柱112及无核心衬底51的附加支柱522。
随后，参考图13D，第一重新分布结构40形成于减小的包封层31的第一表面31a上。在形成第一重新分布结构40期间，导电层45电连接无核心衬底51的附加支柱522及第一半导体装置11的导电支柱112。其余操作与参考图11E及3A描述及参考的操作相似或相同，且因此不再进一步讨论。
图14A到图14J是各自说明根据本公开的实施例的制造如图5A描述及说明的半导体封装结构400的方法的一或多个阶段的截面图。
参考图14A，提供具有第一离型膜210的第一载体21。随后，第一半导体装置11在其第一表面11a处附接到第一离型膜210上。第一半导体装置11包含在第一表面11a处的导电焊盘119。另外，无核心衬底51还附接到第一离型膜210。无核心衬底51包含第一焊盘55及第二焊盘58。在附接第一半导体装置11时，第一半导体装置11的导电焊盘119及无核心衬底51的第二焊盘58附接到第一离型膜210。
参考图14B，第一包封层310形成于离型膜210上，从而覆盖第一半导体装置11及无核心衬底51。随后去除第一载体21以及第一离型膜210，从而暴露第一半导体装置11的第一表面11a及导电焊盘119，及无核心衬底51的第二焊盘58。
接下来参考图14C，第一重新分布结构40形成于第一半导体装置11的第一表面11a以及第一包封层310的第一表面31a上。第一重新分布结构40包含导电层45，所述导电层45进一步包含安置于第一半导体装置11的导电焊盘119上的第一部分451，及安置于无核心衬底51的第二焊盘58上的第二部分452。之后，第一导电支柱812形成于导电层45的第一部分451上，及第二导电支柱822形成于导电层45的第二部分452上。用于第一导电支柱812及第二导电支柱822的合适材料与用于如参考图3A描述的导电支柱112的材料相似或相同。随后，参考图14D，第二半导体装置12结合到第一半导体装置11，从而在其间形成结合接头135。
参考图14E，通过研磨工艺减小第一包封层310的厚度，从而产生减小的第一包封层31。减小的第一包封层31暴露第一半导体装置11的第二表面11b及无核心衬底51的第一焊盘55。
随后，参考图14F，提供具有第二离型膜220的第二载体22。如图14E中所说明的封装结构在第二表面11b处附接到第二离型膜220上。此后，第二包封层320形成于第二离型膜220上，从而覆盖封装结构及第二半导体装置12，所述封装结构包含密封第一半导体装置11及无核心衬底51的减小的第一包封层31。随后去除第二载体22以及第二离型膜220，从而暴露第二表面11b及无核心衬底51的第一焊盘55。
现在参考图14G，第二重新分布结构60形成于第一半导体装置11的第二表面11b及无核心衬底51的第一焊盘55上。第二重新分布结构60包含第二介电层62及第二导电层65。第二导电层65的部分形成与无核心衬底51的第一焊盘55的电连接。
接下来参考图14H，通过研磨工艺减小第二包封层320的高度，从而产生减小的第二包封层32。减小的第二包封层32从其第一表面32a暴露第一导电支柱812及第二导电支柱822。
参考图14I，第三重新分布结构90随后形成于减小的第二包封层32的第一表面32a上。第三重新分布结构90包含第三介电层92及第三导电层95。导电层95的部分与第一导电支柱812及第二导电支柱822形成电连接，进而分别与导电层45的第一部分451及第二部分452电连接。如参考图7F所描述，用于第三介电层92及第三导电层95的合适材料分别与用于介电层42及导电层45的材料相似或相同。
随后，参考图14J，电触点82安装在第二重新分布结构60上，以将第一半导体装置11电连接到例如PCB。
现在返回参考图5A，第三半导体装置70的堆叠附接在第三重新分布结构90上。第三半导体装置70包含高带宽存储器(HBM)。
图5B的半导体封装结构500可通过与参考图14A到14I描述及说明的方式类似的方式制造，不同之处在于例如，在图14I的操作之后，第三半导体装置70的堆叠附接在第二重新分布结构60上，及电触点82安装在第一重新分布结构40上。
图15A到图15H是各自说明根据本公开的实施例的制造如图6描述及说明的半导体封装结构600的方法的一或多个阶段的截面图。
参考图15A，提供具有第一离型膜210的第一载体21。随后，第一半导体装置11在其第一表面11a处附接到第一离型膜210上。第一半导体装置11包含在第一表面11a处的导电焊盘119。
参考图15B，第一包封层310形成于离型膜210上，从而覆盖第一半导体装置11。随后去除第一载体21以及第一离型膜210，从而暴露第一半导体装置11的第一表面11a及导电焊盘119。
接下来参考图15C，第一重新分布结构40形成于第一半导体装置11的第一表面11a上。第一重新分布结构40包含导电层45，所述导电层45进一步包含第一部分451及与第一部分451分离的第二部分452。此后，第一导电支柱812及第二导电支柱822形成于导电层45上，以提供第一半导体装置11的导电焊盘119的电连接。随后，参考图15D，第二半导体装置12结合到第一半导体装置11。
参考图15E，通过研磨工艺减小第一包封层310的厚度，从而产生减小的第一包封层31。减小的第一包封层31暴露第一半导体装置11的第二表面11b及减小的第一包封层31的第一表面31a。
接下来参考图15F，提供具有第二离型膜220的第二载体22。如图15E中所说明的封装结构在第二表面11b处附接到第二离型膜220上。任选地，例如电感器的无源装置88也可附接到第二离型膜220上。此后，第二包封层320形成于第二离型膜220上，从而覆盖无源装置88(如果存在的话)、封装结构及第二半导体装置12，所述封装结构包含密封第一半导体装置11的减小的第一包封层31。在形成第二包封层320之后，去除第二载体22以及第二离型膜220，从而暴露第二表面11b及减小的第一包封层31的第一表面31a。
参考图15G，通过研磨工艺减小第二包封层320的高度，从而产生减小的第二包封层32。减小的第二包封层32从其第一表面32a暴露第一导电支柱812及第二导电支柱822。
随后，参考图15H，第二重新分布结构60形成于减小的第二包封层32的第一表面32a上。第二重新分布结构60包含第二介电层62及第二导电层65。第二导电层65的部分形成与第一导电支柱812及第二导电支柱822的电连接。
现在返回参考图6，电触点82安装在第二重新分布结构60上。第二重新分布结构60及电触点82用于提供第一半导体装置11与例如PCB的电连接。
如本文所使用，术语“大约”、“基本上”、“大体”及“约”用于描述及解释小的变化。当与事件或情况结合使用时，所述术语可指事件或情况精确发生的例子以及事件或情况极近似地发生的例子。另外，有时在本文中以范围格式呈现量、比率及其它数值。应理解，此范围格式是为了便利及简洁而使用，且应灵活地理解，不仅包含明确地指定为范围极限的数值，而且包含涵盖于那个范围内的所有个别数值或子范围，如同明确地指定每一数值及子范围一般。
尽管已参考本公开的特定实施例描述并说明本公开，但这些描述及说明并不是限制性的。本领域技术人员应理解，可在不脱离如由所附权利要求书界定的本发明的真实精神及范围的情况下，作出各种改变且取代等效物。图解可能未必按比例绘制。归因于制造过程及公差，本公开中的工艺再现与实际设备之间可能存在区别。可能存在并未特定说明的本公开的其它实施例。应将本说明书及图式视为说明性的而非限制性的。可进行修改，以使特定情形、材料、物质组成、方法或工艺适宜于本发明的目标、精神及范围。所有此类修改既定在所附权利要求书的范围内。虽然本文中公开的方法已参考按特定次序执行的特定操作加以描述，但应理解，可在不脱离本公开的教示的情况下组合、细分或重新排序这些操作以形成等效方法。相应地，除非本文中特别指示，否则操作的次序及分组并非本公开的限制。

Claims (20)

1.一种半导体封装结构，其包括：
第一半导体装置，其具有有源表面；
重新分布结构，其与所述第一半导体装置电连接；
第二半导体装置，其结合到所述第一半导体装置的所述有源表面及安置于所述第一半导体装置与所述重新分布结构之间；及
多个导电组件，其位于所述第一半导体装置的所述有源表面上及所述第二半导体装置之外，其中所述第一半导体装置通过所述导电组件电连接所述重新分布结构。
2.根据权利要求1所述的半导体封装结构，其进一步包括包封层，其密封所述第一半导体装置，其中所述重新分布结构在所述包封层上。
3.根据权利要求2所述的半导体封装结构，其中所述第一半导体装置包含导电柱，所述第二半导体装置包含导电柱，所述第二半导体装置的所述导电柱直接接触所述第一半导体装置的所述导电柱。
4.根据权利要求2所述的半导体封装结构，其进一步包括在所述重新分布结构的导电层上的电触点。
5.根据权利要求2所述的半导体封装结构，其进一步包括围绕所述第一半导体装置及所述第二半导体装置的衬底。
6.根据权利要求5所述的半导体封装结构，其中所述衬底包含无核心衬底，所述无核心衬底包含第一导电焊盘，所述第一导电焊盘邻近所述包封层的第一表面且与所述重新分布结构电连接。
7.根据权利要求6所述的半导体封装结构，其进一步包括在所述包封层的第二表面上的第一附加重新分布结构，所述第二表面与所述包封层的所述第一表面相对。
8.根据权利要求7所述的半导体封装结构，其中所述无核心衬底包含第二导电焊盘，所述第二导电焊盘邻近所述包封层的所述第二表面且与所述第一附加重新分布结构电连接。
9.根据权利要求7所述的半导体封装结构，其中所述第一半导体装置包含数字处理装置，及所述第二半导体装置包含解耦电容器，所述半导体封装结构进一步包括安置于所述重新分布结构上的第三半导体装置，其中所述第三半导体装置包含存储器装置。
10.根据权利要求7所述的半导体封装结构，其中所述第一半导体装置包含数字处理装置，及所述第二半导体装置包含解耦电容器，所述半导体封装结构进一步包括安置于所述第一附加重新分布结构上的第三半导体装置，其中所述第三半导体装置包含存储器装置。
11.根据权利要求7所述的半导体封装结构，其进一步包括附加包封层，所述附加包封层密封所述第一半导体装置及与所述第二半导体装置一起密封在所述包封层中，所述附加包封层具有第一表面及与其所述第一表面相对的第二表面。
12.根据权利要求11所述的半导体封装结构，其进一步包括第二附加重新分布结构，所述第二附加重新分布结构安置于所述附加包封层的所述第一表面上并且包含导电层，所述导电层进一步包含在所述第一半导体装置的所述有源表面处的第一部分及在所述衬底上的第二部分。
13.根据权利要求12所述的半导体封装结构，其进一步包括在所述导电层的所述第一部分上的第一导电支柱，用于在所述重新分布结构与所述第二附加重新分布结构之间进行电连接。
14.根据权利要求12所述的半导体封装结构，其进一步包括在所述导电层的所述第二部分上的第二导电支柱，用于在所述衬底与所述第二附加重新分布结构之间进行电连接。
15.根据权利要求11所述的半导体封装结构，其中所述第一半导体装置具有比所述第二半导体装置更小的间距。
16.一种制造半导体封装结构的方法，所述方法包括：
提供具有有源表面的第一半导体装置；
形成多个导电组件于所述第一半导体装置的所述有源表面上；
将第二半导体装置结合到所述第一半导体装置的所述有源表面，其中所述导电组件位于所述第二半导体装置之外；及
形成重新分布结构，所述重新分布结构通过所述导电组件与所述第一半导体装置电连接，其中所述第二半导体装置安置于所述第一半导体装置与所述重新分布结构之间。
17.根据权利要求16所述的方法，其进一步包括：
将所述第一半导体装置密封在包封层中，其中所述重新分布结构形成在所述包封层的第一表面上。
18.根据权利要求17所述的方法，其进一步包括：
将所述第一半导体装置密封在附加包封层中，其中所述第一半导体装置、所述附加包封层、所述第二半导体装置及所述导电组件密封在所述包封层中。
19.根据权利要求16所述的方法，其进一步包括：
提供围绕所述第一半导体装置及所述第二半导体装置的中介层。
20.根据权利要求16所述的方法，其中所述第一半导体装置包含数字处理装置，及所述第二半导体装置包含解耦电容器，所述方法进一步包括提供第三半导体装置在所述重新分布结构上，其中所述第三半导体装置包含存储器装置。
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