CN112309486A

CN112309486A - Chip testing device

Info

Publication number: CN112309486A
Application number: CN201910682961.8A
Authority: CN
Inventors: 蔡振龙; 基因·罗森塔尔
Original assignee: First Inspection Co Ltd
Current assignee: First Inspection Co Ltd
Priority date: 2019-07-26
Filing date: 2019-07-26
Publication date: 2021-02-02
Anticipated expiration: 2039-07-26
Also published as: CN112309486B

Abstract

The invention discloses a chip testing device which can be carried and transferred among a plurality of workstations. The chip testing device comprises a circuit board, a control unit and a plurality of connecting terminals. The circuit board is provided with a plurality of electric connection seats, and each electric connection seat is used for bearing a chip. The control unit comprises a plurality of test modules which are arranged on one side of the circuit board. The plurality of connection terminals are disposed on the circuit board. When the connecting terminal is connected with the external power supply device, each test module is connected with the plurality of electric connection seats, and each test module can test a chip borne on the electric connection seat connected with the test module. After the chips are arranged on the electric connection seats, the chips can be arranged in a high-temperature environment or a low-temperature environment together with the chip testing device for testing, and the chips do not need to be repeatedly disassembled and assembled.

Description

Chip testing device

Technical Field

The present invention relates to a chip testing apparatus, and more particularly, to a chip testing apparatus suitable for testing an internal memory.

Background

Generally, before the memory is shipped, the memory must pass a high temperature test, a Burn-In (Burn-In) test, or a high temperature test, a Burn-In test, and a low temperature test. In the existing memory test equipment, when a high-temperature test, a pre-burning test or a low-temperature test is carried out on a memory, the memory must be repeatedly plugged into and pulled out of different electric connection seats, so that the memory pins are easily damaged, and a large amount of time is wasted due to repeated plugging and pulling, thereby causing the problem of low test efficiency.

Disclosure of Invention

Embodiments of the present invention provide a chip testing apparatus, which is used to improve the problems that when an existing memory device is tested in different temperature environments, the chip must be repeatedly disassembled and assembled, which causes low testing efficiency and easily damages pins of the memory.

One embodiment of the invention discloses a chip testing device which is used for bearing a plurality of chips and can be carried by a transfer device to be transferred among a plurality of workstations. The two opposite sides of the circuit board are respectively defined as a first side surface and a second side surface; the electric connection seats are fixedly arranged on the first side surface of the circuit board, and each electric connection seat is used for bearing a chip; the plurality of electric connection seat areas are divided into a plurality of electric connection seat groups, and each electric connection seat group comprises at least one electric connection seat; the control unit is arranged on the second side surface of the circuit board and comprises a plurality of test modules, the test modules are connected with the electric connection seat groups, and each test module is connected with all the electric connection seats in the corresponding electric connection seat group; at least one power supply component connected with the circuit board; the chip testing device is connected with an external power supply device through a power supply component to obtain the power required by the operation of each testing module; when the chip testing device obtains power from the external power supply equipment through the power supply component, each testing module can perform a preset testing program on the chips on the plurality of electric connection seats connected with the testing module.

Preferably, the chip is a memory, and the predetermined test program includes: at least one of a read test, a write test, and an electrical test.

Preferably, each test module comprises: a Pattern Generator (PG), a Device Power supply module (DPS), and a Driver circuit (Driver).

Preferably, the power supply member comprises a plurality of connection terminals, the connection terminals are arranged on the circuit board, and each connection terminal is used for being connected with a plurality of accommodating chamber terminals of at least one workstation; when the plurality of connecting terminals and the plurality of accommodating chamber terminals are connected with each other, the external power supply device can provide power to the chip testing device.

Preferably, the power supply member is a receiving antenna for coupling with a transmitting antenna of the external power supply device, and the chip testing apparatus can wirelessly receive the power transmitted by the external power supply device through the receiving antenna.

Preferably, the chip testing device further includes a plurality of first data transmission terminals disposed on the circuit board, and the plurality of first data transmission terminals are configured to transmit data with the plurality of second data transmission terminals of the at least one workstation.

Preferably, the chip testing device further includes a plurality of first data transmission antennas, and the plurality of first data transmission antennas are configured to wirelessly transmit data with a plurality of second data transmission antennas of at least one workstation.

Preferably, each chip is a memory, and after each test module completes a predetermined test program for the chips on the plurality of electrical connection sockets connected to the test module, the test module writes test result data and test parameter data of each chip into the chip, so that the test result data and the test parameter data are stored in each chip.

Preferably, each test module comprises at least one storage unit and a processing unit; after each test module completes a preset test program for the chips on the plurality of electric connection seats connected with the test module, the processing unit stores the test result data and the test parameter data of each chip in the storage unit.

Preferably, after each test module completes a predetermined test program for the chips on the plurality of electrical connection sockets connected thereto, each processing unit can selectively write the test result data and the test parameter data thereof into the chip according to the test result data of each chip.

Preferably, the chip testing device further comprises a processing unit and a wireless transmission unit, wherein the processing unit is connected with the plurality of testing modules, and the wireless transmission unit is connected with the processing unit; when each test module completes a preset test program to the chips on the plurality of electric connection seats connected with the test module, each test module correspondingly generates test result data and test parameter data; the processing unit can receive the test result data and the test parameter data transmitted by each test module, and the processing unit can control the wireless transmission unit to transmit the test result data and the test parameter data transmitted by the plurality of test modules to an external electronic device in a wireless mode.

Preferably, each electrical connection socket comprises: the base body is provided with a top wall and an annular side wall, the top wall is provided with an opening, one end of the annular side wall is connected with the periphery of the top wall, the other end of the annular side wall is arranged on the circuit board, and the top wall, the annular side wall and the circuit board form a containing groove together; two opposite side surfaces of the top wall are defined as an outer side surface and an inner side surface, and the inner side surface is positioned in the accommodating groove; the supporting structure is arranged on the circuit board and is positioned in the accommodating groove; the lifting structure is arranged in the accommodating groove and is provided with a base part and a bearing part, the base part is positioned in the accommodating groove, the base part extends towards one side to form the bearing part, and at least one part of the bearing part is positioned in the opening; the bearing part extends towards one side far away from the base part to form a plurality of limiting parts, at least one part of the limiting parts penetrates through the opening, and a chip containing groove is formed by the limiting parts and the bearing part together and is used for containing a chip; the lifting structure is also provided with a plurality of connecting holes which penetrate through the base part and the bearing part; the elastic components are arranged in the accommodating groove, one end of each elastic component is fixed to the lifting structure, the other end of each elastic component is fixed to the supporting structure, the elastic restoring force generated by the compression of the elastic components enables the base part to abut against the inner side surface of the top wall, and a gap is formed between the lifting structure and the supporting structure; one end of each probe assembly is fixedly arranged on the supporting structure and is used for being connected with the circuit board, and the other end of each probe assembly penetrates through the connecting holes; when the chip accommodating groove is provided with the chip and the limiting part is not pressed by a pressing device, the probe assemblies positioned in the connecting holes are not connected with the contact parts of the chip; when the chip accommodating groove is provided with the chip, and the limiting part is pressed by the pressing device and is retracted towards the base body, the probe assemblies abut against the contact parts, and the probe assemblies and the chip are connected with each other.

Preferably, when the chip accommodating groove is provided with a chip and the limiting part is pressed by the pressing device to retract towards the base body, the plurality of probe assemblies penetrate through the plurality of connecting holes.

Preferably, the lifting structure is fully retractable within the base body when compressed.

Preferably, any one of the electrical connectors in each electrical connector group is not connected to any electrical connector in another electrical connector group.

To sum up, the chip testing device disclosed in the embodiments of the present invention is applied to the memory testing operation, and the chip testing device and the plurality of chips carried by the chip testing device can be disposed in a high temperature environment or a low temperature environment together through the related robot arm, and then the chip testing device can be powered on to test the plurality of chips, that is, no matter the plurality of chips are tested in the high temperature environment or in the low temperature environment, the chips do not need to be detached from the electrical connection socket, so that the overall testing time can be greatly reduced, and the problem that the memory is easily damaged due to continuous detachment and installation of the conventional memory testing device can be avoided.

Drawings

FIG. 1 is a schematic diagram of a chip testing system according to the disclosure.

FIG. 2 is a block diagram of a chip testing system according to the present invention.

FIG. 3 is a schematic diagram of a chip testing apparatus of the chip testing system disclosed in the present invention.

FIG. 4 is a block diagram of a chip testing apparatus of the chip testing system according to the present invention.

FIG. 5 is a schematic diagram of an electrical connector of a chip testing device of the chip testing system disclosed in the present invention.

FIG. 6 is a cross-sectional exploded view of an electrical connector of a chip testing device of the chip testing system according to the present invention.

Fig. 7 is a schematic cross-sectional view of an electrical connector of a chip testing device of the chip testing system disclosed in the present invention without a chip.

FIG. 8 is a schematic cross-sectional view of an electrical socket of a chip testing device of the chip testing system according to the present invention with a chip.

FIG. 9 is a diagram of an environment control apparatus of the chip testing system according to the disclosure.

FIG. 10 is a block diagram of an environmental control apparatus and a central control device of a chip testing system according to the present invention.

Fig. 11 is an assembly diagram of the temperature adjustment device and the cover of the chip testing system disclosed in the present invention.

Fig. 12 and 13 are exploded views of a temperature adjustment device and a cover of a chip testing system according to the disclosure.

Fig. 14 is a schematic cross-sectional view illustrating a temperature adjustment device and a cover disposed on a chip testing device of a chip testing system according to the present invention.

Fig. 15 is a partially enlarged schematic view of fig. 14.

Fig. 16 is a flowchart illustrating a first embodiment of a chip testing system according to the present invention, which tests a plurality of chips by using a chip testing method.

Fig. 17 is a flowchart illustrating a second embodiment of a chip testing system according to the present invention, which tests a plurality of chips by using a chip testing method.

Fig. 18 is a flowchart illustrating a third embodiment of testing a plurality of chips by using a chip testing method in the chip testing system disclosed in the present invention.

Fig. 19 is a flowchart illustrating a fourth embodiment of testing a plurality of chips by using a chip testing method in the chip testing system according to the disclosure.

Fig. 20 is a flowchart illustrating a fifth embodiment of testing a plurality of chips by using a chip testing method in the chip testing system according to the disclosure.

Fig. 21 is a flowchart illustrating a sixth embodiment of testing a plurality of chips by using a chip testing method in the chip testing system according to the present disclosure.

Fig. 22 is a flowchart illustrating a seventh embodiment of testing a plurality of chips by using a chip testing method in the chip testing system according to the disclosure.

Fig. 23 is a flowchart illustrating an eighth embodiment of testing a plurality of chips by using a chip testing method in the chip testing system according to the disclosure.

Fig. 24 is a flowchart illustrating a ninth embodiment of testing a plurality of chips by using a chip testing method in the chip testing system according to the disclosure.

Fig. 25 is a flowchart illustrating a tenth embodiment of testing a plurality of chips by using a chip testing method in the chip testing system according to the disclosure.

FIG. 26 is a block diagram illustrating a memory tested by the chip test system according to the present disclosure.

Fig. 27 is a flowchart illustrating an eleventh embodiment of a chip testing system for testing a plurality of chips by using a chip testing method according to the present disclosure.

Fig. 28 is a flowchart illustrating a twelfth embodiment of testing a plurality of chips by using a chip testing method in the chip testing system according to the disclosure.

Fig. 29 is a flowchart illustrating a thirteenth embodiment of testing a plurality of chips by using a chip testing method in the chip testing system according to the disclosure.

FIG. 30 is a block diagram of a central control device according to the present disclosure.

Detailed Description

Referring to fig. 1, fig. 2 and fig. 3 together, fig. 1 is a schematic diagram of a chip testing system disclosed in the present invention, fig. 2 is a block schematic diagram of the chip testing system disclosed in the present invention, and fig. 3 is a schematic diagram of a chip testing apparatus disclosed in the present invention. The chip test system E disclosed by the invention is used for testing a plurality of chips C. The chip test system E includes: a central control device E1, a chip installation device E2, at least one chip testing device 1, a plurality of environment control devices E3, a transfer device E4 and a sorting device E5.

The central control device E1 is connected with the chip mounting equipment E2, the plurality of environment control equipment E3, the transferring equipment E4 and the sorting equipment E5, and the central control device E1 can control the operation of each equipment; the central control device E1 is, for example, a server, various computer devices, and the like, and is not limited thereto. The chip mounting apparatus E2 may include a robot arm (not shown), which can be controlled by the central control device E1 to take out the chips C on the tray one by one and place the chips C on the electrical connectors 2 of the chip testing apparatus 1 one by one.

As shown in fig. 2, 3 and 4, fig. 4 is a block diagram of the chip testing apparatus 1. The chip testing apparatus 1 is used to carry a plurality of chips C, and the chip testing apparatus 1 can be carried by the transfer equipment E4 and transferred among a plurality of workstations (e.g., a chip mounter E2, a plurality of environmental control equipments E3, a transfer equipment E4, and a sorting equipment E5).

The chip testing device 1 includes: a circuit board 10, a plurality of electrical connection sockets 2, a control unit 3 and at least one power supply member 4. Two opposite sides of the circuit board 10 are respectively defined as a first side 101 and a second side 102. The electrical connection sockets 2 are fixedly disposed on the first side surface 101 of the circuit board 10, and each electrical connection socket 2 is used for carrying a chip C. The form of the electrical connector 2 can vary from chip to chip, without limitation.

In practical applications, the electrical connectors 2 may be divided into a plurality of electrical connector groups, each electrical connector group including at least one electrical connector 2. The control unit 3 is disposed on the second side surface 102 of the circuit board 10, the control unit 3 includes a plurality of test modules 30, and each test module 30 is correspondingly connected to one electrical connection socket group.

Specifically, in fig. 3 of the present embodiment, the circuit board 10 is provided with 96 electrical connectors 2, and the electrical connectors can be divided into 16 electrical connector groups, each electrical connector group includes 6 electrical connectors 2, and the 6 electrical connectors 2 in each electrical connector group are connected to the same test module 30, that is, the circuit board 10 in fig. 3 can be provided with 16 test modules 30. Of course, the number of the electrical connection sockets 2 disposed on the circuit board 10 and the number of the electrical connection socket groups correspondingly partitioned can be changed according to the requirement.

When the test modules 30 are powered, a predetermined test program can be performed on the chips C on the electrical connectors 2, for example, the chips C can be various memories (for example, NAND Flash, etc.), and the test modules 30 can perform at least one of a read test, a write test and an electrical test on the memories. In an embodiment where each test module 30 is used to test the memory, each test module 30 may include a Pattern Generator (PG), a Parametric Measurement Unit (PMU), a Device Power supply module (DPS), and a Driver circuit (Driver).

By the design of connecting the electrical connectors 2 disposed on the circuit board 10 to different test modules 30, the test modules 30 and the chips C connected to the electrical connectors 2 can transmit signals faster and less easily. More specifically, if the circuit board 10 provided with 96 electrical connection sockets 2 is connected to only one signal input source, when the signal emitted from the signal input source is transmitted from one side of the circuit board 10 to the other side of the circuit board 10, the signal is attenuated obviously, which may result in inaccurate chip test results.

In practical applications, all the electrical connectors 2 in each electrical connector group may be connected in parallel, and all the electrical connectors 2 connected in parallel in the same electrical connector group are connected to the same test module 30; in other words, all the electrical sockets 2 to which the respective test modules 30 are connected in parallel. In addition, any electrical connector 2 in each electrical connector group is not connected to any electrical connector 2 in other electrical connector groups. For example, suppose that four electrical connectors 2 are disposed on the circuit board 10: z1, Z2, Q1, Q2, four electrical sockets 2 are divided into two groups of electrical sockets, the first group includes Z1, Z2, the second group includes Q1, Q2, then Z1 and Z2 are connected in parallel, Q1 and Q2 are connected in parallel, Z1 is not connected with Q1 (whether in parallel or in series), Z1 is not connected with Q2 (whether in parallel or in series), Z2 is not connected with Q1 (whether in parallel or in series), and Z2 is not connected with Q2 (whether in parallel or in series).

It should be noted that the electrical connection sockets 2 of different electrical connection socket groups may not be connected to each other, and when the chip testing apparatus 1 fails, the related maintenance personnel may quickly find out the damaged electrical connection socket 2 by testing each electrical connection socket group one by one, and the related maintenance personnel may only replace the damaged electrical connection socket 2, the components of the electrical connection socket 2, the electrical connection socket 2 in the same group or the testing module 30, and the related personnel do not need to replace all the electrical connection sockets 2 or all the testing modules 30 of the whole circuit board 10.

As shown in fig. 3, in practical applications, the chip testing apparatus 1 may further include a housing 31, the housing 31 is fixedly disposed on the second side surface 102 of the circuit board 10, and the housing 31 correspondingly covers the plurality of testing modules 30 to protect the plurality of testing modules 30. In a specific implementation, the housing 31 may also be provided with a related heat dissipation device, such as a fan, a heat dissipation fin, etc., according to requirements. In the embodiment shown in fig. 3, the chip testing apparatus 1 includes only a single housing 31, and the housing 31 correspondingly covers a plurality of testing modules 30, but the number of the housing 31 of the chip testing apparatus 1 is not limited to a single one, and in different applications, the chip testing apparatus 1 may also include a plurality of housings 31, and each housing 31 may be covered with a single testing module 30 or two or three testing modules 30.

The power supply member 4 is disposed on the circuit board 10, the power supply member 4 is connected to the circuit board 10, and the power supply member 4 can be connected to a plurality of test modules 30 through the circuit board 10. The power supply member 4 may be, for example, a board-to-board connector, and may be, for example, but not limited to, a Pogo pin or a reed structure. In fig. 3 of the present embodiment, the power supply member 4 includes a plurality of connection terminals, and the power supply member 4 is disposed on the first side 101 of the circuit board 10 as an example, but the form and number of the power supply members 4, the position of the power supply member 4 disposed on the circuit board, and the like are not limited to those shown in the drawings.

The power supply means 4 is used to connect with an external power supply device, and the external power supply device can supply power to each test module 30 through the power supply means 4, the external power supply device refers to a power supply device independent from the chip testing apparatus 1, and the external power supply device may be any device capable of supplying power, which is not limited herein. That is, in the chip testing apparatus 1, when the external power supply device is not connected to the external power supply device through the power supply means 4, the respective test modules 30 basically perform the predetermined test program on the plurality of chips C connected thereto without electric power. Of course, in different embodiments, the chip testing apparatus 1 may also be provided with at least one battery, the battery is connected to the plurality of testing modules 30, and the battery can supply power to the plurality of testing modules 30.

In another embodiment, the power supply means 4 may comprise a receiving antenna, and the power supply means 4 may receive power wirelessly to provide power to each test module 30. In the embodiment where the power supply component 4 is a receiving antenna, the chip testing apparatus 1 may include a rechargeable battery module, and the power supply component 4 is connected to the rechargeable battery module, and the power supply component 4 can receive power wirelessly to charge the rechargeable battery module; in a specific implementation, the power required by each test module 30 to test the chip C carried by the test module may be supplied from the rechargeable battery module and the external power supply device through the receiving antenna (the power supply component 4). In the embodiment where the power supply member 4 is a receiving antenna, the power supply member 4 may be disposed not exposed from the chip testing apparatus 1, but embedded in the circuit board 10 or hidden in the chip testing apparatus 1. The number of the power feeding members 4 included in each chip test apparatus 1 may be changed according to the demand, and is not limited to a single one, and may be two or more.

As shown in fig. 3, 4 and 10, it is specifically noted that the chip testing device 1 may further include a plurality of first data transmission terminals 8, and a plurality of second data transmission terminals E32 may be correspondingly disposed in the accommodating chamber E311. The plurality of first data transmission terminals 8 and the plurality of second data transmission terminals E32 can contact each other and transfer information with each other. In practical applications, the first data transmission terminals 8 and the second data transmission terminals E32 may be Pogo pins or reeds, but not limited thereto. The number of the first data transmission terminals 8 and the second data transmission terminals E32 and the arrangement positions thereof may be changed according to the needs, and are not limited herein.

In different embodiments, the chip testing apparatus 1 may also include at least one first data transmission antenna (not shown), and the accommodating chamber E311 may be correspondingly provided with at least one second data transmission antenna (not shown). The first data transmission antenna can interact with the second data transmission antenna to transmit information to each other in a wireless manner. In practical applications, the position of the first data transmission antenna is not limited to the accommodation chamber E311, and the first data transmission antenna may be disposed at any position of the environment control device E3 as long as the first data transmission antenna can transmit information with the second data transmission antenna disposed in the accommodation chamber E311.

Referring to fig. 5, fig. 6, fig. 7 and fig. 8 together, fig. 5 is a schematic diagram illustrating each electrical connection socket 2 of the chip testing apparatus 1 disclosed in the present invention, fig. 6 is a schematic diagram illustrating a cross-sectional exploded view of the electrical connection socket 2, fig. 7 is a schematic diagram illustrating a cross-sectional view of the electrical connection socket 2 without the chip C, and fig. 8 is a schematic diagram illustrating a cross-sectional view of the electrical connection socket 2 with the chip C.

Each electrical connector socket 2 comprises: a plurality of probe assemblies 20, a base body 21, a lifting structure 22, a supporting structure 23 and a plurality of elastic assemblies 24. Each probe assembly 20 includes a needle 201 and a spring 202. One end of the pin 201 is used to connect with an electrical connection C1 (shown in fig. 8) of the chip C. The spring 202 is sleeved on the needle body 201, and when one end of the needle body 201 is pressed, the spring 202 is pressed to generate an elastic restoring force correspondingly, so that when the needle body 201 is not pressed any more, the needle body 201 is restored to an uncompressed position under the action of the elastic restoring force.

The base body 21 has a top wall 211 and a circular sidewall 212, the top wall 211 has an opening 21A, one side of the circular sidewall 212 is connected to the periphery of the top wall 211, the other side of the circular sidewall 212 is fixedly disposed on the circuit board 10, and the top wall 211, the circular sidewall 212 and the circuit board 10 together form a receiving slot 21B. Opposite sides of the top wall 211 define an outer side 2111 and an inner side 2112 (shown in FIG. 7). In practical applications, the top wall 211 and the annular side wall 212 may be integrally formed, the base body 21 may further have a plurality of locking holes 21C (as shown in fig. 5), and the plurality of locking holes 21C may cooperate with a plurality of locking members (e.g., screws) to fix the base body 21 to the circuit board 10.

The lifting structure 22 includes a base 221 and a supporting portion 222. The base 221 is completely disposed in the receiving groove 21B, the base 221 extends toward one side to form a bearing portion 222, and a portion of the bearing portion 222 can pass through the opening 21A. The carrying portion 222 extends to a side away from the base portion 221 to form four limiting portions 223, the four limiting portions 223 may be located at four corners of the carrying portion 222, and the four limiting portions 223 and the carrying portion 222 together form a chip accommodating groove 22B, the chip accommodating groove 22B is used for providing a chip C, and the four limiting portions 223 are used for being mutually clamped with the chip C. The lifting structure 22 further has a plurality of connection holes 22A (shown in fig. 6), and each connection hole 22A is disposed through the base portion 221 and the bearing portion 222.

A part of the probe assemblies 20 is fixedly disposed in the supporting structure 23, and the probe assemblies 20 are fixedly disposed at one end of the supporting structure 23 for connecting with the circuit board 10; the other ends of the probe assemblies 20 are located in the connecting holes 22A, and one end of the probe assembly 20 located in the connecting holes 22A is used to connect with the electrical connection portion C1 of the chip C.

In practical applications, the supporting structure 23 may include a base structure 231 and an auxiliary structure 232. The base structure 231 is disposed in the receiving groove 21B, and the base structure 231 and the body 21 are fixed to each other (for example, fixed to the body 21 by a plurality of screws). The base structure 231 has a plurality of through holes, and one end of the probe assemblies 20 are fixedly disposed in the through holes of the base structure 231. The auxiliary structure 232 is disposed in the receiving groove 21B, the auxiliary structure 232 is located between the base structure 231 and the top wall 211, and the auxiliary structure 232 and the base structure 231 are fixed to each other (for example, fastened to each other by screws). The auxiliary structure 232 has a plurality of supporting holes spaced apart from each other, the supporting holes are communicated with the through holes of the base structure 231, the supporting holes are disposed corresponding to the connecting holes 22A, the supporting holes and the through holes together form a plurality of probe channels, and the probe assemblies 20 are disposed corresponding to the probe channels.

As shown in fig. 7, the supporting structure 23 is disposed in the accommodating groove 21B, and the elastic component 24 is disposed between the supporting structure 23 and the lifting structure 22. The elastic assembly 24 enables the base 221 of the lifting structure 22 to abut against the inner side 2112 of the top wall 211, and a gap S is correspondingly formed between the base 221 and the supporting structure 23.

In practical applications, when the electrical connector 2 is fixed on the circuit board 10 and the limiting portion 223 of the electrical connector 2 is not pressed by an external force, the four elastic elements 24 located between the lifting structure 22 and the supporting structure 23 may be slightly compressed, and the elastic restoring force generated by the compression of the elastic elements 24 will make the lifting structure 22 firmly abut against the inner side 2112 of the top wall 211.

As shown in fig. 8, when the chip C is fixedly disposed in the chip accommodating slot 22B and the lifting structure 22 is not pressed, the electrical connection portions C1 of the chip C are correspondingly accommodated in the connection holes 22A, and the probe assemblies 20 are not connected with the electrical connection portions C1 (e.g., do not contact each other). When the lifting structure 22 is pressed, at least a portion of the lifting structure 22 will be retracted into the base body 21, that is, the lifting structure 22 will move toward the circuit board 10 relative to the supporting structure 23, and the probe assemblies 20 will be correspondingly connected to the electrical connections C1 of the chip C.

Referring to fig. 3, 9 and 10 together, fig. 9 is a schematic diagram of an environmental control apparatus E3 according to the present disclosure. A plurality of environment control devices E3 are connected to the central control unit E1, and the central control unit E1 can control any one of the environment control devices E3 to operate independently. Each of the environment control devices E3 is configured to perform a predetermined test procedure on the plurality of chips C disposed on the chip testing apparatus 1 in an environment with a predetermined temperature (e.g., a predetermined high temperature or a predetermined low temperature).

Each environment control device E3 includes: an equipment body E31, a plurality of containing chamber terminals E33 and a plurality of temperature adjusting devices E34. The apparatus body E31 includes a plurality of accommodation chambers E311. The accommodation chamber E311 is mainly used for accommodating the chip testing apparatus 1, and the plurality of accommodation chambers E311 included in the environmental control device E3 may be connected or not connected, which is not limited herein.

It should be noted that in the embodiment where the plurality of chambers E311 included in the environmental control apparatus E3 are independent from each other, but not connected to each other, each chamber E311 may be provided with a movable door, and the environmental control apparatus E3 may be connected to an air extractor. When the chip testing device 1 is disposed in the accommodating chamber E311, the central control device E1 can control the corresponding movable door to operate, so that the accommodating chamber E311 becomes a closed space, and then the central control device E1 can control the air-extracting device to operate, so that the accommodating chamber E311 is in a state similar to vacuum, and thus, the temperature in the accommodating chamber E311 is not easily affected by the external environment.

In the embodiment where the power supply member 4 of the chip testing apparatus 1 includes a plurality of connection terminals, a plurality of chamber terminals E33 may be correspondingly disposed in each chamber E311, and the plurality of chamber terminals E33 are used to connect with the plurality of connection terminals of the chip testing apparatus 1. The position of the housing terminal E33 may be designed according to the position of the chip testing apparatus 1 in the housing E311 and the positions of the plurality of connection terminals of the power feeding member 4, and is not limited thereto. In the embodiment where the power supply member 4 of the chip testing apparatus 1 is a receiving antenna, a transmitting antenna for wireless charging may be correspondingly disposed in each of the accommodating chambers E311, the transmitting antenna is connected to an external power supply device, and when the chip testing apparatus 1 is disposed at a predetermined position in the accommodating chamber E311, the transmitting antenna in the accommodating chamber E311 can be coupled to the receiving antenna (the power supply member 4) of the chip testing apparatus 1, and the external power supply device can provide power to each of the testing modules 30.

Each temperature adjustment device E34 is connected to the central control device E1, and each temperature adjustment device E34 can be controlled by the central control device E1 to make the ambient temperature of the chips C on the plurality of electrical connection sockets 2 of the chip testing device 1 in the corresponding accommodation chamber E311 reach a predetermined temperature.

In one practical example, the plurality of temperature adjustment devices E34 can be divided into a plurality of heating devices E34A and a plurality of cooling devices E34B. A plurality of heating devices E34A provided in the apparatus main body E31, and a plurality of refrigerating devices E34B provided in the apparatus main body E31; the temperature in each of the accommodating compartments E311 can be changed by one of the heating devices E34A or one of the cooling devices E34B to reach a predetermined low temperature or a predetermined high temperature.

Each of the heating devices E34A may include a high temperature contact structure E34a1, and the high temperature contact structure E34a1 is configured to contact a side of the chips C disposed on the chip testing apparatus 1. Each heating device E34A is connected to the central control device E1, and the central control device E1 can control each heating device E34A to operate independently, so that the temperature of the high temperature contact structure E34a1 of each heating device E34A is raised to a predetermined high temperature. The material of the high-temperature contact structure E34a1 may be determined according to a predetermined high-temperature, and a side of the high-temperature contact structure E34a1 contacting the plurality of chips C may be flat.

In a specific application, each high temperature contact structure E34a1 may include various electrothermal heaters (e.g., heating coils), or each high temperature contact structure E34a1 may include a plurality of flow passages, each flow passage providing a high temperature fluid to pass through. Of course, an electric heater or a related heater having a plurality of flow paths may be provided on one side of the high temperature contact structure E34a 1.

Each of the cooling devices E34B may include a low temperature contact structure E34B1, E34B1 for contacting one side of the chips C disposed on the chip testing apparatus 1. Each of the refrigerators E34B is connected to the central control unit E1, and the central control unit E1 can control each of the refrigerators E34B to operate independently to lower the temperature of the low temperature contact structure E34B1 of each of the refrigerators E34B to a predetermined low temperature. The material of the low temperature contact structure E34B1 may be determined according to a predetermined low temperature, and a side of the low temperature contact structure E34B1 contacting the plurality of chips C may be flat. In a specific application, each low temperature contact structure E34B1 may include a plurality of flow passages, each flow passage providing for the passage of the cryogenic fluid, or related components having a plurality of flow passages may be disposed on one side of the low temperature contact structure E34B 1.

In the above embodiment, each heating device E34A includes a high temperature contact structure E34a1, each cooling device E34B includes a low temperature contact structure E34B1, and the heating device E34A and the cooling device E34B respectively contact one side of the chips C through the high temperature contact structure E34a1 and the low temperature contact structure E34B1 to directly perform heat transfer or heat removal on each chip C, so that the temperature of the chips C reaches a predetermined temperature. However, in different applications, each heating device E34A and each cooling device E34B may also be used to make the ambient temperature of the plurality of chips C on the chip testing device 1 reach a predetermined temperature in a non-contact manner, for example, each heating device E34A or each cooling device E34B may directly raise or lower the temperature in the corresponding accommodating chamber E311.

In the above description, the heating device E34A or the cooling device E34B is provided in each of the accommodating chambers E311 as an example, but the temperature adjusting device E34 provided in each of the accommodating chambers E311 is not limited to have only a single heating function or only a single cooling function. In various embodiments, each temperature adjustment device E34 may include both a heater E341 and a refrigerator E342, and each temperature adjustment device E34 may further include a contact structure E343 according to requirements. The heater E341 and the refrigerator E342 can be controlled by the central control device E1 so that the temperature of the contact structure E343 reaches a predetermined high temperature or a predetermined low temperature. The contact structure E343 is used to contact the plurality of chips C disposed on the chip testing apparatus 1, thereby bringing the temperature of the plurality of chips C to a predetermined temperature in a direct contact manner. Of course, in different applications, each temperature adjustment device E34 may not have the contact structure E343, and each temperature adjustment device E34 may pass through the heater E341 or the refrigerator E342 to make the corresponding accommodating chamber E311 reach the predetermined high temperature or the predetermined low temperature.

Referring to fig. 9, 10, 11, 12, 13 and 14, the temperature adjusting device E34 of each environmental control apparatus E3 may be connected to a cover E35. A groove E351 is formed in one side of the cover body E35 in a concave mode, the cover body E35 is provided with an accommodating opening E352, and the accommodating opening E352 is communicated with the groove E351. The cover E35 also has two suction holes E353. Each environmental control equipment E3 may include at least one air extractor E37, and two air extraction holes E353 for connecting with the air extractor E37.

The temperature adjusting device E34 may include the aforementioned contact structures E34a1, E34B1, E343, and one side of the contact structures E34a1, E34B1, E343 may be flat, and the contact structures E34a1, E34B1, E343 may include at least one flow channel E344 therein, and the contact structures E34a1, E34B1, E343 have a fluid inlet E345 and a fluid outlet E346 correspondingly, whereby the high temperature fluid or the low temperature fluid may enter the flow channel E344 through the fluid inlet E345 and then flow out through the fluid outlet E346, and thereby the temperature of the contact structures E34a1, E34B1, E343 may reach a predetermined temperature by flowing uninterruptedly in the flow channel E344.

In practical applications, the cover E35 may further be fixedly disposed with a cover E36, an accommodating space SP1 may be correspondingly formed between the cover E36 and the temperature adjustment device E34, and the accommodating space SP1 may be filled with any component capable of blocking heat energy transfer.

Referring to fig. 14 and 15, fig. 14 shows a schematic view of the electrical connection socket 2 of the chip testing device 1 and the chip C disposed thereon contacting with the contact structures E34a1, E34B1 and E343 of the temperature adjustment device E34, and fig. 15 is a partially enlarged schematic view of fig. 14. As shown in the figure, when the cover E35 abuts against one side of the circuit board 10, the cover E35, the contact structures E34a1, E34B1, E343 and the circuit board 10 together form a closed space SP2, and the electrical connectors 2 are correspondingly located in the closed space SP 2; meanwhile, a plurality of connection terminals of the power supply member 4 may be correspondingly connected to a plurality of receiving chamber terminals E33.

As shown in fig. 8 and fig. 15, in the process that the central control device E1 controls the pumping apparatus to operate to pump the gas in the enclosed space SP2 outwards through the pumping hole E353 of the cover E35, so that the enclosed space SP2 is in a state of being close to vacuum or vacuum, the contact structures E34a1, E34B1, E343 will press against the lifting structures 22 of the electrical connectors 2, and each lifting structure 22 will move relative to the base body 21 in the direction of approaching the circuit board 10, and the plurality of probe assemblies 20 will be correspondingly connected to the plurality of electrical connectors C1 of the chips C, and the contact structures E34a1, E34B1, E343 will be correspondingly pressed against one side of the plurality of chips C; in other words, during the process of pumping out the gas in the enclosed space SP2, the contact structures E34a1, E34B1 and E343 will press against the lifting structure 22 of the respective electrical socket 2, and the lifting structure 22 of the electrical socket 2 will be transformed from the state shown in fig. 8 to the state shown in fig. 15.

In practical applications, the central control device E1 controls the air-extracting device, and the time point for extracting the air in the enclosed space SP2 can be designed according to the requirement. For example, the central control device E1 may control the operation of the air-extracting device to extract the air in the enclosed space SP2 when the plurality of connection terminals (shown in fig. 3) included in the power supply member 4 are connected to the accommodating chamber terminal E33 (shown in fig. 10); alternatively, the central control device E1 may determine whether the chip testing device 1 is already disposed at a predetermined position in the accommodating chamber E311 by at least one sensor (e.g., an optical sensor or a mechanical pressing sensor) disposed in the accommodating chamber E311 (as shown in fig. 9), and the central control device E1 controls the air pumping device to operate to pump out the air in the enclosed space SP2 when the chip testing device 1 is determined to be located at the predetermined position in the accommodating chamber E311 by the sensor.

As shown in fig. 10 and 15, when the air extracting device E37 extracts the air in the enclosed space SP2, and the contact structures E34a1, E34B1, E343 are correspondingly abutted against one side of the chips C, and the probe assemblies 20 of each electrical connection socket 2 are connected to the electrical connection portions C1 of the chip C disposed thereon, the central control device E1 may control the temperature adjusting device E34 to actuate, so that the contact structures E34a1, E34B1, E343 reach a predetermined temperature, and the central control device E1 may control the test module 30 connected to each electrical connection socket 2 to perform a predetermined test procedure on the chip C when the temperatures of the contact structures E34a1, E34B1, E343 reach the predetermined temperature.

Through the cooperation of the cover body E35 and the air extractor E37, the acting force required by the contact structures E34a1, E34B1, E343 to press against the lifting structures 22 of the electrical connectors 2 at the same time can be greatly reduced, that is, the acting force required by the lifting device E38 (described in detail later) to make the chips C carried by the chip testing apparatus 1 to press against the contact structures E34a1, E34B1, E343 at the same time can be reduced.

Referring to fig. 1 and 2 again, the transfer equipment E4 is disposed between the environmental control equipments E3, and the transfer equipment E4 is used for carrying the chip testing apparatus 1. The transfer apparatus E4 may comprise a robot and a holding component for holding the chip testing device 1. The central control device E1 is connected to the transfer facility E4, and the central control device E1 can control the transfer facility E4, so that the chip testing apparatus 1 carrying a plurality of chips C is installed in any one of the accommodation chambers E311 (shown in fig. 9) of any one of the environment control facilities E3. In contrast, the transfer device E4 may be controlled by the central control device E1 to move the chip testing apparatus 1 disposed in any of the accommodating chambers E311 out of the accommodating chamber E311.

The sorting apparatus E5 is connected to the central control device E1, and the sorting apparatus E5 can be controlled by the central control device E1 to detach the chips C from the electrical connectors 2 of the chip testing apparatus 1, and the sorting apparatus E5 can place the chips C on a tray of a good area a1 or a tray of a defective area a2 according to the test results of the chips C after passing a predetermined test procedure. The sorting device E5 may, for example, comprise a robot arm. In an embodiment where the sorting apparatus E5 and the chip mounting apparatus E2 are disposed at adjacent positions, the chip mounting apparatus E2 and the sorting apparatus E5 may share the same robot arm. In practical applications, the good area a1 may be divided into a plurality of areas according to requirements, and the sorting apparatus E5 may arrange the chips C in different areas of the good area a1 according to the test results of the chips C after passing through the predetermined test procedures, for example, the chips C may be distinguished according to the operation performance of the chips C.

Fig. 16 is a schematic flow chart of a chip testing method according to a first embodiment of the present invention. The chip test system E may perform a predetermined test procedure on the plurality of chips C by using a chip test method including:

a chip mounting step S1: transferring a plurality of chips (C) from a carrying tray to a plurality of electric connection seats (2) of a chip testing device (1) by a chip mounting device (E2);

a shift to step S2: transferring a chip testing device (1) carrying a plurality of chips (C) to one of the accommodating chambers (E311) of one of the environment control devices (E3);

a temperature adjustment step S3: controlling a temperature adjusting device (E34) in the accommodating chamber (E311) to operate so as to enable the plurality of chips (C) to be in an environment with a preset temperature;

a test step S4: supplying power to a chip testing device (1) arranged in the accommodating chamber (E311) so that each testing module (30) performs a preset testing program on a plurality of chips (C) connected with the testing module;

a shift-out step S6: removing the chip testing device (1) from the accommodating chamber (E311), and transferring the chip testing device (1) to a sorting device (E5);

a classification step S7: a sorting device (E5) is used for placing a plurality of chips (C) into a good product area (A1) or a defective product area (A2) respectively according to the test results of the chips (C) after the chips (C) complete the predetermined test procedures.

In the embodiment where the power supply component 4 of the chip testing apparatus 1 includes a plurality of connection terminals, before the testing step S4, a connection step may be further included: the plurality of connection terminals of the power feeding member 4 of the chip testing apparatus 1 are connected to the plurality of housing chamber terminals E33 provided in the housing chamber E311. In an embodiment, the connection step may be located between the moving-in step S2 and the temperature adjustment step S3, or the connection step may be located between the temperature adjustment step S3 and the test step S4.

Fig. 17 is a schematic flow chart of a chip testing method according to a second embodiment of the present invention. The biggest difference between this embodiment and the embodiment shown in fig. 16 is that: an air-extracting step S21 may be further included between the moving step S2 and the temperature adjusting step S3. In the moving-in step S2, the enclosure E35 disposed in the accommodating chamber E311 and the circuit board 10 of the chip testing apparatus 1 are connected to each other, so that the enclosure E35 and the circuit board 10 form a closed space SP2 (as shown in fig. 14), and then, in the air exhausting step S21, the air exhausting device connected to the closed space SP2 is operated to exhaust the air in the closed space SP2 outward.

As shown in fig. 14 and described in the corresponding embodiment, when the cover body E35 and the circuit board 10 form the enclosed space SP2, each electrical connector 2 is located in the enclosed space SP 2. After the air-extracting step S21 is performed, each electrical connector 2 will be located in a near vacuum environment, so that, when the temperature adjusting step S3 is performed subsequently, the temperature of the enclosed space SP2 will not be affected by the external environment, and the ambient temperature of the electrical connector 2 and the chip C carried thereby will be easily maintained at the predetermined temperature.

Fig. 18 is a schematic flow chart of a chip testing method according to a third embodiment of the present invention. The present embodiment is different from the previous embodiments in the following point: between the test step S4 and the shift-out step S6, the following steps may be included:

a separation step S5: after the chip testing device (1) completes a predetermined test program for all chips (C) connected thereto, the power supply member (4) of the chip testing device (1) is controlled to be separated from the plurality of housing chamber terminals (E33) in the housing chamber (E311).

As shown in fig. 3, 9 and 10, in practical applications, the environmental control apparatus E3 may further include a plurality of lifting devices E38, and each of the accommodating chambers E311 is provided with one lifting device E38. Each lifting device E38 is connected to a central control device E1. Each of the elevating devices E38 is controlled by the central control device E1 to elevate the chip testing apparatus 1 disposed in the housing chamber E311, so that the plurality of connection terminals of the power supply member 4 of the chip testing apparatus 1 are connected to or separated from the housing chamber terminal E33.

In practical applications, when each chip testing apparatus 1 is transferred into the accommodating chamber E311 by the transfer apparatus E4, the power supply members 4 of the chip testing apparatus 1 may not be connected to the accommodating chamber terminals E33, and when the central control apparatus E1 determines that a chip testing apparatus 1 is disposed in any one of the accommodating chambers E311, the central control apparatus E1 may control the corresponding lifting apparatus E38 to move the chip testing apparatus 1 in the accommodating chamber E311, so that the connection terminals of the power supply members 4 are connected to the accommodating chamber terminals E33, whereby the external power supply apparatus can provide power to the test modules 30 through the power supply members 4.

In practical applications, how the central control device E1 determines whether the chip testing device 1 is disposed in any of the accommodating chambers E311 may be designed according to requirements, and is not limited herein. For example, a sensor (e.g., an optical sensor or any mechanical push switch) may be disposed in the housing E311, and when the chip testing device 1 enters the housing E311, the sensor correspondingly generates a relevant signal and transmits the relevant signal to the central control device E1, and the central control device E1 may determine whether the chip testing device 1 is disposed in the housing E311 according to the signal transmitted by the sensor. Of course, the sensor may be used to confirm whether the chip testing device 1 is disposed at a predetermined position in the accommodating chamber E311, and the sensor may transmit a corresponding signal to the central control device E1 according to the position of the chip testing device 1 in the accommodating chamber E311, the central control device E1 may determine whether the chip testing device 1 is disposed at the predetermined position in the accommodating chamber E311 according to the signal transmitted by the sensor, and if the central control device E1 determines that the chip testing device 1 is disposed at the predetermined position in the accommodating chamber E311, the central control device E1 may control the lifting device E38 to operate; on the contrary, if the central control device E1 determines that the chip testing device 1 is not located at the predetermined position in the accommodating chamber E311, the central control device E1 may control the related warning device to operate to warn the user, for example, the central control device E1 may control the related warning lamp to emit light of a specific color, control the related display screen to display an error message, and the like.

In the embodiment where the power supply member 4 is a receiving antenna, when the chip testing apparatus 1 is disposed in the accommodating chamber E311, the corresponding transmitting antenna in the accommodating chamber E311 may be coupled to the receiving antenna, and the chip testing apparatus 1 may obtain power through the power supply member 4. Of course, in another embodiment, the receiving antenna may be coupled to the receiving antenna when the chip testing device 1 is disposed at a predetermined position in the accommodating chamber E311, which is not limited herein.

As shown in fig. 3 and 10, in the embodiment where each temperature adjustment device E34 has the aforementioned contact structures E34a1, E34B1, and E343, when the lifting device E38 is controlled to operate, the chip testing apparatus 1 and the chips C carried by the chip testing apparatus are driven by the lifting device E38 to move toward the contact structures E34a1, E34B1, and E343 or move away from the contact structures E34a1, E34B1, and E343.

In the embodiment where the temperature adjustment device E34 is connected with the cover body E35, when the lifting device E38 is controlled to move the chip testing apparatus 1 to the predetermined position in the direction of the contact structures E34a1, E34B1 and E343, the cover body E35 is correspondingly covered on the circuit board 10 of the chip testing apparatus 1, and the cover body E35 forms the enclosed space SP2 together with the circuit board 10. Then, before the temperature adjustment step S3, the central control device E1 controls the air extraction device E37 to extract air from the enclosed space SP2 so that the enclosed space SP2 is in a state close to vacuum, and thus, after the temperature adjustment step S3, the temperature in the enclosed space SP2 is not easily affected by the external environment.

In practical applications, when the chip testing apparatus 1 is disposed in the accommodating chamber E311 and the lifting device E38 lifts the chip testing apparatus 1, the chips C may not contact with the contact structures E34a1, E34B1, and E343, and when the air extractor E37 starts to extract air, the chips C and the contact structures E34a1, E34B1, and E343 may contact with each other, but not limited thereto. In another embodiment, the plurality of chips C may also be in contact with the contact structures E34a1, E34B1 and E343 when the air extracting device E37 is not extracting air.

In the testing step S4, the chip testing apparatus 1 is coupled or connected to the corresponding transmitting antenna or the receiving chamber terminal through the receiving antenna or the plurality of connecting terminals, so as to obtain power, and each testing module 30 can test the chip C connected thereto.

As shown in fig. 9 and 10, in practical applications, in order to firmly connect the plurality of connection terminals of the power supply member 4 of the chip testing apparatus 1 and the plurality of receiving chamber terminals E33, the environmental control device E3 may further include a plurality of position-limiting devices E39, and the plurality of position-limiting devices E39 are disposed in the plurality of receiving chambers E311. Each of the stopper devices E39 is connected to a central control device E1. Each of the position-limiting devices E39 can be controlled by the central control device E1 to limit the moving range of the chip testing device 1 in the accommodating chamber E311. The specific structure of the position-limiting device E39 can be designed according to the requirement, for example, the chip testing device 1 can be provided with a locking hole, and the position-limiting device E39 includes a corresponding hook structure, when the position-limiting device E39 is actuated, the hook structure can be correspondingly locked in the locking hole; alternatively, the stopper E39 may include a plurality of retractable pins, and the retractable pins may be inserted into the engaging holes of the chip testing apparatus 1.

In the embodiment where the accommodation chamber E311 of each environmental control apparatus E3 has the contact structures E34a1, E34B1, E343, the lifting device E38 and the limiting device E39, the chip testing method may include the following steps in the moving step S2:

a step of moving into the accommodating chamber: moving the chip testing device (1) into the accommodating chamber (E311);

a rising step: controlling a lifting device (E38) in the accommodating chamber (E311) to enable the chip testing device (1) to move towards the contact structures (E34A1, E34B1 and E343);

a locking step: controlling a limiting device (E39) in the accommodating chamber (E311) to enable the limiting device (E39) to limit the moving range of the chip testing device (1) in the accommodating chamber (E311).

In summary, the chip testing method of the present invention may be that a plurality of chips are mounted on the chip testing device 1; next, the chip testing apparatus 1 is moved into one of the accommodating chambers E311 of the environmental control device E3; then, the lifting device E38 is controlled to lift the chip testing device 1, so that one side of the chips C of the chip testing device 1 is adjacent to the contact structures E34a1, E34B1 and E343 of the temperature adjusting device E34, and the cover body E35 connected with the temperature adjusting device E34 is covered on the circuit board 10 of the chip testing device 1 to form a closed space SP 2; subsequently, the air extractor E37 is controlled to extract air from the enclosed space SP2, so that one side of the chips C on the chip testing apparatus 1 is attached to the contact structures E34a1, E34B1, E343, and the temperature regulator E34 is controlled to operate, so that the chips C reach a predetermined temperature; when the temperature adjusting device E34 is activated, power is supplied to the chip testing apparatus 1 so that the plurality of test modules 30 test the plurality of chips C.

Referring to fig. 19, which is a flowchart illustrating a fourth embodiment of the chip testing method according to the present disclosure, the chip testing system E can test a plurality of memories (i.e., the chips) by using the chip testing method. The chip testing method disclosed by the embodiment is different from the chip testing method in the following point: after moving to step S2 and before the separating step S5, the temperature adjusting step S3 and the testing step S4 may be repeatedly performed twice, which are the temperature adjusting step S31, the testing step S41, the temperature adjusting step S32, and the testing step S42, respectively.

In the temperature adjusting step S31 and the testing step S41 (i.e., the temperature adjusting step S3 and the testing step S4 are executed for the first time), the temperature adjusting device E34 corresponding to the accommodating chamber E311 is controlled to enable the chips C to be in an environment with a temperature above 115 ℃, and then each testing module 30 is controlled to perform at least one of a read test, a write test and an electrical test on the chips C. The temperature adjustment step S31 and the test step S41 are performed to Burn-In (Burn-In) the memory.

In the temperature adjusting step S32 and the testing step S42 (i.e., the temperature adjusting step S3 and the testing step S4 are executed for the second time), the temperature adjusting device E34 corresponding to the accommodating chamber E311 is controlled to enable the chips C to be in an environment with a temperature of 75 ℃ to 95 ℃, and then each testing module 30 is controlled to perform at least one of a read test, a write test and an electrical test on the chips C. The temperature adjustment step S31 and the test step S41 are performed to test the memory at a high temperature.

Specifically, in various embodiments, the test step S41 and the temperature adjustment step S32 may include a shift-out step and a shift-in step; the moving-out step is to move the chip testing device 1 out of the current chamber E311, and the moving-in step is to move the chip testing device 1 into another chamber E311. That is, the chip testing apparatus 1 can be sequentially located in two different chambers E311 (which can be located in the same environmental control equipment E3 or in different environmental control equipment E3) with a temperature above 115 ℃ and a temperature between 75 ℃ and 95 ℃ for testing.

Referring to fig. 20, which is a flowchart illustrating a fifth embodiment of the chip testing method according to the present disclosure, the chip testing system E can test a plurality of memories (i.e., the chips) by using the chip testing method. The chip testing method disclosed in this embodiment is different from the chip testing method shown in fig. 19 in that: after moving to step S2 and before the separating step S5, the temperature adjusting step S3 and the testing step S4 may be repeated three times, which are the temperature adjusting step S31, the testing step S41, the temperature adjusting step S32, the testing step S42, the temperature adjusting step S33 and the testing step S43, respectively.

After the temperature adjusting step S32 and the testing step S42 are performed, the temperature adjusting step S33 and the testing step S43 (i.e., the temperature adjusting step S3 and the testing step S4 are performed for the third time) are performed by controlling the temperature adjusting device E34 corresponding to the accommodating chamber E311 to make the chips C in the environment with the temperature of-55 ℃ to-35 ℃, and then controlling each testing module 30 to perform at least one of the read test, the write test and the electrical test on the chips C. In other words, the chip testing method disclosed In this embodiment sequentially performs a Burn-In (Burn-In) test, a high temperature test, and a low temperature test on the plurality of chips C.

Referring to fig. 21, which is a flowchart illustrating a sixth embodiment of the chip testing method according to the present disclosure, the chip testing system E can test a plurality of memories (i.e., the chips) by using the chip testing method. The chip testing method disclosed in this embodiment is different from the chip testing method shown in fig. 19 in that: after moving to step S2 and before the separating step S5, the temperature adjusting step S3 and the testing step S4 may be repeated four times, which are the temperature adjusting step S31, the testing step S41, the temperature adjusting step S32, the testing step S42, the temperature adjusting step S33, the testing step S43, the temperature adjusting step S34, and the testing step S44, respectively.

After the temperature adjusting step S33 and the testing step S43 are performed, the temperature adjusting step S34 and the testing step S44 (i.e., the temperature adjusting step S3 and the testing step S4 are performed for the fourth time) are performed by controlling the temperature adjusting device E34 corresponding to the accommodating chamber E311 to make the chips C in the environment with the temperature of 20 ℃ to 30 ℃ (normal temperature), and then controlling each testing module 30 to perform at least one of the read test, the write test and the electrical test on the chips C. In other words, the chip testing method disclosed In this embodiment sequentially performs a Burn-In (Burn-In) test, a high temperature test, a low temperature test, and a normal temperature test on the plurality of chips C.

In view of the above, the chip testing method of the present embodiment can be performed by using the chip testing system E in which the temperature adjustment devices E34 of the environmental control apparatuses E3 have the refrigerators E342 and the heaters E341 at the same time in the foregoing description. After the chip testing apparatus 1 is moved into the accommodating chamber E311 of the environment control device E3, at least one of a read test, a write test, and an electrical test is sequentially performed In an environment at a temperature of 115 ℃ or higher, an environment at a temperature of 75 ℃ to 95 ℃, an environment at a temperature of-55 ℃ to-35 ℃, and an environment at a temperature of 20 ℃ to 30 ℃, that is, a Burn-In (Burn-In) test, a high temperature test, a low temperature test, and a normal temperature test are sequentially performed on the plurality of chips C. Of course, In practical applications, the chip testing apparatus 1 may perform the Burn-In (Burn-In) test, the high temperature test, the low temperature test and the normal temperature test on the plurality of chips C In the sequence, which may be arranged according to the requirement, and is not limited to the above sequence.

Referring to fig. 22, which is a flowchart illustrating a chip testing method according to a seventh embodiment of the present disclosure, the chip testing system E can test a plurality of memories (i.e., the chips) by using the chip testing method. The chip testing method disclosed in this embodiment is different from the chip testing method shown in fig. 19 in that: the following steps may be included between the shift-out step S6 and the sorting step S7:

a move-in step SX 1: transferring a chip testing apparatus (1) carrying a plurality of chips (C) to an accommodating chamber (E311) of another environment control device (E3);

a temperature adjustment step SX 2: controlling the operation of a temperature regulating device (E34) in the accommodating chamber (E311) so that the plurality of chips (C) are in an environment of-55 ℃ to-35 ℃;

a test step SX 3: power is supplied to a chip testing device (1) arranged in the accommodating chamber (E311) so that each testing module (30) performs a predetermined testing procedure on a plurality of chips (C) connected with the testing module.

In the chip testing method of the present embodiment, the chip testing apparatus 1 is first disposed in the accommodating chamber E311 of one of the environment control devices E3, and the plurality of chips C are sequentially subjected to at least one of a read test, a write test, and an electrical test in an environment with a temperature of 115 ℃ or higher and in an environment with a temperature of 75 ℃ to 95 ℃; then, the chip testing apparatus 1 is moved out of the containing chamber E311, and the chip testing apparatus 1 is moved into one of the containing chambers E311 of different environmental control devices E3 (or moved into another containing chamber E311 of the same environmental control device E3); subsequently, the temperature control device E34 of the accommodating chamber E311 operates to enable the plurality of chips C carried by the chip testing apparatus 1 to be at least one of a read test, a write test and an electrical test in an environment with a temperature of-55 ℃ to-35 ℃.

The chip testing method of the present embodiment may be performed by using the chip testing system E in the foregoing description, and particularly, the chip testing system E in which only the heating device E34A or only the cooling device E34B is disposed in each accommodating chamber E311 of each environmental control apparatus E3.

In the chip testing method of the present embodiment, since the temperature of the single accommodating chamber E311 is not decreased from the temperature of more than 100 ℃ to the temperature of less than 0 ℃, the time required for the temperature around each chip C to reach the predetermined high temperature and the predetermined low temperature can be greatly shortened, and the energy consumed for the temperature adjusting devices E34 to reach the predetermined temperature in the accommodating chamber E311 can be greatly reduced.

As shown in fig. 23, which is a flowchart illustrating an eighth embodiment of the chip testing method disclosed in the present invention, the chip testing system E can test a plurality of memories (i.e., the chips) by using the chip testing method. The chip testing method disclosed by the embodiment is different from the chip testing method in the following point: after the temperature adjustment step SX2 and the test step SX3, a temperature adjustment step SX4 and a test step SX5 may be further included. In the temperature adjusting step SX4, the temperature adjusting device E34 in the chamber E311 is controlled to operate, so that the plurality of chips C are in an environment of 20 ℃ to 30 ℃. In the testing step SX5, power is supplied to the chip testing apparatus 1 disposed in the accommodating chamber E311, so that each testing module 30 performs a predetermined testing procedure on the plurality of chips C connected thereto. That is, in the temperature adjustment step SX2 and the test step SX3, the plurality of chips C are tested in a low temperature environment, and in the temperature adjustment step SX4 and the test step SX, the plurality of chips C are tested in a normal temperature environment.

Referring to fig. 24, which is a flowchart illustrating a ninth embodiment of the chip testing method according to the disclosure, the chip testing system E can test a plurality of memories (i.e., the chips) by using the chip testing method. The chip testing method disclosed by the embodiment is different from the chip testing method in the following point: when the chip testing device 1 is brought into contact with the contact structures E34a1, E34B1, E343 to complete the predetermined testing procedure, and the chip testing device 1 is removed from the accommodating chamber E311 (i.e. after any one of the removing steps), the following steps may be performed:

a position test step SY 1: extracting images of a plurality of electric sockets (2) and a plurality of chips (C) arranged on the electric sockets by using an image extraction unit in a position detection device E8 to generate extracted image information;

a determination step SY 2: and judging whether the positions of the chips relative to the corresponding electric connection seats accord with the allowable deviation amount or not according to the extracted image information. If the positions of the chips relative to the corresponding electrical connection seats accord with the allowable deviation amount, the chip testing device (1) is continuously transferred to the next workstation or another containing chamber (E311) so as to test the chips (C) in another temperature environment. The work station is, for example, transferred to a sorting facility (E5) to perform a sorting operation. If the positions of the chips relative to the corresponding electric connection seats do not accord with the allowable deviation amount, the chips are reinstalled.

In practical applications, if the positions of the plurality of chips with respect to the corresponding electrical sockets do not match the allowable deviation amount, the central control unit E1 controls the transfer device E4 to transfer the chip testing apparatus 1 to the chip mounter E2, and then the chip mounter E2 is used to re-mount the specific chip C, or all the chips C may be re-mounted. Of course, the chip C on the chip testing apparatus 1 may be remounted by another robot arm or the like different from the chip mounting apparatus E2; alternatively, the central control device E1 may control the transfer device E4 to transfer the chip testing apparatus 1 to a temporary storage area and send out related prompt signals to notify related personnel. In practical applications, the position detecting apparatus E8 may also include a chip mounting device (not shown, for example, including a stage and a robot), and the chip mounting device may directly perform a re-mounting operation on at least one chip C on the chip testing apparatus 1. The position testing step SY1 and the determining step SY2 in this embodiment may be arranged after any step of removing the chip testing apparatus 1 according to the requirement.

Referring back to fig. 1 and fig. 3, in practical applications, the chip testing system E may further include two image capturing units E91 and E92, where the two image capturing units E91 and E92 are connected to the central control device E1. The image extracting unit E91 is disposed adjacent to the chip mounting device E2, the chip mounting device E2 is used for mounting the chip C on the chip testing apparatus 1, and the image extracting unit E91 is used for extracting the image of the chip testing apparatus 1 and the chip C carried by the chip testing apparatus 1; the central control device E1 can judge whether the chip C on the chip testing device 1 is correctly mounted after receiving the image information extracted by the image extracting unit E91; if the central control device E1 determines that the chip C is not correctly mounted on the chip testing device 1, the central control device E1 may control the chip mounting apparatus E2 to re-mount the chip C.

The image extracting unit E92 is disposed adjacent to the sorting apparatus E5, the image extracting unit E92 is used for extracting the image of the chip C disposed in the defective region or the good region, and the central control device E1 can receive the image extracted by the image extracting unit E92 to determine whether the chip C is correctly mounted (e.g., mounted on a tray). If the central control device E1 determines that the chip C is not properly mounted, the central control device E1 may control the sorting apparatus E5 or the adjacent related robot or chip mounting apparatus E2 to re-mount the chip C.

Referring to fig. 1 again, the chip testing system E of the present invention may further include a Pre-Test (Pre-Test) device E6. The pretest equipment E6 is connected to the central control unit E1. The pre-test equipment E6 may include at least one electrical connector (the specific structure of the electrical connector may be the electrical connector 2 shown in fig. 5 and 6), and the electrical connector of the pre-test equipment E6 is used to carry a chip C. The pre-Test equipment E6 can perform an Open/Short Test (Open/Short Test) and a Leakage current Test (Leakage Test) on the chip C. In a specific application, the pre-test equipment E6 may include the chip testing apparatus 1 shown in FIG. 3, and the pre-test equipment E6 may test the chip C by the chip testing apparatus 1 shown in FIG. 3.

In the embodiment of the chip testing system E applied to testing memories, particularly NAND Flash, the performance of the overall test can be greatly improved by performing the short circuit test and the leakage current test on a plurality of memories (i.e. the chip C) through the pre-test equipment E6 with the chip testing device 1. Specifically, the memory needs to spend a lot of time in the high temperature Test, the burn-in Test, the low temperature Test and the normal temperature Test, so that the memory is preliminarily screened by the pre-Test device E6, each electrical connector 2 on the chip Test apparatus 1 can be effectively utilized, and the problem that the electrical connector 2 is occupied by the memory which does not pass the Short circuit Test (Open/Short Test) and the Leakage current Test (Leakage Test) in the subsequent Test process can be avoided. In different applications, the pre-test equipment E6 may perform a short-circuit test and a leakage current test on the memory, and the pre-test equipment E6 may perform a specific DC electrical test on the memory and a Read operation (Read ID) on each location of the memory according to the requirement.

In various embodiments, before the classifying step S7, a final testing step may be included, which includes:

an installation step: mounting a plurality of chips on an electrical connection socket of a final test device;

a testing step: controlling the final Test equipment to perform an Open/Short Test (Open/Short Test) and a Leakage current Test (Leakage Test) on the chip mounted on the final Test equipment;

a judgment step: judging whether a chip arranged on a pre-test device passes a short circuit test and a leakage current test; if the chip fails the short circuit test or the leakage current test, the chip is transferred to the defective area in the classification step.

The electrical connector included in the final test apparatus may be the same as the electrical connector 2 shown in fig. 5 and 6, but is not limited thereto. Through the setting of the final test equipment, the speed of the classification equipment can be assisted to be accelerated. Specifically, when the sorting device sorts each chip, each chip is moved to a specific area according to the test result of the chip in each test process, so that when one chip is damaged unexpectedly in the test process and the chip fails any test, the sorting device wastes much time in sorting the chip without the final test step. In practical applications, the final test equipment, the chip mounting equipment E2, and the preliminary test equipment E6 may be configured to perform a chip mounting operation using the same robot arm, but not limited thereto, and the final test equipment, the chip mounting equipment E2, and the preliminary test equipment E6 may be configured to have separate robot arms.

As shown in fig. 25, which is a flowchart illustrating a tenth embodiment of the chip testing method disclosed in the present invention, the chip testing system E can test a plurality of memories (i.e. the chips) by using the chip testing method. The chip testing method disclosed by the embodiment is different from the chip testing method in the following point: before the chip mounting step S1, a pre-test step may be further included, which includes:

a mounting step S01: taking down a plurality of memories (chips C) from the carrying disc one by one and installing the memories (chips C) on an electric connection seat of a pre-testing device (E6);

a test step S02: controlling the pre-test equipment (E6) to perform a short circuit test and a leakage current test on the memory (chip C);

a determination step S03: if the memory (chip C) passes the short circuit test and the leakage current test, the chip mounting step S1 is executed; if the memory (chip C) fails the short circuit test or the leakage current test, the memory (chip C) is transferred to the defective area (a 2).

As shown in fig. 1, in practical applications, the pre-testing apparatus E6 may be disposed between a tray loading apparatus E7 and a chip mounting apparatus E2, and at least one robot arm may be disposed between the pre-testing apparatus E6, the tray loading apparatus E7 and the chip mounting apparatus E2; the mechanical arm can be an electric connection socket which is firstly placed on the pre-testing device E6 after the internal memory (chip) on the carrying disc of the carrying disc feeding device E7 is detached; if the memory (chip) passes the short circuit test and the leakage current test, the mechanical arm takes off the chip and mounts the chip on the electric connection socket 2 of the chip testing device 1 arranged on the chip mounting equipment E2; if the memory (chip) does not pass the short circuit test and the leakage current test, the mechanical arm places the memory (chip) in another defective product area A3; in practical applications, the chip mounting apparatus E2 and the pre-test apparatus E6 may use the same robot to transfer the chips, but not limited thereto, and in different embodiments, the chip mounting apparatus E2 and the pre-test apparatus E6 may have different robots, respectively.

As shown in fig. 26, in a different embodiment, after each test module 30 completes a predetermined test procedure on the chips C on the electrical connectors 2 connected thereto, the test module 30 may write the test result data C2 and the corresponding test parameter data C3 of each chip C into each chip C, so that the test result data C2 and the test parameter data C3 are stored in each chip C.

More specifically, the test result data C2 may include, for example: the test conditions of the chip C in the high temperature test, the pre-burning test, the low temperature test and the normal temperature test may be respectively determined, or only whether the chip C passes the high temperature test, the pre-burning test, the low temperature test and the normal temperature test may be recorded.

The test parameter data C3 may include, for example: an identification Number (ID Number) of the chip testing apparatus 1, an identification Number of the test module 30, an identification Number of the electrical connector 2, an identification Number of the environmental control device E3 and an identification Number of the housing chamber E311 thereof, a temperature value at the time of high temperature test, a temperature value at the time of burn-in test, a temperature value at the time of low temperature test, a temperature value at the time of normal temperature test, and the like.

By the above design that the test module 30 writes the test result data C2 and the test parameter data of the chip C into the chip C, when any chip C is handed to a consumer, the consumer can read the data stored in the chip C through the relevant device to confirm the detection state during the production; when the relevant manufacturer receives any chip C returned by the consumer, the testing result data C2 and the testing parameter data stored in the chip C can be read to quickly trace the testing process of the chip C, thereby effectively helping the manufacturer to find out the possible defects in the testing process.

As shown in fig. 27, which is a flowchart illustrating an eleventh embodiment of the chip testing method disclosed in the present invention, the chip testing system E can test a plurality of memories (i.e. the chips) by using the chip testing method. The chip testing method disclosed by the embodiment is different from the chip testing method in the following point: the following steps may also be included after each testing step:

a test result writing step SW: and storing the test result data after each memory completes the preset test program and the corresponding test parameter data in each memory.

In the above embodiment, when each test module 30 completes any test (for example, including a high temperature test, a burn-in test, a low temperature test, and a normal temperature test) on the memory connected thereto, the corresponding test result data C2 and the test parameter data C3 are immediately stored in the memory, but in practical applications, the invention is not limited thereto.

Referring to fig. 4 again, in different applications, each test module 30 may include a processing unit 5 and at least one storage unit 6. When each test module 30 completes any test (for example, a high temperature test, a burn-in test, a low temperature test, and a normal temperature test) on the memory on the electrical connectors 2 connected thereto, the test module 30 may store the test result data C2 and the test parameter data C3 of each chip C in the storage unit 6 of each test module 30 without directly storing the corresponding test result data C2 and the corresponding test parameter data C3 in the memory. In another embodiment, the chip testing apparatus 1 may include a storage unit, and each testing module 30 may store the testing result data C2 and the testing parameter data C3 of the chip C connected thereto in the storage unit of the chip testing apparatus 1. In other words, the chip testing apparatus 1 may include the storage unit 6, and the storage unit 6 may be disposed in each testing module 30 according to the requirement, or the storage unit 6 may be disposed independently of the testing modules 30.

In summary, when the memory carried by the chip testing apparatus 1 completes all tests (such as a burn-in test and a high temperature test, or a burn-in test, a high temperature test, a low temperature test, and a normal temperature test) according to requirements, the central control apparatus E1 may control a read-write device (not shown) to connect with the plurality of connection terminals of the power supply member 4 of the chip testing apparatus 1, so as to read out the storage unit of the chip testing apparatus 1 or the storage unit 6 of each testing module 30, the stored test result data C2, and the stored test parameter data C3, and write each test result data C2 and the test parameter data C3 into the corresponding memory through the read-write device.

In another embodiment, the chip testing apparatus 1 may also include a wireless transmission unit 7, and the wireless transmission unit 7 is connected to the processing unit 5. When each test module 30 completes a predetermined test procedure for the chips on the electrical connectors 2 connected thereto, each test module 30 will correspondingly generate test result data C2 and test parameter data C3. The processing unit 5 can receive the test result data C2 and the test parameter data C3 transmitted by each test module 30, and the processing unit 5 can control the wireless transmission unit 7 to transmit the test result data C2 and the plurality of test parameter data C3 to an external electronic device in a wireless manner, where the external electronic device is, for example, a central control device E1, and then the central control device E1 can write each test result data C2 and the test parameter data C3 into a corresponding memory through a read-write device.

Fig. 28 shows a schematic flow chart of a twelfth embodiment of the chip testing method disclosed in the present invention. The biggest difference between this embodiment and the flow chart shown in fig. 16 is: after the classifying step S7, the method may include:

a test result writing step S8: and storing the test result data after each memory completes the preset test program and the corresponding test parameter data in each memory.

Specifically, when the memory carried by the chip testing apparatus 1 completes all tests (for example, burn-in test and high temperature test, or burn-in test, high temperature test, low temperature test, and normal temperature test) according to the requirements, the central control apparatus E1 may first control the sorting device E5 to sort each memory according to the test result of each memory. Then, the central control device E1 controls the related read/write device to perform the related read/write operation on the memories classified into the good area a1, so as to store the corresponding test result data C2 and the corresponding test parameter data C3 in each memory. That is, only the memory classified as good is stored with the test result data C2 and the test parameter data C3.

Fig. 29 is a schematic flow chart showing a thirteenth embodiment of the chip testing method disclosed in the present invention. The biggest difference between this embodiment and the flow chart shown in fig. 16 is: before the classifying step S7, the method may include:

a test result is written in step S7A: and storing the memory passing through each preset test program, the corresponding test result data and the corresponding test parameter data in the corresponding memory.

Specifically, when the memory carried by the chip testing device 1 is tested according to the requirements and passes all tests (such as a burn-in test and a high-temperature test, or a burn-in test, a high-temperature test, a low-temperature test, and a normal-temperature test), the chip testing device 1 writes the test result corresponding to the memory and the related test parameter data into the memory; on the contrary, if the memory fails at least one of the tests, the chip testing apparatus 1 will not write any test-related data corresponding to the memory into the memory. Thus, in the classifying step S7, the classifying device may rapidly determine whether the memory passes the test by determining whether any of the test-related data is written in the memory, and if the classifying device determines that the data is not written in the memory, the classifying device may directly classify the memory into the defective area.

Referring to fig. 30, in practical applications, the central control device E1 of the chip testing system E may include a Master control device E11(Master control device), a chip testing control device E12, an environmental status control device E13, and a transfer control device E14. The number of the chip test control apparatus E12, the environmental condition control apparatus E13, and the transfer control apparatus E14 may be varied according to the needs, and is not limited to a single one.

In the embodiment where the chip testing system E has a single chip testing control device E12, the chip testing control device E12 may be used to control the operations of all the chip testing devices 1, the pre-testing equipment E6 and the final testing equipment, so as to perform various testing operations on a plurality of chips. In short, the chip test control device E12 may be any device for controlling a chip to be tested. In an embodiment where the chip testing system E includes a plurality of chip testing control devices E12, each chip testing control device E12 may, for example, correspondingly control at least one chip testing device 1; the different chip test control apparatus E12 may perform different test operations according to the chip test apparatus 1 connected thereto.

In the embodiment where the chip testing system E has a single environmental status control apparatus E13, the environmental status control apparatus E13 may be used to control the operation of any environmental control equipment E3, so as to control the operation of any environmental control equipment E3, for example, the environmental status control apparatus E13 may control the operation of the temperature adjusting apparatus E34, the air extracting apparatus E37, the lifting apparatus E38, and the position limiting apparatus E39 of any environmental control equipment E3. In an embodiment where the chip testing system E includes a plurality of environmental status controllers E13, each environmental status controller E13 may, for example, correspondingly control at least one environmental control device E3; the different environmental status control device E13 can be operated completely differently according to the environmental control equipment E3 connected to it. It is worth mentioning that each environmental condition control device E13 can control the actions of each component of any environmental control equipment E3, such as the actions of each sensor of each environmental control equipment E3 and the sensing result of each sensor.

In the embodiment where the chip test system E has a single transfer control device E14, the transfer control device E14 may be configured to control the chip mounter E2, the position detection apparatus E8, the transfer apparatus E4, and the sorting apparatus E5. In short, the transfer controller E14 may be any device for controlling the chip testing apparatus 1 or the chip to be transferred. Of course, in the embodiment where the chip testing system E includes a plurality of transfer control devices E14, the plurality of transfer control devices E14 may be classified according to the requirements and correspondingly control different devices, for example, one of the transfer control devices E14 may be a device dedicated to controlling the transfer chip testing apparatus 1, and one of the transfer control devices E14 may be a device dedicated to controlling the transfer of chips.

The master control device E11 is connected to the chip test control device E12, the environmental status control device E13 and the transfer control device E14, and the master control device E11 may be used to control the cooperation among the chip test control device E12, the environmental status control device E13 and the transfer control device E14. In a specific application, the host E11, the chip test control device E12, the environmental status control device E13 and the transfer control device E14 may be at least one computer device, server, etc., but not limited thereto.

Through the design that the chip testing system E includes the main control device E11, the chip testing control device E12, the environmental state control device E13 and the transfer control device E14, the chip testing system E is relatively easy to perform related control integration in the production and manufacturing process, and the problems can be easily and rapidly found out during the subsequent operation and maintenance of the chip testing system E.

In particular, in any of the above embodiments, the chip testing apparatus 1 is not limited to be powered during the testing step, the chip testing apparatus 1 may be powered at any time point after being disposed in the accommodating chamber E311 and between the testing steps, and the chip testing apparatus 1 is not limited to be powered during the testing step. In other words, in practical applications, the chip testing apparatus 1 may be powered immediately when being installed in the accommodating chamber E311, or the chip testing apparatus 1 may be powered only when performing the testing procedure.

In addition, it should be emphasized that in any of the above embodiments in which the power supply member includes a plurality of connection terminals, the connection terminals and the housing chamber terminals can be directly replaced by the receiving antenna and the transmitting antenna. Of course, since the receiving antenna and the transmitting antenna are wirelessly used for power transmission, the related process steps of contacting or separating the connecting terminal and the receiving chamber terminal in some embodiments can be omitted when the connecting terminal and the receiving chamber terminal are directly replaced by the receiving antenna and the transmitting antenna.

In summary, the chip testing system, the chip testing apparatus and the chip testing method applied to the chip testing system disclosed by the invention have the advantages of cost and better testing efficiency compared with the existing chip testing equipment. In addition, the chip testing system disclosed by the invention has the advantages that the plurality of chips are arranged on the chip testing device, then the chip testing device is moved to carry out related testing operation in different temperature environments, therefore, the chips are arranged on the same chip testing device in the testing process in different temperature environments, the chips cannot be repeatedly disassembled and assembled in the whole testing process, and the chips are not easy to be damaged unexpectedly. In contrast, in the conventional memory detection device, the memory is repeatedly detached and mounted on the electrical connection socket in different temperature environments, so that the memory is easily damaged unexpectedly after repeated detachment and mounting.

The disclosure is only a preferred embodiment of the invention and is not intended to limit the scope of the invention, so that all equivalent technical changes made by using the contents of the specification and the drawings are included in the scope of the invention.

Claims

1. A chip testing device, wherein the chip testing device is used for bearing a plurality of chips, and the chip testing device can be carried by a carrying device and transferred among a plurality of workstations, the chip testing device comprises:

the circuit board, its opposite both sides define a first side and a second side separately;

the electric connection seats are fixedly arranged on the first side surface of the circuit board and are used for bearing a chip; the plurality of electric connection seats are divided into a plurality of electric connection seat groups, and each electric connection seat group comprises at least one electric connection seat;

the control unit is arranged on the second side surface of the circuit board and comprises a plurality of test modules, the test modules are connected with the electric connecting seat groups, and each test module is connected with all the electric connecting seats in the corresponding electric connecting seat group;

at least one power supply component connected with the circuit board;

the chip testing device is connected with an external power supply device through the power supply component so as to obtain the power required by the operation of each testing module;

when the chip testing device obtains power from the external power supply equipment through the power supply component, each testing module can perform a preset testing program on the chips on the electric connection seats connected with the testing module.

2. The device for testing chips of claim 1, wherein the chip is a memory, and the predetermined test procedure comprises: at least one of a read test, a write test, and an electrical test.

3. The chip test apparatus according to claim 2, wherein each of the test modules comprises: the device comprises a pattern generator, a component power supply module and a driving circuit.

4. The apparatus according to claim 2, wherein the power supply means comprises a plurality of connection terminals disposed on the circuit board, each of the connection terminals being configured to be connected to a plurality of receiving chamber terminals of at least one of the workstations; when the plurality of connecting terminals and the plurality of accommodating chamber terminals are connected with each other, the external power supply device can provide power for the chip testing device.

5. The apparatus according to claim 2, wherein the power supply member is a receiving antenna, the receiving antenna is configured to couple with a transmitting antenna of the external power supply device, and the chip testing apparatus is configured to wirelessly receive the power transmitted by the external power supply device through the receiving antenna.

6. The chip testing device as claimed in claim 2, further comprising a plurality of first data transmission terminals disposed on the circuit board for transmitting data with a plurality of second data transmission terminals of at least one of the workstations.

7. The device for chip testing as claimed in claim 2, further comprising a plurality of first data transmission antennas for wirelessly transmitting data with a plurality of second data transmission antennas of at least one of the workstations.

8. The device for testing chips as claimed in claim 2, wherein each of the chips is a memory, and after each of the test modules completes the predetermined test procedure for the chips on the plurality of electrical connectors connected thereto, the test module writes test result data and test parameter data of each of the chips into the chip, so that the test result data and the test parameter data are stored in each of the chips.

9. The device for testing chips of claim 2, wherein each of the test modules comprises at least one storage unit and a processing unit; after each testing module completes the predetermined testing program for the chips on the plurality of electrical connectors connected with the testing module, the processing unit stores the testing result data and the testing parameter data of each chip in the storage unit.

10. The apparatus of claim 9, wherein after each of the test modules completes the predetermined test procedure on the chips on the electrical connectors connected thereto, each of the processing units can selectively write test result data and test parameter data thereof into the chip according to the test result data of each of the chips.

11. The device for testing chips of claim 2, further comprising a processing unit and a wireless transmission unit, wherein the processing unit is connected to the plurality of test modules, and the wireless transmission unit is connected to the processing unit; when each test module finishes the preset test program for the chips on the plurality of electric connection seats connected with the test module, each test module correspondingly generates test result data and test parameter data; the processing unit can receive the test result data and the test parameter data transmitted by each test module, and the processing unit can control the wireless transmission unit to wirelessly transmit the test result data and the test parameter data transmitted by the plurality of test modules to an external electronic device.

12. The chip testing apparatus of claim 1, wherein each electrical connector comprises:

the base body is provided with a top wall and an annular side wall, the top wall is provided with an opening, one end of the annular side wall is connected with the periphery of the top wall, the other end of the annular side wall is arranged on the circuit board, and the top wall, the annular side wall and the circuit board together form a containing groove; two opposite side surfaces of the top wall are defined as an outer side surface and an inner side surface, and the inner side surface is positioned in the accommodating groove;

the supporting structure is arranged on the circuit board and is positioned in the accommodating groove;

the lifting structure is arranged in the accommodating groove and is provided with a base part and a bearing part, the base part is positioned in the accommodating groove, the base part extends towards one side to form the bearing part, and at least one part of the bearing part is positioned in the opening; the bearing part extends towards one side far away from the base part to form a plurality of limiting parts, at least one part of the limiting parts penetrates through the opening, a chip containing groove is formed by the limiting parts and the bearing part together, and the chip containing groove is used for containing the chip; the lifting structure is also provided with a plurality of connecting holes which penetrate through the base part and the bearing part;

at least one elastic component, which is arranged in the containing groove, one end of each elastic component is fixed on the lifting structure, the other end of each elastic component is fixed on the supporting structure, the elastic restoring force generated by the compression of the elastic components enables the base part to be abutted against the inner side surface of the top wall, and a gap is formed between the lifting structure and the supporting structure;

one end of each probe assembly is fixedly arranged on the supporting structure and is used for being connected with the circuit board, and the other end of each probe assembly penetrates through the connecting holes;

when the chip accommodating groove is provided with the chip and the limiting part is not pressed by a pressing device, the probe assemblies positioned in the connecting holes are not connected with the contact parts of the chip;

when the chip accommodating groove is provided with the chip, and the limiting part is pressed by the pressing device and is retracted towards the base body, the probe assemblies abut against the contact parts, and the probe assemblies and the chip are connected with each other.

13. The apparatus for testing chips as defined in claim 12, wherein when the chip receiving slot is provided with the chip and the position-limiting portion is pressed by the pressing device to retract into the base body, the plurality of probe assemblies penetrate through the plurality of connecting holes.

14. The apparatus of claim 12, wherein the elevating structure is capable of being fully retracted within the base body when under compression.

15. The apparatus for testing chips as defined in claim 1, wherein any one of said electrical connectors in each of said electrical connector groups is not connected to any of said electrical connectors in other of said electrical connector groups.