TWI700499B - Chip testing system - Google Patents

Abstract

The invention discloses a chip testing system comprising: a central control device, a chip mounting device, a plurality of environmental control devices, a sorting device and a transfer device. The central control unit can control the chip mounting device to mount a plurality of chips to the chip test device. Each of the environmental control devices includes a plurality of chambers that are independent of each other, and temperature adjusting devices are disposed in each of the chambers. The central control unit can control the transfer device and place the chip test device in one of the chambers of the environmental control device. When the chip testing device carries the chip and is disposed in the chamber, the central control device can control the temperature adjusting device to operate, so as that the plurality of chips can be tested by the chip testing device in a predetermined testing procedure.

Description

Wafer test system

The invention relates to a chip testing system, in particular to a chip testing system suitable for memory testing.

Generally speaking, the memory must pass a high temperature test, a burn-in test, or a high temperature test, a burn-in test, and a low temperature test before leaving the factory. With existing memory testing equipment, the memory must be repeatedly plugged in and out of different electrical connectors during high temperature test, burn-in test or low temperature test. For this reason, it is easy to cause damage to the memory pins and repeatedly Plugging and unplugging also wastes a lot of time and causes the problem of low test efficiency.

The embodiment of the present invention is to provide a chip test system, which is used to improve the existing memory device. When the memory is tested in different temperature environments, the chip must be repeatedly disassembled and assembled, resulting in low test efficiency and easy to cause The pins of the memory are damaged.

The embodiment of the invention discloses a wafer testing system for testing multiple wafers. The wafer testing system includes: a central control device, a wafer mounting device, at least one environmental control device, a transfer device and a sorting device. The chip mounting equipment can be controlled by a central control device to mount multiple chips on multiple electrical connection seats of a wafer testing device. The environmental control equipment is connected to the central control device, and each environmental control device includes: an equipment body and a plurality of temperature adjustment devices. The main body of the equipment contains multiple accommodating chambers. The main body of the equipment is connected to a power supply device. Each accommodating chamber can accommodate a wafer test device. The main body of the equipment has multiple power supply components. Electricity is supplied to the wafer testing equipment installed in each containing chamber. Each accommodating chamber is provided with a temperature adjustment device; each temperature adjustment device can be controlled by the central control device, so that the surrounding temperature of the wafer on the multiple electrical connection seats of the wafer test device in the corresponding accommodating chamber reaches a level Scheduled temperature. The transfer equipment can be controlled by the central control device to carry the wafer test device, so that the wafer test device can be moved between the wafer mounting equipment, the multiple accommodation chambers of the multiple environmental control equipment and the sorting equipment; among them, when the transfer equipment will When the wafer testing device carrying multiple wafers is transferred from the wafer mounting equipment to one of the accommodating chambers of one of the environmental control equipment, the power supply device can provide power to the wafer testing device through the power supply member of the equipment body; When the device is powered and the temperature adjustment device makes the surrounding temperature of the multiple wafers on the wafer test device reach a predetermined temperature, the central control device can control the wafer test device to perform a predetermined test procedure on the multiple wafers it carries. The sorting equipment can be controlled by the central control device, and the multiple wafers can be unloaded from the multiple electrical connectors of the wafer testing device, and the sorting equipment can place each wafer in a place based on the test results of each wafer after the predetermined test procedure is completed. Good product area or a defective product area. Wherein, when the wafer testing device completes a predetermined test procedure for the multiple wafers it carries, the central control device will control the transfer equipment to transfer the wafer testing device from the containing chamber to the sorting equipment.

In summary, the wafer testing system disclosed in the embodiments of the present invention can use the wafer mounting equipment to mount multiple wafers on the wafer testing device, and then use the transfer equipment to transfer the wafer testing device and the wafers it carries to In the accommodating chamber, the temperature adjustment device is used to make the surrounding temperature of the wafer carried by the wafer testing device installed in the accommodating chamber reach a predetermined temperature; then, after power is supplied to the wafer testing device, the wafer testing device will The multiple wafers carried are tested; finally, after the wafer testing device has completed the testing of the multiple wafers carried by it, the transfer equipment and the sorting equipment are used to classify the wafers according to the results of the testing. Therefore, the chip testing system of the present invention can prevent the chip from being repeatedly inserted and removed during the testing process.

Please refer to Figure 1, Figure 2 and Figure 3 together. Figure 1 is a schematic diagram of the wafer testing system disclosed in the present invention, Figure 2 is a block schematic diagram of the wafer testing system disclosed in the present invention, and Figure 3 is a wafer testing device disclosed in the present invention Schematic diagram. The wafer testing system E disclosed in the present invention is used to test multiple wafers C. The wafer testing system E includes: a central control device E1, a wafer mounting device E2, at least one wafer testing device 1, a plurality of environmental control devices E3, a transfer device E4, and a sorting device E5.

The central control device E1 is connected to the chip installation equipment E2, multiple environmental control equipment E3, transfer equipment E4, and classification equipment E5, and the central control device E1 can control the actions of each device; the central control device E1 is, for example, a server, various computers Equipment, etc., are not restricted here. The chip mounting equipment E2 may include a robotic arm (not shown). The robotic arm can be controlled by the central control device E1 to take out multiple chips C on the tray one by one and place them one by one on the chip for testing. The multiple electrical connection bases 2 of the device 1 are installed.

As shown in FIGS. 2, 3 and 4, FIG. 4 shows a block diagram of the wafer testing apparatus 1. The wafer testing device 1 is used to carry multiple wafers C, and the wafer testing device 1 can be carried by the transfer equipment E4 to multiple workstations (such as wafer mounting equipment E2, multiple environmental control equipment E3, transfer equipment E4, and sorting equipment) E5) transfer between.

The wafer testing device 1 includes: a circuit board 10, a plurality of electrical connection seats 2, a control unit 3 and at least one power supply component 4. The opposite sides of the circuit board 10 are defined as a first side surface 101 and a second side surface 102 respectively. A plurality of electrical connection seats 2 are fixedly arranged on the first side surface 101 of the circuit board 10, and each electrical connection seat 2 is used to carry one chip C. Regarding the form of the electrical connection base 2 can be changed according to different chips C, it is not limited here.

In practical applications, the multiple electrical connection bases 2 may be divided into multiple electrical connection base groups, and each electrical connection base group includes at least one electrical connection base 2. The control unit 3 is disposed on the second side surface 102 of the circuit board 10, and the control unit 3 includes a plurality of test modules 30, and each test module 30 is correspondingly connected to an electrical connector group.

Specifically, in FIG. 3 of this embodiment, 96 electrical connection sockets 2 are provided on the circuit board 10, which can be divided into 16 groups of electrical connection sockets, and each electrical connection socket group includes 6 electrical connection sockets. The connection base 2 and the six electrical connection bases 2 in each electrical connection base group are connected to the same test module 30, that is, the circuit board 10 in FIG. 3 may be provided with 16 test modules 30. Of course, the number of electrical connection sockets 2 provided on the circuit board 10 and how many electrical connection socket groups are divided into corresponding groups can be changed according to requirements.

When each test module 30 is powered on, a predetermined test procedure can be performed on a plurality of chips C on the plurality of electrical connection sockets 2 to which it is connected. For example, the chip C may be various types of memory (for example, NAND Flash, etc.), and each test module 30 can perform at least one of a read test, a write test, and an electrical test on each memory. In the embodiment in which each test module 30 is used to test the memory, each test module 30 may include a pattern generator (PG), a parameter measurement unit (Parametric Measurement Unit, PMU), and a component power supply module. Group (Device Power Supplies, DPS) and drive circuit (Driver).

Through the design that the multiple electrical connection sockets 2 provided on the circuit board 10 are respectively connected to multiple different test modules 30, the test module 30 and the multiple chips C on the electrical connection socket 2 connected to each other The signal transmission between them can be faster and less prone to attenuation. More specifically, if the circuit board 10 provided with 96 electrical connection sockets 2 is connected to only one signal input source, the signal from the signal input source is transmitted from one side of the circuit board 10 to the other side of the circuit board 10. At this time, the signal will obviously attenuate, which may lead to inaccurate chip test results.

It is worth mentioning that the multiple electrical connection sockets 2 of different electrical connection socket groups may not be connected to each other. When the chip testing device 1 fails, the relevant maintenance personnel can test each electrical connection socket group one by one. Group, and quickly find the damaged electrical connection base 2, and the relevant maintenance personnel can only replace the damaged electrical connection base 2, the components of the electrical connection base 2, the electrical connection base 2 or the test module 30 in the same group , And relevant personnel do not need to replace all the electrical connection seats 2 or all the test modules 30 of the entire circuit board 10.

As shown in FIG. 3, in practical applications, the wafer testing device 1 may also include a housing 31 fixedly disposed on the second side 102 of the circuit board 10, and the housing 31 correspondingly covers a plurality of The test module 30 protects a plurality of test modules 30. In a specific implementation, the casing 31 may also be provided with related heat dissipation devices, such as fans, heat dissipation fins, etc., according to requirements. In FIG. 3 of this embodiment, the wafer testing device 1 only includes a single housing 31, and the housing 31 corresponds to covering a plurality of test modules 30, but the number of housings 31 of the wafer testing device 1 It is not limited to a single one. In different applications, the chip testing device 1 may also include multiple housings 31, and each housing 31 may be covered with a single test module 30 or two or three An equal number of test modules 30.

The power supply member 4 is disposed on the circuit board 10, the power supply member 4 is connected to the circuit board 10, and the power supply member 4 can be connected to a plurality of test modules 30 through the circuit board 10. The power supply member 4 can be, for example, a board-to-board connector, and its form can be, for example, a Pogo pin or a reed, but it is not limited to this. In FIG. 3 of the present embodiment, the power supply member 4 includes a plurality of connection terminals, and the power supply member 4 is provided on the first side 101 of the circuit board 10 as an example, but the form and number of the power supply member 4 and the power supply member 4 The location on the circuit board, etc. are not limited to those shown in the figure.

The power supply component 4 is used to connect with an external power supply device, and the external power supply device can supply power to each test module 30 through the power supply component 4. The external power supply device refers to a power supply device independent of the wafer test apparatus 1. The external power supply device can It is any device that can provide electricity, so there is no restriction here. In other words, when the wafer testing apparatus 1 is not connected to an external power supply device through the power supply member 4, each test module 30 basically has no power to perform a predetermined test procedure on the multiple wafers C connected to it. Of course, in different embodiments, the chip testing device 1 may also be provided with at least one battery, the battery is connected to a plurality of test modules 30, and the battery can supply power to the plurality of test modules 30.

In another embodiment, the power supply member 4 may include a receiving antenna, and the power supply member 4 can receive power in a wireless manner to provide power to each test module 30. In the embodiment where the power supply member 4 is a receiving antenna, the chip testing device 1 may include a rechargeable battery module, and the power supply member 4 is connected to the rechargeable battery module, and the power supply member 4 can receive power in a wireless manner, so as to The rechargeable battery module is charged; and, in a specific implementation, the power required for each test module 30 to test the chip C carried by it can come from the rechargeable battery module and the external power supply device through the receiving antenna (Power supply member 4) Provided. In the embodiment where the power supply member 4 is a receiving antenna, the location of the power supply member 4 may not be exposed outside the chip testing device 1 but embedded in the circuit board 10 or hidden in the chip testing device 1. In addition, the number of power supply members 4 included in each wafer testing device 1 may vary according to requirements, and is not limited to a single one, and may also be two or more.

As shown in FIGS. 3, 4, and 10, it is particularly noted that the wafer testing device 1 may also include a plurality of first data transmission terminals 8, and the accommodating chamber E311 may be correspondingly provided with a plurality of second data Transmission terminal E32. The plurality of first data transmission terminals 8 and the plurality of second data transmission terminals E32 can contact each other and transmit information to each other. In practical applications, each of the first data transmission terminals 8 and each of the second data transmission terminals E32 may have a Pogo pin or a reed structure, but is not limited to this. Regarding the number of the first data transmission terminal 8 and the second data transmission terminal E32 and their installation positions, they can be changed according to requirements, and are not limited here.

In a different embodiment, the wafer testing device 1 may also include at least one first data transmission antenna (not shown), and at least one second data transmission antenna (not shown) may be correspondingly provided in the accommodation chamber E311. Show). The first data transmission antenna can interact with the second data transmission antenna to transmit information to each other in a wireless manner. In practical applications, the location of the first data transmission antenna is not limited to the storage room E311, as long as the first data transmission antenna can transmit information to the second data transmission antenna installed in the storage room E311, the first data The transmission antenna can be arranged at any position of the environmental control equipment E3.

Please refer to FIG. 5, FIG. 6, FIG. 7 and FIG. 8. FIG. 5 is a schematic diagram of each electrical connection base 2 of the chip testing device 1 disclosed in the present invention, and FIG. 6 is a cross-sectional exploded schematic view of the electrical connection base 2. 7 shows a schematic cross-sectional view of the electrical connection base 2 without the chip C, and FIG. 8 shows a schematic cross-sectional view of the electrical connection base 2 provided with the chip C.

Each electrical connection base 2 includes: a plurality of probe assemblies 20, a connection base body 21, a lifting structure 22, a supporting structure 23 and a plurality of elastic components 24. Each probe assembly 20 includes a needle body 201 and a spring 202. One end of the needle body 201 is used to connect with the electrical connection portion C1 of the chip C (as shown in FIG. 8 ). The spring 202 is sleeved on the needle body 201, and when one end of the needle body 201 is pressed, the spring 202 will be compressed and correspondingly generate elastic restoring force, whereby when the needle body 201 is no longer compressed, the needle body 201 will be The elastic restoring force returns to the uncompressed position.

The connecting seat body 21 has a top wall 211 and a ring side wall 212. The top wall 211 has an opening 21A. One side of the ring side wall 212 is connected to the periphery of the top wall 211, and the other side of the ring side wall 212 is fixedly arranged on the circuit board 10. , The top wall 211, the ring side wall 212 and the circuit board 10 jointly form a receiving groove 21B. The two opposite sides of the top wall 211 are defined as an outer side 2111 and an inner side 2112 (as shown in FIG. 7). In practical applications, the top wall 211 and the ring side wall 212 may be integrally formed, and the connecting base body 21 may also have a plurality of lock holes 21C (as shown in FIG. 5), and the plurality of lock holes 21C may be combined with a plurality of locking members. (For example, screws) cooperate with each other to fix the connector body 21 to the circuit board 10.

The lifting structure 22 includes a base 221 and a supporting portion 222. The base 221 is completely disposed in the accommodating groove 21B, and the base 221 extends to one side to form a supporting portion 222, and a portion of the supporting portion 222 can penetrate through the opening 21A. The bearing portion 222 has four limiting portions 223 extending away from the base 221. The four limiting portions 223 may be located at the four corners of the bearing portion 222, and the four limiting portions 223 and the bearing portion 222 jointly forms a wafer receiving groove 22B, the wafer receiving groove 22B is used to provide the setting of the chip C, and the four limiting portions 223 are used to engage the chip C with each other. The lifting structure 22 also has a plurality of connecting holes 22A (as shown in FIG. 6 ), and each connecting hole 22A is provided through the base 221 and the carrying portion 222.

A part of the plurality of probe assemblies 20 is fixedly arranged in the supporting structure 23, and the plurality of probe assemblies 20 are fixedly arranged at one end of the supporting structure 23 for connecting with the circuit board 10; the other of the plurality of probe assemblies 20 One end is located in the plurality of connecting holes 22A, and one end of the probe assembly 20 located in the plurality of connecting holes 22A is used to connect with the electrical connection portion C1 of the chip C.

In practical applications, the supporting structure 23 may include a base structure 231 and an auxiliary structure 232. The base structure 231 is disposed in the accommodating groove 21B, and the base structure 231 and the main body 21 are fixed to each other (for example, a plurality of screws are used to fix the main body 21 to each other). The base structure 231 has a plurality of perforations, and one end of the plurality of probe assemblies 20 is fixedly disposed in the plurality of perforations of the base structure 231. The auxiliary structure 232 is disposed in the accommodating groove 21B, and the auxiliary structure 232 is located between the base structure 231 and the top wall 211, and the auxiliary structure 232 and the base structure 231 are fixed to each other (for example, using screws to lock each other). The auxiliary structure 232 has a plurality of support holes arranged at intervals, and the plurality of support holes communicate with the plurality of perforations of the base structure 231, and the plurality of support holes are arranged corresponding to the plurality of connecting holes 22A, and the plurality of connecting holes 22A. The multiple support holes and the multiple perforations will jointly form multiple probe channels, and the multiple probe assemblies 20 are correspondingly arranged in the multiple probe channels.

As shown in FIG. 7, the supporting structure 23 is disposed in the accommodating groove 21B, and the elastic component 24 is disposed between the supporting structure 23 and the lifting structure 22. The elastic component 24 can make the base 221 of the lifting structure 22 abut against the inner side surface 2112 of the top wall 211, and a gap S is formed between the base 221 and the supporting structure 23 correspondingly.

In practical applications, when the electrical connection base 2 is fixed on the circuit board 10 and the limiting portion 223 of the electrical connection base 2 is not pressed by external force, the four elastic components 24 located between the lifting structure 22 and the supporting structure 23 It may be slightly compressed, and the elastic restoring force generated by the compression of the elastic component 24 will make the lifting structure 22 stably abut against the inner surface 2112 of the top wall 211.

As shown in FIG. 8, when the chip C is fixedly arranged in the chip receiving groove 22B and the lifting structure 22 is not pressed, the plurality of electrical connection portions C1 of the chip C are correspondingly accommodated in the plurality of connection holes 22A, and Each probe assembly 20 is not connected to the plurality of electrical connection parts C1 (for example, they are not in contact with each other). When the lifting structure 22 is pressed, at least a part of the lifting structure 22 will retract in the connecting base body 21, that is, the lifting structure 22 will move in the direction of the circuit board 10 relative to the supporting structure 23, and the multiple probe assemblies 20 connects the plurality of electrical connection portions C1 corresponding to the wafer C.

Please refer to FIG. 3, FIG. 9 and FIG. 10 together. FIG. 9 is a schematic diagram of the environmental control device E3 disclosed in the present invention. Multiple environmental control devices E3 are connected to the central control device E1, and the central control device E1 can control any environmental control device E3 to operate independently. Each environmental control device E3 is used to make a plurality of wafers C set on the wafer testing device 1 perform a predetermined test procedure in an environment of a predetermined temperature (for example, a predetermined high temperature or a predetermined low temperature).

Each environmental control device E3 includes: an equipment body E31, a plurality of accommodation chamber terminals E33, and a plurality of temperature adjusting devices E34. The equipment body E31 includes a plurality of accommodation chambers E311. The accommodating chamber E311 referred to here is mainly used for accommodating the wafer testing device 1, and the plurality of accommodating chambers E311 included in the environmental control equipment E3 may or may not be in communication with each other, which is not limited here. . The equipment body E31 is connected to a power supply device (that is, the external power supply device independent of the wafer test apparatus 1 described in the foregoing description). The equipment body E31 may include a plurality of power supply components, the power supply components of the equipment body E31 are electrically connected to the power supply equipment, and the power supply equipment can provide power to each accommodation chamber E311 through the multiple power supply components of the equipment body E31的wafer testing device1.

It is worth mentioning that, in an embodiment where the multiple accommodating chambers E311 included in the environmental control equipment E3 are independent of each other and not connected to each other, each accommodating chamber E311 may be provided with a movable door, and the environmental control equipment E3 It can be connected to a suction device. When the wafer testing device 1 is installed in the accommodating chamber E311, the central control device E1 can control the action of the corresponding movable door so that the accommodating chamber E311 becomes a closed space. Then, the central control device E1 can control the action of the pumping equipment, In order to make the accommodating chamber E311 appear in a state similar to a vacuum, the temperature in the accommodating chamber E311 will not be easily affected by the external environment.

In the embodiment where the power supply member 4 of the wafer testing device 1 includes multiple connection terminals, the power supply member of the equipment body E31 may correspondingly include a plurality of receiving chamber terminals E33, and each receiving chamber E311 may be correspondingly provided There are a plurality of accommodating chamber terminals E33, and the plurality of accommodating chamber terminals E33 are used to connect with a plurality of connection terminals of the wafer testing device 1. Regarding the location of the accommodating chamber terminal E33, it can be designed based on the location of the wafer testing device 1 in the accommodating chamber E311 and the location of the multiple connection terminals of the power supply member 4, which is not limited here. In the embodiment where the power supply member 4 of the wafer testing device 1 is a receiving antenna, each containing chamber E311 may be correspondingly provided with a transmitting antenna for wireless charging, and the transmitting antenna is connected to an external power supply device, and when the wafer testing device 1 is set When in a predetermined position in the accommodating chamber E311, the transmitting antenna in the accommodating chamber E311 can be coupled with the receiving antenna (power supply member 4) of the wafer testing device 1 and the external power supply device can provide power to each test module 30.

Each temperature adjustment device E34 is connected to the central control device E1, and each temperature adjustment device E34 can be controlled by the central control device E1, so that the wafers C on the multiple electrical connection seats 2 of the wafer testing device 1 in the corresponding housing chamber E311 The ambient temperature reaches the predetermined temperature.

In one of the actual examples, the plurality of temperature adjustment devices E34 can be divided into a plurality of heating devices E34A and a plurality of refrigeration devices E34B. A plurality of heating devices E34A are arranged on the equipment body E31, and a plurality of refrigeration devices E34B are arranged on the equipment body E31; the temperature in each accommodating chamber E311 can be changed by one of the heating devices E34A or one of the cooling devices E34B to reach a predetermined value The low temperature or the predetermined high temperature.

Each heating device E34A may include a high-temperature contact structure E34A1, and the high-temperature contact structure E34A1 is used to contact a side surface of a plurality of wafers C provided on the wafer testing device 1. Each heating device E34A is connected to the central control device E1, and the central control device E1 can control each heating device E34A to operate independently, so that the temperature of the high temperature contact structure E34A1 of each heating device E34A is raised to a predetermined high temperature. The material of the high-temperature contact structure E34A1 may be determined according to a predetermined high-temperature temperature, and the side of the high-temperature contact structure E34A1 for contacting the plurality of chips C may be flat.

In specific applications, each high-temperature contact structure E34A1 may contain various electric heaters (such as heating coils), or the high-temperature contact structure E34A1 may also contain multiple flow channels, and each flow channel provides high-temperature fluid. by. Of course, it is also possible to arrange an electric heater or a related heater with multiple flow channels on one side of the high temperature contact structure E34A1.

Each refrigeration device E34B may include a low-temperature contact structure E34B1, and the low-temperature contact structure E34B1 is used to contact one side of a plurality of wafers C provided on the wafer testing device 1. Each refrigeration device E34B is connected to the central control device E1, and the central control device E1 can control each refrigeration device E34B to operate independently, so that the temperature of the low temperature contact structure E34B1 of each refrigeration device E34B is reduced to a predetermined low temperature. Wherein, the material of the low-temperature contact structure E34B1 may be determined according to a predetermined low-temperature temperature, and the side of the low-temperature contact structure E34B1 for contacting the plurality of chips C may be flat. In specific applications, each low-temperature contact structure E34B1 may contain multiple flow channels, and each flow channel provides a low-temperature fluid to pass through, or it may also be related components with multiple flow channels arranged in the low-temperature contact structure E34B1 Side.

In the above embodiment, each heating device E34A includes a high-temperature contact structure E34A1, each refrigeration device E34B includes a low-temperature contact structure E34B1, and the heating device E34A and the refrigeration device E34B are respectively through the high-temperature contact structure E34A1 and the low-temperature contact structure. The structure E34B1 is used to contact one side surface of a plurality of wafers C to directly transfer or dissipate heat to each wafer C, so that the temperature of the plurality of wafers C reaches a predetermined temperature. However, in different applications, each heating device E34A and each cooling device E34B can also make the surrounding temperature of the multiple wafers C on the wafer testing device 1 reach a predetermined temperature in a non-contact manner. For example, each The heating device E34A or the cooling device E34B can directly raise or lower the temperature in the corresponding accommodating chamber E311.

In the above description, the heating device E34A or the refrigerating device E34B is provided in each accommodating chamber E311 as an example, but the temperature adjusting device E34 provided in each accommodating chamber E311 is not limited to only having a single heating function, or Only has a single cold function. In different embodiments, each temperature adjusting device E34 may include a heater E341 and a uniform cooler E342 at the same time, and each temperature adjusting device E34 may also include a contact structure E343 according to requirements. The heater E341 and the refrigerator E342 can be controlled by the central control device E1, so that the temperature of the contact structure E343 reaches a predetermined high temperature or a predetermined low temperature. The contact structure E343 is used for contacting the plurality of wafers C provided on the wafer testing device 1, thereby making the temperature of the plurality of wafers C reach a predetermined temperature in a direct contact manner. Of course, in different applications, each temperature adjusting device E34 may not have the contact structure E343, and each temperature adjusting device E34 may pass through the heater E341 or the refrigerator E342, so that the corresponding accommodating chamber E311, Reach a predetermined high temperature or a predetermined low temperature.

Please refer to FIG. 9, FIG. 10, FIG. 11, FIG. 12, FIG. 13 and FIG. 14, the temperature adjusting device E34 of each environmental control device E3 may be connected to a cover E35. A groove E351 is concavely formed on one side of the cover E35. The cover E35 has an accommodating opening E352, and the accommodating opening E352 is communicated with the groove E351. The cover E35 also has two suction holes E353. Each environmental control device E3 may include at least one exhaust device E37, and two exhaust holes E353 are used to connect with the exhaust device E37.

The temperature adjusting device E34 may for example include the aforementioned contact structures E34A1, E34B1, E343, and one side of the contact structures E34A1, E34B1, E343 may be flat, and the contact structures E34A1, E34B1, E343 may include at least first Channel E344, and the contact structures E34A1, E34B1, E343 correspondingly have a fluid inlet E345 and a fluid outlet E346, whereby high-temperature fluid or low-temperature fluid can enter the flow channel E344 through the fluid inlet E345, and then flow out from the fluid outlet E346 As a result, the high-temperature fluid or the low-temperature fluid continuously flows in the flow channel E344, so that the temperature of the contact structures E34A1, E34B1, and E343 can reach a predetermined temperature.

In practical applications, the cover E35 can also be fixedly provided with a cover E36. A accommodating space SP1 can be formed between the cover E36 and the temperature adjusting device E34, and the accommodating space SP1 can be filled with anything that can be blocked. Thermal energy transfer components.

Please refer to FIGS. 14 and 15. FIG. 14 shows a schematic diagram of the electrical connection base 2 of the wafer testing device 1 and the chip C disposed thereon in contact with the contact structures E34A1, E34B1, and E343 of the temperature adjusting device E34. FIG. 15 is Figure 14 is a partial enlarged schematic view. As shown in the figure, when the cover E35 abuts against one side of the circuit board 10, the cover E35, the contact structures E34A1, E34B1, E343, and the circuit board 10 will jointly form a closed space SP2, and a plurality of electrical connection seats 2 Will be correspondingly located in the closed space SP2; at the same time, the multiple connection terminals of the power supply member 4 may be correspondingly connected to the multiple accommodation chamber terminals E33.

As shown in Figures 8 and 15, the central control device E1 controls the operation of the air extraction device to extract the gas in the enclosed space SP2 through the air extraction hole E353 of the cover E35, so that the enclosed space SP2 appears close During the vacuum or vacuum state, the contact structures E34A1, E34B1, and E343 will press the lifting structure 22 of each electrical connection base 2, and each lifting structure 22 will move in a direction closer to the circuit board 10 relative to the connection base body 21 , And the plurality of probe assemblies 20 will correspond to the plurality of electrical connection parts C1 of the chip C, and the contact structures E34A1, E34B1, E343 will correspondingly abut against one side of the plurality of chips C; in other words, in the enclosed space SP2 In the process of the gas being drawn outward, the contact structures E34A1, E34B1, and E343 will press the lifting structure 22 of each electrical connection base 2, and the lifting structure 22 of the electrical connection base 2 will be converted from the state shown in FIG. 15 shown in the state.

In practical applications, the central control device E1 controls the air extraction equipment, and the time point at which the air in the enclosed space SP2 is extracted can be designed according to requirements. For example, the central control device E1 may control the operation of the air extraction device when the multiple connection terminals (as shown in FIG. 3) included in the power supply member 4 are connected to the receiving chamber terminal E33 (as shown in FIG. 10) , In order to extract the air in the enclosed space SP2; or, the central control device E1 can also be through at least one sensor (such as an optical sensor or a mechanical device) arranged in the containing chamber E311 (as shown in FIG. 9) Type pressure sensor, etc.) to determine whether the wafer testing device 1 has been set in the predetermined position in the accommodating chamber E311, and the central control device E1 uses the sensor to determine that the wafer testing device 1 is located in the predetermined position in the accommodating chamber E311. In the position, the air extraction device is controlled to act to extract the air in the enclosed space SP2.

As shown in Figures 10 and 15, when the exhaust device E37 draws out the gas in the enclosed space SP2, the contact structures E34A1, E34B1, and E343 correspondingly abut one side surface of the multiple chips C, and each electrical connection seat When the plurality of probe assemblies 20 of 2 are connected to the plurality of electrical connection parts C1 of the wafer C set on it, the central control device E1 will actuate the controllable temperature adjustment device E34 to make the contact structures E34A1, E34B1, and E343 reach When the temperature of the contact structures E34A1, E34B1, and E343 reaches a predetermined temperature, the central control device E1 can control the test module 30 connected to each electrical connector 2 to perform a predetermined test procedure on the chip C.

Through the mutual cooperation of the aforementioned cover E35 and the air extraction device E37, the force required for the contact structures E34A1, E34B1, and E343 to simultaneously press the lifting structures 22 of the multiple electrical connection seats 2 can be greatly reduced, that is, the lifting devices can be reduced E38 (detailed later) makes the multiple wafers C carried by the wafer testing device 1 abut the contact structures E34A1, E34B1, and E343 at the same time.

Please refer to FIG. 1 and FIG. 2 again. The transfer equipment E4 is arranged between the plurality of environmental control devices E3, and the transfer equipment E4 is used to carry the wafer test device 1. The transfer equipment E4 may include a robotic arm and a holding component, and the holding component is used to hold the wafer testing device 1. The central control device E1 is connected to the transfer equipment E4, and the central control device E1 can control the transfer equipment E4 to install the wafer testing device 1 carrying multiple wafers C in any accommodating room E311 of any environmental control equipment E3 (As shown in Figure 9). In contrast, the transfer equipment E4 can also be controlled by the central control device E1 to move the wafer testing device 1 arranged in any accommodating chamber E311 out of the accommodating chamber E311.

The sorting equipment E5 is connected to the central control device E1, and the sorting equipment E5 can be controlled by the central control device E1 to unload a plurality of wafers C from the multiple electrical connection seats 2 of the wafer testing device 1, and the sorting equipment E5 can be based on each After the chip C has passed the test result of the predetermined test procedure, each chip C is placed on a carrier plate in a good product area A1 or a carrier plate in a defective product area A2. The classification device E5 may include a robotic arm, for example. In the embodiment in which the sorting equipment E5 and the wafer mounting equipment E2 are arranged at adjacent positions, the wafer mounting equipment E2 and the sorting equipment E5 may share the same robotic arm. In practical applications, the good product area A1 can also be divided into multiple areas based on requirements, and the classification device E5 can set the chip C in the good product area A1 based on the test results of each chip C after passing a predetermined test procedure. For example, the different areas can be distinguished based on the operating performance of chip C.

As shown in FIG. 16, it is a schematic flowchart of the first embodiment of a wafer testing method disclosed in the present invention. The above-mentioned wafer testing system E may use the following wafer testing methods to perform predetermined testing procedures on multiple wafers C, and the wafer testing methods include: A chip mounting step S1: through the chip mounting equipment (E2), a plurality of chips (C) are transferred from a carrier plate to a plurality of electrical connectors (2) of the chip testing device (1); 1. Move into step S2: move the wafer testing device (1) carrying multiple wafers (C) to one of the containing chambers (E311) of one of the environmental control equipment (E3); A temperature adjustment step S3: controlling the operation of the temperature adjustment device (E34) in the containing chamber (E311) so that the plurality of wafers (C) are in an environment with a predetermined temperature; A test step S4: power is supplied to the wafer testing device (1) arranged in the containing chamber (E311), so that each test module (30) performs a predetermined test procedure on the multiple wafers (C) connected to it; One removal step S6: remove the wafer testing device (1) from the containing chamber (E311), and transfer the wafer testing device (1) to the sorting equipment (E5); A sorting step S7: Using sorting equipment (E5), according to the test results of each wafer (C) after completing the predetermined test procedure, place multiple wafers (C) in the good product area (A1) or the defective product area (A2) respectively .

In the embodiment where the power supply member 4 of the wafer testing device 1 includes multiple connection terminals, before the test step S4, a connection step may be included: connecting the multiple connection terminals of the power supply member 4 of the wafer testing device 1 to the A plurality of accommodating chamber terminals E33 in the accommodating chamber E311 are connected. In specific implementation, the connecting step may be between the moving-in step S2 and the temperature adjusting step S3, or the connecting step may also be between the temperature adjusting step S3 and the testing step S4.

As shown in FIG. 17, it is a schematic flowchart of a second embodiment of a wafer testing method of the present invention. The biggest difference between this embodiment and the embodiment shown in FIG. 16 is that a pumping step S21 may be included between the moving in step S2 and the temperature adjusting step S3. In the moving step S2, the cover E35 and the circuit board 10 of the wafer testing device 1 are connected to each other, and the cover E35 and the circuit board 10 together form a closed space SP2 (as shown in FIG. 14 ), and then, in the air extraction step S21, the air extraction device connected to the enclosed space SP2 is activated to extract the air in the enclosed space SP2 to the outside.

As shown in FIG. 14 and the corresponding embodiments described above, when the cover E35 and the circuit board 10 together form a closed space SP2, each electrical connection seat 2 is correspondingly located in the closed space SP2. After performing the air extraction step S21, each electrical connection base 2 will be located in an environment close to vacuum. Therefore, when the temperature adjustment step S3 is subsequently performed, the temperature of the enclosed space SP2 will not be easily affected by the external environment, and the electrical connection base 2 The surrounding temperature of the wafer C and the wafer C it carries can easily be maintained at a predetermined temperature.

As shown in FIG. 18, it is a schematic flowchart of a third embodiment of a wafer testing method disclosed in the present invention. The biggest difference between this embodiment and the previous embodiment is that between the test step S4 and the removal step S6, the following steps may also be included: A separation step S5: After the wafer testing device (1) completes the predetermined test procedure for all the connected wafers (C), control the power supply member (4) of the wafer testing device (1) and the accommodating chamber (E311) The plurality of receiving chamber terminals (E33) are separated from each other.

As shown in FIGS. 3, 9 and 10, in practical applications, the environmental control equipment E3 may also include a plurality of lifting devices E38, and each containing room E311 is provided with a lifting device E38. Each lifting device E38 is connected to the central control device E1. Each lifting device E38 can be controlled by the central control device E1, so that the wafer testing device 1 installed in the containing chamber E311 can be moved up and down, so that the multiple connection terminals of the power supply member 4 of the wafer testing device 1 and the containing chamber terminals E33 is connected or separated from each other.

In practical applications, when each wafer testing device 1 is transferred into the accommodating chamber E311 by the transfer equipment E4, the multiple power supply members 4 of the wafer testing device 1 may not be connected to the multiple accommodating chamber terminals E33, and when When the central control device E1 determines that the wafer testing device 1 is provided in any accommodating chamber E311, the central control device E1 can control the corresponding lifting device E38 to act, so as to move the wafer testing device 1 in the accommodating chamber E311, thereby The plurality of connection terminals of the power supply member 4 are connected to the accommodation chamber terminal E33, whereby the external power supply device can provide power to the plurality of test modules 30 through the power supply member 4.

In practical applications, the manner in which the central control device E1 determines whether there is a wafer testing device 1 in any accommodating chamber E311 can be designed according to requirements and is not limited here. For example, a sensor (such as an optical sensor or any mechanical push switch, etc.) may be provided in the accommodating chamber E311, and when the wafer testing device 1 enters the accommodating chamber E311, the sensor The sensor will correspondingly generate relevant signals and transmit them to the central control device E1, and the central control device E1 can determine whether the wafer testing device 1 is provided in the containing chamber E311 according to the signal transmitted by the sensor. Of course, the sensor can also be used to confirm whether the wafer testing device 1 is set in a predetermined position in the accommodating chamber E311, and the sensor can be based on the position of the wafer testing device 1 in the accommodating chamber E311, and transfer corresponding Signal to the central control device E1, the central control device E1 can be based on the signal transmitted by the sensor to determine whether the wafer test device 1 is located in the predetermined position in the containing chamber E311, if the central control device E1 determines the wafer test device 1 Located at a predetermined position in the accommodating chamber E311, the central control device E1 can control the lifting device E38 to act; on the contrary, if the central control device E1 determines that the wafer testing device 1 is not located in the predetermined position in the accommodating chamber E311, the central control device E1 can control related warning devices to act to warn users. For example, the central control device E1 can control related warning lights to emit light of a specific color, and control related display screens to display error messages.

In the embodiment where the power supply member 4 is a receiving antenna, when the wafer testing device 1 is set in the containing chamber E311, the corresponding transmitting antenna in the containing chamber E311 may be coupled with the receiving antenna, and the wafer testing The device 1 can obtain power through the power supply member 4. Of course, in another embodiment, the receiving antenna can also be coupled to the receiving antenna when the wafer testing device 1 is set in a predetermined position in the containing chamber E311, which is not limited here.

As shown in FIGS. 3 and 10, in the embodiment where each temperature adjusting device E34 has the aforementioned contact structure E34A1, E34B1, E343, when the lifting device E38 is controlled and actuated, the wafer testing device 1 and the multiple wafers it carries C will be driven by the lifting device E38 to move towards the contact structure E34A1, E34B1, E343 or move away from the contact structure E34A1, E34B1, E343.

In the embodiment in which the temperature adjusting device E34 is connected to the cover E35, when the lifting device E38 is controlled to move the wafer test device 1 to the contact structure E34A1, E34B1, E343 direction to a predetermined position, the cover E35 will cover the corresponding On the circuit board 10 of the wafer testing device 1, the cover E35 and the circuit board 10 will form a closed space SP2 together. Then, before the temperature adjustment step S3, the central control device E1 will first control the air extraction device E37 to extract air from the enclosed space SP2 so that the enclosed space SP2 is in a state close to vacuum. In this way, after the temperature adjustment step S3 , The temperature in the enclosed space SP2 will not be easily affected by the external environment.

In practical applications, when the wafer testing device 1 is set in the accommodating chamber E311, and the lifting device E38 raises the wafer testing device 1, the plurality of wafers C may not be in contact with the contact structures E34A1, E34B1, E343, but when After the pumping device E37 starts pumping, the multiple wafers C and the contact structures E34A1, E34B1, and E343 are in contact with each other, but it is not limited to this. In another embodiment, the plurality of wafers C may also be in contact with the contact structures E34A1, E34B1, and E343 when the pumping device E37 is not performing pumping.

In the testing step S4, the chip testing device 1 is coupled with or connected to the corresponding transmitting antenna or the terminal of the receiving chamber through the receiving antenna or a plurality of connection terminals to obtain power, so that each test module 30 The chip C connected to it can be tested.

As shown in Figures 9 and 10, in practical applications, in order to enable the multiple connection terminals of the power supply member 4 of the wafer testing device 1 to be firmly connected to the multiple accommodation chamber terminals E33, the environmental control equipment E3 may also include A plurality of limiting devices E39, and the plurality of limiting devices E39 are arranged in the plurality of accommodation chambers E311. Each limit device E39 is connected to the central control device E1. Each limiting device E39 can be controlled by the central control device E1 to limit the range of movement of the wafer testing device 1 in the containing chamber E311. The specific structure of the limiting device E39 can be designed according to requirements. For example, the wafer testing device 1 can be provided with a clamping hole, and the limiting device E39 includes a corresponding hook structure. When the limiting device E39 When actuated, the hook structure can be correspondingly locked in the locking hole; or, the limiting device E39 can include a plurality of telescopic pins, and the telescopic pins can be correspondingly penetrated in the locking hole of the wafer testing device 1 .

As described above, in the embodiments in which the contact structures E34A1, E34B1, E343, the lifting device E38, and the limiting device E39 are provided in each accommodating chamber E311 of each environmental control device E3, the above-mentioned wafer testing method is moved into step S2 , Can include the following steps: A step of moving into the containing chamber: moving the wafer testing device (1) into the containing chamber (E311); A rising step: controlling the lifting device (E38) in the containing chamber (E311) to move the wafer testing device (1) to the contact structure (E34A1, E34B1, E343); A locking step: controlling the limiting device (E39) in the accommodating chamber (E311) so that the limiting device (E39) limits the movement range of the wafer testing device (1) in the accommodating chamber (E311).

As described above, the wafer testing method of the present invention can be simply to mount multiple wafers on the wafer testing device 1; then, move the wafer testing device 1 to one of the accommodating chambers E311 of the environmental control equipment E3 Then, the lifting device E38 is controlled to raise the wafer testing device 1 so that one side of the multiple wafers C of the wafer testing device 1 is adjacent to the contact structures E34A1, E34B1, E343 of the temperature regulating device E34, and the temperature regulating device The cover E35 connected to the E34 is arranged on the circuit board 10 of the wafer testing device 1 to form a closed space SP2; then, the air extraction device E37 is controlled to evacuate the closed space SP2, so that multiple One side of the wafer C is attached to the contact structures E34A1, E34B1, E343, and at the same time, the operation of the temperature adjustment device E34 is controlled to make the wafer C reach a predetermined temperature; when the temperature adjustment device E34 is activated, power is supplied to the wafer test device 1 to The multiple test modules 30 test multiple chips C.

Please refer to FIG. 19, which shows a schematic flow chart of the fourth embodiment of the chip testing method disclosed in the present invention. The chip testing system E can use this chip testing method to test multiple memories (ie, the aforementioned chips). The biggest difference between the wafer testing method disclosed in this embodiment and the aforementioned wafer testing method is: after moving into step S2 and before separating step S5, the temperature adjustment step S3 and the test step S4 can be repeated twice, which are respectively Temperature adjustment step S31, test step S41, temperature adjustment step S32, and test step S42.

In the temperature adjustment step S31 and the test step S41 (that is, the temperature adjustment step S3 and the test step S4 are executed for the first time), the temperature adjustment device E34 corresponding to the accommodating chamber E311 is first controlled so that the plurality of wafers C are at 115 In an environment with a temperature above ℃, each test module 30 is then controlled to perform at least one of a read test, a write test, and an electrical test on the plurality of chips C. The temperature adjustment step S31 and the test step S41 referred to here are to perform a burn-in test on the memory.

In the temperature adjustment step S32 and the test step S42 (that is, the temperature adjustment step S3 and the test step S4 are executed for the second time), the temperature adjustment device E34 corresponding to the accommodating chamber E311 is first controlled so that the plurality of wafers C are at 75 In an environment with a temperature ranging from ℃ to 95 ℃, each test module 30 is then controlled to perform at least one of a read test, a write test and an electrical test on the plurality of chips C. The temperature adjustment step S31 and the test step S41 referred to here are to perform a high temperature test on the memory.

It is particularly noted that in different embodiments, between the above-mentioned test step S41 and the temperature adjustment step S32, there may be a moving-out step and a moving-in step; the moving-out step is to move the wafer testing device 1 out of the current content. In the holding chamber E311, the moving step is to move the wafer testing device 1 into another holding chamber E311. In other words, the wafer testing device 1 can be located in two different containing chambers E311 with a temperature above 115°C and a temperature ranging from 75°C to 95°C (which can be located in the same environmental control equipment E3 or in different environments). The test operation is performed in the control equipment E3).

Please refer to FIG. 20, which shows a schematic flowchart of a fifth embodiment of the chip testing method disclosed in the present invention. The chip testing system E can use this chip testing method to test multiple memories (ie, the aforementioned chips). The biggest difference between the wafer testing method disclosed in this embodiment and the wafer testing method shown in FIG. 19 is that after moving into step S2 and before separating step S5, the temperature adjustment step S3 and the test step S4 can be repeated three times , Which are the aforementioned temperature adjustment step S31, the aforementioned test step S41, the aforementioned temperature adjustment step S32, the aforementioned test step S42, the aforementioned temperature adjustment step S33, and the aforementioned test step S43.

After performing the aforementioned temperature adjustment step S32 and the aforementioned test step S42, the executed temperature adjustment step S33 and the test step S43 (that is, the temperature adjustment step S3 and the test step S4 are executed for the third time) are first controlled by the containing chamber E311 Corresponding temperature adjustment device E34, so that the plurality of chips C are in a temperature environment of -55°C to -35°C, and then each test module 30 is controlled to perform read test, write test and electrical properties on the plurality of chips C At least one of the tests. In other words, the wafer testing method disclosed in this embodiment is to sequentially perform a burn-in test, a high temperature test, and a low temperature test on a plurality of wafers C.

Please refer to FIG. 21, which shows a schematic flow chart of the sixth embodiment of the chip testing method disclosed in the present invention. The chip testing system E can use this chip testing method to test multiple memories (ie, the aforementioned chips). The biggest difference between the wafer testing method disclosed in this embodiment and the wafer testing method shown in FIG. 19 is that after moving into step S2 and before separating step S5, the temperature adjustment step S3 and the test step S4 can be repeatedly executed. Next, they are the aforementioned temperature adjustment step S31, the aforementioned test step S41, the aforementioned temperature adjustment step S32, the aforementioned test step S42, the aforementioned temperature adjustment step S33, the aforementioned test step S43, the aforementioned temperature adjustment step S34, and the aforementioned test step S44.

After executing the aforementioned temperature adjustment step S33 and the aforementioned test step S43, the executed temperature adjustment step S34 and the test step S44 (that is, the temperature adjustment step S3 and the test step S4 are executed for the fourth time) are first controlled by the containing chamber E311 The corresponding temperature adjusting device E34 keeps the plurality of chips C in a temperature (normal temperature) environment of 20°C to 30°C, and then controls each test module 30 to perform reading, writing, and electrical tests on the plurality of chips C At least one of the sex tests. In other words, the wafer testing method disclosed in this embodiment is to sequentially perform a burn-in test, a high temperature test, a low temperature test, and a normal temperature test on a plurality of wafers C.

As described above, the wafer testing method of the present embodiment can be executed by using the wafer testing system E in which each temperature adjusting device E34 in each environmental control device E3 has a refrigerator E342 and a heater E341 in the foregoing description. However, after the wafer testing device 1 is moved into the containing chamber E311 of the environmental control equipment E3, it will be sequentially placed in an environment with a temperature of 115°C or higher, a temperature of 75°C to 95°C, and -55°C to -35°C. At least one of the reading test, the writing test, and the electrical test is performed in an environment with a temperature of 20°C to 30°C, that is, a plurality of chips C are sequentially burned (Burn- In) test, high temperature test, low temperature test and room temperature test. Of course, in practical applications, the sequence of the wafer testing device 1 for the burn-in test, high temperature test, low temperature test, and normal temperature test on multiple wafers C may be arranged according to requirements, and is not limited to the above sequence.

Please refer to FIG. 22, which shows a schematic flowchart of a seventh embodiment of the chip testing method disclosed in the present invention. The chip testing system E can use this chip testing method to test multiple memories (ie, the aforementioned chips). The biggest difference between the wafer testing method disclosed in this embodiment and the wafer testing method shown in FIG. 19 is that the following steps may be included between the removing step S6 and the sorting step S7: 1. Move into step SX1: move the wafer testing device (1) carrying multiple wafers (C) to the containing chamber (E311) of another environmental control device (E3); A temperature adjustment step SX2: controlling the operation of the temperature adjustment device (E34) in the containing chamber (E311) so that the multiple wafers (C) are in an environment of -55°C to -35°C; A test step SX3: power is supplied to the wafer testing device (1) set in the containing chamber (E311), so that each test module (30) performs a predetermined test procedure on the multiple wafers (C) connected to it.

In the wafer testing method of this embodiment, the wafer testing device 1 is first installed in the containing chamber E311 of one of the environmental control equipment E3, and the multiple wafers C are sequentially placed in an environment with a temperature above 115°C and 75°C. Perform at least one of the read test, write test, and electrical test in an environment with a temperature of 95°C; then, move the wafer test device 1 out of the containing chamber E311, and move the wafer test device 1 into different environmental controls One of the accommodating chambers E311 of the equipment E3 (or the other accommodating chamber E311 moved into the same environmental control equipment E3); subsequently, the temperature control device E34 of the accommodating chamber E311 operates, so that the wafer testing device 1 At least one of a reading test, a writing test, and an electrical test is performed in an environment where the carried multiple chips C are at a temperature of -55°C to -35°C.

The wafer testing method of this embodiment can be executed by the wafer testing system E in the foregoing description, especially the wafers with only the heating device E34A or only the cooling device E34B in each accommodating chamber E311 of each environmental control device E3 Test system E.

In the wafer testing method of this embodiment, since the temperature of a single accommodating chamber E311 will not drop from a temperature above 100°C to a temperature below 0°C, it can be greatly shortened to make the temperature around each wafer C reach a predetermined high temperature and The time of the predetermined low temperature temperature can also greatly reduce the energy required for each temperature adjusting device E34 to reach the predetermined temperature of the containing chamber E311.

As shown in FIG. 23, it shows a schematic flow chart of the eighth embodiment of the wafer testing method disclosed in the present invention. The wafer testing system E can use this wafer testing method to test multiple memories (ie, the aforementioned wafers). The biggest difference between the wafer test method disclosed in this embodiment and the aforementioned wafer test method is that after the temperature adjustment step SX2 and the test step SX3, the temperature adjustment step SX4 and the test step SX5 may also be included. In the temperature adjustment step SX4, the operation of the temperature adjustment device E34 in the accommodating chamber E311 is controlled so that the plurality of wafers C are in an environment of 20°C to 30°C. In the testing step SX5, power is supplied to the wafer testing device 1 arranged in the containing chamber E311, so that each testing module 30 performs a predetermined testing procedure on the multiple wafers C connected to it. That is, in the temperature adjustment step SX2 and the test step SX3, the plurality of wafers C are tested in a low temperature environment, and in the temperature adjustment step SX4 and the test step SX, the plurality of wafers C are tested in a normal temperature environment Test under.

Please refer to FIG. 24, which shows a schematic flowchart of a ninth embodiment of the chip testing method disclosed in the present invention. The chip testing system E can use this chip testing method to test multiple memories (ie, the aforementioned chips). The biggest difference between the wafer testing method disclosed in this embodiment and the aforementioned wafer testing method is that the wafer testing device 1 is brought into contact with the contact structures E34A1, E34B1, and E343 to complete the predetermined test procedure, and the wafer testing device 1 is removed from the container. When chamber E311 is set (that is, after any step is removed), the following steps can be followed: A position test step SY1: the image capturing unit in a position detecting device E8 is used to capture images of a plurality of electrical connectors (2) and a plurality of chips (C) arranged on them to generate a captured image information ； A judging step SY2: judging whether the positions of the multiple chips relative to their corresponding electrical connectors meet the allowable deviation according to the captured image information. If the positions of multiple wafers relative to their corresponding electrical connection seats meet the allowable deviation, then the wafer testing device (1) is successively transferred to the next workstation, or transferred to another accommodating chamber (E311), This allows multiple wafers (C) to be tested in another temperature environment. The workstation is, for example, transferred to the sorting device (E5) for sorting operations. If the positions of the multiple chips relative to their corresponding electrical connection seats do not meet the allowable deviation, the chips are reinstalled.

In practical applications, if the positions of multiple chips relative to their corresponding electrical connectors do not meet the allowable deviation, the central control device E1 controls the transfer equipment E4 to transfer the wafer testing device 1 to the wafer mounting equipment E2 , And then use the wafer mounting equipment E2 to re-mount the specific wafer C, or it can also re-mount all the wafers C. Of course, it is also possible to re-install the wafer C on the wafer testing device 1 through another mechanical arm other than the wafer mounting equipment E2; or, the central control device E1 can control the transfer equipment E4 to test the wafer The device 1 is transferred to a temporary storage area, and relevant reminders are sent out to notify relevant personnel. In practical applications, the position detection equipment E8 may also have a wafer mounting device (not shown, for example, including a stage and a robot arm), and the wafer mounting device can directly perform at least one wafer C on the wafer testing device 1 Reinstall the job. The position test step SY1 and the judgment step SY2 mentioned in this embodiment can be arranged after any step of removing the wafer testing device 1 according to requirements.

Please refer to FIGS. 1 and 3 again. In practical applications, the chip testing system E may also include two image capturing units E91 and E92, and the two image capturing units E91 and E92 are connected to the central control device E1. The image capturing unit E91 is arranged adjacent to the chip mounting device E2. The chip mounting device E2 is used to set the chip C on the chip testing device 1, and the image capturing unit E91 is used to capture the chip testing device 1 and its carried After receiving the image information captured by the image capturing unit E91, the central control device E1 can determine whether the chip C on the chip testing device 1 is correctly installed; if the central control device E1 determines that the chip C is not If it is correctly installed on the wafer testing device 1, the central control device E1 can control the wafer mounting equipment E2 to reinstall the wafer C.

The image capturing unit E92 is disposed adjacent to the sorting equipment E5, and the image capturing unit E92 is used to capture the image of the chip C disposed in the defective product area or the good product area, and the central control device E1 can receive the image capturing unit E92. The captured image is used to determine whether the chip C is correctly installed (for example, it is installed on a carrier). If the central control device E1 determines that the chip C is not installed correctly, the central control device E1 can control the sorting equipment E5 or the neighboring related robot arm, the chip mounting equipment E2 and other equipment to reinstall the chip C.

Please refer to FIG. 1 again, the wafer test system E disclosed in the present invention may also include a pre-test (Pre-Test) device E6. The pre-test equipment E6 is connected to the central control device E1. The pre-test equipment E6 may include at least one electrical connector (the specific structure of the electrical connector may be the same as the electrical connector 2 shown in Figures 5 and 6), and the electrical connector of the pre-test equipment E6 is used to carry a chip C. The pre-test equipment E6 can perform an Open/Short Test and a Leakage Test on the chip C. In a specific application, the pre-testing equipment E6 may include the wafer testing device 1 shown in FIG. 3, and the pre-testing equipment E6 may perform the wafer C test through the included wafer testing device 1 shown in FIG. test.

In the embodiment where the chip test system E is applied to test memory, especially NAND Flash, the above-mentioned pre-testing equipment E6 with the aforementioned chip testing device 1 first performs short-circuit testing on multiple memories (ie, the aforementioned chip C) and Leakage current test will greatly improve the overall test performance. Specifically, the memory must spend a lot of time in the aforementioned high temperature test, burn-in test, low temperature test and normal temperature test. Therefore, the preliminary screening of the memory through the pre-test equipment E6 can ensure the chip test device Each electrical connection socket 2 on 1 is effectively used, and it can prevent the memory that fails the short circuit test (Open/Short Test) and the leakage current test (Leakage Test) from occupying the electrical connection socket 2 during the subsequent test. The problem occurs. In different applications, in addition to the short-circuit test and leakage current test of the memory, the pre-test equipment E6 can also perform specific DC electrical tests on the memory and various locations of the memory according to requirements. Perform a read operation (Read ID).

In different embodiments, before the classification step S7, a final test step may also be included, which includes: One installation step: install multiple chips on the electrical connection seat of a final test device; A test step: controlling the final test equipment to perform an Open/Short Test and a leakage current test (Leakage Test) on the chip installed on the final test equipment; A judging step: judging whether the chip set on the pre-testing device has passed the short circuit test and the leakage current test; wherein, if the chip fails the short circuit test or the leakage current test, then all the chips are classified in the classification step. The chip is transferred to the defective product area.

The electrical connection base included in the final test equipment may be the same as the electrical connection base 2 shown in FIG. 5 and FIG. 6, and is not limited herein. The setting of the final test equipment can assist in accelerating the classification speed of the classification equipment. Specifically, when the sorting equipment classifies each wafer, it will transfer each wafer to a specific area based on the test results of the wafer during each test process. Therefore, when one of the wafers is in the test process, unexpected If the wafer fails to pass any test, the sorting equipment will waste a lot of time in sorting the wafer without the above-mentioned final test steps. In actual applications, the final test equipment, wafer mounting equipment E2 and pre-testing equipment E6 can use the same robotic arm to perform wafer mounting operations, but not limited to this, the final testing equipment, wafer mounting equipment E2 and pre-testing The equipment E6 can also have independent robotic arms.

As shown in FIG. 25, it shows a schematic flow chart of the tenth embodiment of the chip testing method disclosed in the present invention. The chip testing system E can use this chip testing method to test multiple memories (ie, the aforementioned chips). The biggest difference between the chip test method disclosed in this embodiment and the aforementioned chip test method is that a pre-test step may be included before the chip mounting step S1, which includes: An installation step S01: remove multiple memories (chips C) from the carrier one by one, and install them on the electrical connector of a pre-test equipment (E6); A test step S02: control the pre-test equipment (E6) to perform a short circuit test and a leakage current test on the memory (chip C); A judgment step S03: if the memory (chip C) passes the short circuit test and the leakage current test, then execute the chip mounting step S1; if the memory (chip C) fails the short circuit test or the leakage current test, then the memory (chip C) Transfer to the defective product area (A2).

As shown in Figure 1, in practical applications, the pre-testing equipment E6 can be set between a tray loading equipment E7 and the wafer mounting equipment E2, and the pre-testing equipment E6, tray loading equipment E7 and wafer mounting equipment There can be at least one robotic arm installed between E2; the robotic arm can be used to unload the memory (chip) on the tray of the tray loading equipment E7, and then first place it on the electrical connector of the pre-test equipment E6; If the memory (chip) passes the short-circuit test and the leakage current test, the robotic arm will remove the chip and mount the chip on the electrical connector 2 of the chip testing device 1 set in the chip mounting equipment E2; if the memory If the body (chip) fails the short circuit test and the leakage current test, the robotic arm places the memory (chip) in another defective product area A3; in actual applications, the chip mounting equipment E2 and the pre-test equipment E6 can The same robotic arm is used to transfer the wafer, but it is not limited to this. In different embodiments, it is also possible that the wafer mounting equipment E2 and the pre-testing equipment E6 have different robotic arms.

As shown in FIG. 26, in different embodiments, after each test module 30 completes a predetermined test procedure for the chip C on the plurality of electrical connection sockets 2 to which it is connected, the test module 30 may be The test result data C2 and the corresponding test parameter data C3 are written into each chip C, so that each chip C stores the test result data C2 and the test parameter data C3.

Furthermore, the test result data C2 may include, for example, the test conditions of the chip C in the high temperature test, the burn-in test, the low temperature test and the normal temperature test respectively, or it may only record whether the chip C passes the high temperature test. Test, whether to pass the burn-in test, whether to pass the low temperature test, and whether to pass the normal temperature test.

The test parameter data C3 may include, for example, the identification number (ID Number) of the wafer testing device 1, the identification number of the test module 30, the identification number of the electrical connection base 2, the identification number of the environmental control equipment E3 and its accommodation chamber. E311 identification number, temperature value during high temperature test, time of high temperature test, temperature value during burn-in test, time of burn-in test, temperature value during low temperature test, time of low temperature test, temperature value during normal temperature test and Time of room temperature test, etc.

Through the above design that the test module 30 writes the test result data C2 and test parameter data of the chip C into the chip C, when any chip C is delivered to the consumer, the consumer can read it through the relevant equipment The data stored in the chip C can be used to confirm the inspection status during its production; and when the relevant production personnel receive any chip C returned by the consumer, they can also read the test results stored in the chip C Data C2 and test parameter data are used to quickly trace the inspection history of the chip C, which can effectively help the production personnel to find possible defects in the inspection process.

As shown in FIG. 27, which shows a schematic flow chart of the eleventh embodiment of the chip testing method disclosed in the present invention, the above-mentioned chip testing system E can use this chip testing method to test multiple memories (ie, the aforementioned chips) . The biggest difference between the wafer test method disclosed in this embodiment and the foregoing wafer test method is that after each test step, the following steps may be included: A test result writing step SW: store the test result data of each memory after the predetermined test procedure and the corresponding test parameter data are stored in each memory.

In the above embodiment, when each test module 30 completes any test (for example, including high temperature test, burn-in test, low temperature test, and normal temperature test) on the memory connected to it, the corresponding test is immediately performed The result data C2 and the test parameter data C3 are stored in the memory, but in practical applications, it is not limited to this.

Please refer to FIG. 4 again. In different applications, each test module 30 may include a processing unit 5 and at least one storage unit 6. When each test module 30 completes any test (for example, a high temperature test, a burn-in test, a low temperature test, and a normal temperature test) on the memory on the multiple electrical connection sockets 2 to which it is connected, it may not directly compare the phases. The corresponding test result data C2 and test parameter data C3 are stored in the memory, and each test module 30 stores the test result data C2 of each chip C and the test parameter data C3 in the storage unit 6 of each test module 30 in. In another embodiment, the chip test device 1 may include a storage unit, and each test module 30 may store the test result data C2 and its test parameter data C3 of the chip C connected to the chip test device 1 in the storage unit. In other words, the chip testing apparatus 1 may include a storage unit 6, and the storage unit 6 may be provided in each test module 30 according to requirements, or the storage unit 6 may also be provided independently of a plurality of test modules 30.

In addition, when the memory carried by the chip testing device 1 completes all tests (such as burn-in test and high temperature test, or burn-in test, high temperature test, low temperature test and normal temperature test) according to requirements, the central control device E1 can It controls a read-write device (not shown in the figure), which is connected to the multiple connection terminals of the power supply member 4 of the chip testing device 1 to connect the storage unit of the chip testing device 1 or the storage unit 6 of each test module 30, The stored test result data C2 and test parameter data C3 are read out, and each test result data C2 and test parameter data C3 are written into the corresponding memory through the read-write device.

In another embodiment, the wafer testing device 1 may also include a wireless transmission unit 7 connected to the processing unit (not shown). When each test module 30 completes a predetermined test procedure for the chips on the plurality of electrical connection sockets 2 to which it is connected, each test module 30 will correspondingly generate test result data C2 and test parameter data C3. The processing unit can receive the test result data C2 and the test parameter data C3 transmitted by each test module 30, and the processing unit can control the wireless transmission unit 7 to wirelessly transmit the test result data C2 and multiple test parameter data C3 to a An external electronic device. The external electronic device is, for example, a central control device E1. Then, the central control device E1 can write each test result data C2 and test parameter data C3 into the corresponding memory through a read-write device.

As shown in FIG. 28, it is a schematic flowchart of the twelfth embodiment of the wafer testing method disclosed in the present invention. The biggest difference between this embodiment and the flowchart shown in FIG. 16 is that after the classification step S7, it may include: A test result writing step S8: Store the test result data of each memory after the predetermined test procedure and the corresponding test parameter data are stored in each memory.

Specifically, when the memory carried by the chip testing device 1 completes all tests (for example, burn-in test and high temperature test, or burn-in test, high temperature test, low temperature test, normal temperature test) according to requirements, the central control device E1 It can first control the classification device E5, and classify each memory according to the test result of each memory. Then, the central control device E1 controls the related reading and writing equipment to perform related reading and writing operations on the memory that has been classified into the good product area A1 to store the corresponding test result data C2 and test parameter data C3 in each memory Body. In other words, only the memory that is classified as a good product can store the test result data C2 and the test parameter data C3 inside.

As shown in FIG. 29, it is a schematic flowchart of the thirteenth embodiment of the wafer testing method disclosed in the present invention. The biggest difference between this embodiment and the flowchart shown in FIG. 16 is that before the classification step S7, it may include: A test result writing step S7A: Store the corresponding test result data and test parameter data in the memory that has passed each predetermined test procedure in the corresponding memory.

Specifically, when the memory carried by the chip testing device 1 is completed and passed all tests (for example, burn-in test and high temperature test, or burn-in test, high temperature test, low temperature test, and normal temperature test) according to requirements, the chip test The device 1 writes the test results and related test parameter data corresponding to the memory into the memory; on the contrary, if the memory fails at least one of the tests, the chip testing device 1 will not write the memory Any corresponding test-related data is written in the memory. In this way, in the classification step S7, the classification device can quickly determine whether the memory has passed the test by determining whether any of the above-mentioned test-related data is written in the memory, and if the classification device determines that the above-mentioned data is not written in the memory , The classification device can directly classify the memory to the defective area.

Please refer to FIG. 30. In practical applications, the central control device E1 of the chip test system E may include a master control device E11 (Master control device), a chip test control device E12, an environmental state control device E13, and a transfer Control device E14. Regarding the number of the wafer test control device E12, the environmental state control device E13, and the transfer control device E14, it can be changed according to demand, and is not limited to a single one.

In the embodiment where the wafer test system E has a single wafer test control device E12, the wafer test control device E12 may be used to control the actions of all the wafer test devices 1, the pre-test equipment E6, and the final test equipment to perform multiple wafer tests. Various test jobs. In simple terms, the wafer test control device E12 can be used to control any equipment used to test wafers. In an embodiment in which the wafer test system E includes multiple wafer test control devices E12, each wafer test control device E12 may correspondingly control at least one wafer test device 1; and different wafer test control devices E12 may correspondingly control The wafer test device 1 connected to it performs different test operations.

In the embodiment where the wafer test system E has a single environmental state control device E13, the environmental state control device E13 may be used to control the action of any environmental control device E3 to control the action of any environmental control device E3, for example, The environmental state control device E13 can control the action of the temperature adjustment device E34, the air extraction device E37, the lifting device E38, and the limit device E39 of any environmental control device E3. In an embodiment in which the wafer test system E includes multiple environmental state control devices E13, each environmental state control device E13 may correspondingly control at least one environmental control device E3; and different environmental state control devices E13 may correspondingly control The environmental control equipment E3 connected to it performs completely different actions. It is worth mentioning that each environmental state control device E13 can control the action of each component in any environmental control device E3, such as the action of each sensor in each environmental control device E3, and the result of each sensor sensing.

In the embodiment where the wafer test system E has a single transfer control device E14, the transfer control device E14 may be used to control the wafer mounting equipment E2, the position detection equipment E8, the transfer equipment E4, and the sorting equipment E5. To put it simply, the transfer control device E14 can be used to control any equipment used to transfer the wafer test device 1 or wafers. Of course, in the embodiment where the wafer test system E includes multiple transfer control devices E14, the multiple transfer control devices E14 can be classified according to requirements, and correspondingly control different equipment, for example, one of the transfer control devices E14 The device E14 may be a device specifically used to control the wafer transfer test device 1, and one of the transfer control devices E14 may be a device specifically used to control wafer transfer.

The main control device E11 is connected to the chip test control device E12, the environmental state control device E13, and the transfer control device E14, and the main control device E11 can be used to control the chip test control device E12, the environmental state control device E13, and the transfer control device E14 Collaboration between each other. In specific applications, the main control device E11, the chip test control device E12, the environmental state control device E13, and the transfer control device E14 may all be composed of at least one computer device, a server, etc., but it is not limited thereto.

By designing the wafer test system E to include the main control device E11, the wafer test control device E12, the environmental state control device E13, and the transfer control device E14, the wafer test system E will be relatively easy to perform related control during the manufacturing process Integration, and the chip test system E is easier to quickly find problems during subsequent operation and maintenance.

In particular, in any of the foregoing implementations, the wafer testing device 1 is not limited to being powered during the testing step, and the wafer testing device 1 can be installed in the accommodating chamber E311 and at any point in time between the testing steps. Power is supplied, and the wafer testing device 1 is not limited to being powered during the test step. In other words, in practical applications, the wafer testing device 1 can be powered immediately when it is installed in the accommodating chamber E311, or the wafer testing device 1 can also be powered only when the testing step is performed.

In addition, it should be emphasized that in any of the above embodiments in which the power supply member includes multiple connection terminals, the connection terminals and the accommodation chamber terminals can be directly replaced with receiving antennas and transmitting antennas. Of course, since the receiving antenna and the transmitting antenna are used for wireless power transmission, when directly replacing the connecting terminal and the receiving room terminal with the receiving antenna and the transmitting antenna, it can be ignored in some of the above embodiments. Relevant process steps of contacting or separating the connecting terminal and the accommodating chamber terminal.

In summary, the wafer testing system, wafer testing device, and wafer testing method suitable for the wafer testing system disclosed in the present invention not only have a cost advantage, but also have better advantages than existing wafer testing equipment. Test efficiency. In addition, the wafer testing system disclosed in the present invention sets a plurality of wafers on the wafer testing device, and then transfers the wafer testing device to place the wafers in different temperature environments for related testing operations. Therefore, the wafers In the process of testing in different temperature environments, they are all set on the same chip testing device, and the chip will not be repeatedly disassembled and installed during the entire test process, and the chip will not be prone to unexpected damage and other problems . On the contrary, the existing memory testing equipment repeatedly disassembles and installs the memory on the electrical connector in different temperature environments. Therefore, the memory is prone to unexpected damage after repeated disassembly and installation. problem.

The content disclosed above is only the preferred and feasible embodiments of the present invention, and does not limit the patent scope of the present invention. Therefore, all equivalent technical changes made by using the description and drawings of the present invention are included in the patent scope of the present invention. Inside.

E: Wafer test system E1: Central control device E11: Master control device E12: Wafer test control device E13: Environmental status control device E14: Transfer control device E2: Chip mounting equipment E3: Environmental control equipment E31: Equipment body E311: containing room E32: The second data transmission terminal E33: Terminal E34: Temperature adjustment device E34A: heating device E34A1: High temperature contact structure E34B: Refrigerator E34B1: Low temperature contact structure E341: heater E342: Refrigerator E343: Contact structure E344: runner E345: fluid inlet E346: fluid outlet E35: Cover E351: Groove E352: containment opening E353: Vent E36: Lid E37: Air extraction device E38: Lifting device E39: limit device E4: Transfer equipment E5: Sorting equipment E6: Pre-test equipment E7: Disk loading equipment E8: Location detection equipment E91: Image capture unit E92: Image capture unit 1: Wafer testing device 10: Circuit board 101: first side 102: second side 2: Electrical connection seat 20: Probe assembly 201: Needle Body 202: Spring 21: Connection base body 21A: Opening 21B: holding tank 21C: keyhole 211: top wall 2111: outer side 2112: inside 212: Ring sidewall 22: Lifting structure 22A: connecting hole 22B: wafer container 221: base 222: Bearing Department 223: Limit 23: Supporting structure 231: base structure 232: auxiliary structure 24: Elastic component 3: control unit 30: Test module 31: Chassis 4: Power supply component 5: Processing unit 6: Storage unit 7: Wireless transmission unit 8: The first data transmission terminal A1: Good product area A2: Defective product area A3: Defective product area C: chip C1: Electrical connection part C2: Test result data C3: Test parameter data SP1: Housing space SP2: enclosed space S: gap

FIG. 1 is a schematic diagram of the wafer testing system disclosed in the present invention.

FIG. 2 is a block diagram of the wafer testing system disclosed in the present invention.

FIG. 3 is a schematic diagram of a wafer testing device of the wafer testing system disclosed in the present invention.

4 is a block diagram of the wafer testing device of the wafer testing system disclosed in the present invention.

5 is a schematic diagram of the electrical connection seat of the wafer testing device of the wafer testing system disclosed in the present invention.

6 is a schematic cross-sectional exploded view of the electrical connector of the wafer testing device of the wafer testing system disclosed in the present invention.

7 is a schematic cross-sectional view of the electrical connector of the wafer testing device of the wafer testing system disclosed in the present invention without a wafer.

FIG. 8 is a schematic cross-sectional view of the electrical connection seat of the wafer testing device of the wafer testing system disclosed by the present invention provided with a wafer.

FIG. 9 is a schematic diagram of the environmental control equipment of the wafer test system disclosed in the present invention.

10 is a block diagram of the environmental control equipment and the central control device of the wafer test system disclosed in the present invention.

11 is a schematic diagram of the assembly of the temperature adjusting device and the cover of the wafer test system disclosed in the present invention.

12 and 13 are exploded schematic diagrams of the temperature adjusting device and the cover of the wafer testing system disclosed in the present invention.

14 is a schematic cross-sectional view of the temperature adjusting device and the cover of the wafer testing system disclosed in the present invention being arranged on the wafer testing device.

Fig. 15 is a partial enlarged schematic diagram of Fig. 14.

FIG. 16 is a schematic flow chart of the first embodiment of the wafer testing system for testing multiple wafers by the wafer testing method disclosed in the present invention.

FIG. 17 is a schematic flowchart of a second embodiment of the wafer testing system disclosed in the present invention to test multiple wafers by using the wafer testing method.

FIG. 18 is a schematic flowchart of a third embodiment of the wafer testing system for testing multiple wafers by the wafer testing method disclosed in the present invention.

FIG. 19 is a schematic flowchart of a fourth embodiment of the wafer testing system disclosed in the present invention to test multiple wafers by using the wafer testing method.

FIG. 20 is a schematic flowchart of a fifth embodiment of the wafer testing system disclosed in the present invention to test multiple wafers by using the wafer testing method.

FIG. 21 is a schematic flowchart of a sixth embodiment of the wafer testing system disclosed in the present invention to test multiple wafers by using a wafer testing method.

FIG. 22 is a schematic flowchart of a seventh embodiment of the wafer testing system disclosed in the present invention to test multiple wafers by using the wafer testing method.

FIG. 23 is a schematic flow chart of the eighth embodiment of the wafer testing system for testing multiple wafers by the wafer testing method disclosed in the present invention.

24 is a schematic flowchart of a ninth embodiment of the wafer testing system disclosed in the present invention to test multiple wafers using a wafer testing method.

FIG. 25 is a schematic flowchart of a tenth embodiment of the wafer testing system for testing multiple wafers by the wafer testing method disclosed in the present invention.

26 is a schematic block diagram of the memory after passing the test of the chip test system disclosed in the present invention.

FIG. 27 is a schematic flow chart of the eleventh embodiment of the wafer testing system using the wafer testing method to test multiple wafers according to the present invention.

FIG. 28 is a schematic flow chart of the twelfth embodiment of the wafer testing system for testing multiple wafers by the wafer testing method disclosed in the present invention.

FIG. 29 is a schematic flowchart of the thirteenth embodiment of the wafer testing system for testing multiple wafers by the wafer testing method disclosed in the present invention.

Figure 30 is a block diagram of the central control device disclosed in the present invention.

E: Wafer test system

E2: Chip mounting equipment

E3: Environmental control equipment

E4: Transfer equipment

E5: Sorting equipment

E6: Pre-test equipment

E7: Disk loading equipment

E8: Location detection equipment

E91: Image capture unit

E92: Image capture unit

A1: Good product area

A2: Defective product area

A3: Defective product area

Claims (13)

A wafer testing system for testing multiple wafers, the wafer testing system comprising: A central control device; At least one chip testing device, which includes a plurality of electrical connection seats, each of the electrical connection seats is used to carry one chip, and the chip testing device can be controlled by the central control device to control the plurality of electrical connection seats it carries. The chip performs a predetermined test procedure, and the chip test device has at least one power supply component; A chip mounting device, which can be controlled by the central control device to mount a plurality of the chips on a plurality of electrical connection seats of the chip testing device; At least one environmental control device, the environmental control device is connected to the central control device, and each of the environmental control devices includes: An equipment body comprising a plurality of accommodating chambers, the equipment body is connected to a power supply device, each of the accommodating chambers can accommodate the wafer testing device, and the equipment body has a plurality of power supply members; A plurality of temperature adjustment devices, each of the accommodating chambers is provided with one temperature adjustment device; each of the temperature adjustment devices can be controlled by the central control device, so that all of the corresponding accommodating chambers The ambient temperature of the wafer on the plurality of electrical connection seats of the wafer testing device reaches a predetermined temperature; A transfer equipment, which can be controlled by the central control device to carry the wafer testing device, so that the wafer testing device is placed in the wafer mounting equipment and the multiple accommodating devices of the multiple environmental control equipment Between the chamber and the sorting equipment; wherein, when the transfer equipment transfers the wafer testing device carrying a plurality of the wafers from the wafer mounting equipment to one of the environmental control equipment When one of the accommodating chambers is in, the power supply device can provide power to the wafer test device through the power supply member of the device body and the power supply member of the wafer test device; when the wafer test device is When power is supplied and the temperature adjustment device makes the surrounding temperature of the plurality of wafers on the wafer test device reach the predetermined temperature, the central control device can control the wafer test device to control the amount of the wafer Performing a predetermined test procedure on each of the chips; A sorting device, the sorting device can be controlled by the central control device, and a plurality of the wafers are unloaded from the plurality of the electrical connection seats of the wafer testing device, and the sorting device can be based on each Placing each of the chips in a good product area or a defective product area according to the test result after the chip has completed the predetermined test procedure; Wherein, when the wafer testing device completes the predetermined test procedure for the multiple wafers it carries, the central control device will control the transfer equipment to transfer the wafer testing device from the container. The storage room is transferred to the classification equipment. The wafer testing system according to claim 1, wherein the wafer testing device further includes: A circuit board whose opposite sides are defined as a first side and a second side respectively; A plurality of the electrical connection seats are fixedly arranged on the first side surface of the circuit board, each of the electrical connection seats is used to carry at least one of the chips; the plurality of electrical connection seats are divided into a plurality of Electrical connection base groups, each of the electrical connection base groups includes at least one of the electrical connection bases; A control unit, the control unit is arranged on the second side of the circuit board, the control unit includes a plurality of test modules, the plurality of the test modules are connected to the plurality of the electrical connection seat groups Connected, and each of the test modules is connected to all the electrical connection sockets in the corresponding electrical connection socket group; each of the test modules is used to connect the multiple electrical connections to it The chip on the seat performs the predetermined test procedure; and Wherein, the power supply component is connected to the circuit board; the power supply device can provide power to each of the test modules through the power supply component of the device body and the power supply component of the wafer testing device. The wafer test system according to claim 2, wherein the power supply member of the wafer test device includes a plurality of connection terminals, and the plurality of connection terminals are provided on the circuit board; the power supply member of the equipment body includes a plurality of A receiving chamber terminal, a plurality of the receiving chamber terminals are provided in each of the receiving chambers; the plurality of connecting terminals are used to connect to a plurality of the receiving chamber terminals in each of the receiving chambers When a plurality of the connection terminals and a plurality of the accommodating chamber terminals in one of the accommodating chambers are connected to each other, the power supply device can provide power to the wafer testing device. The wafer testing system according to claim 3, wherein each of the environmental control equipment further includes a plurality of lifting devices, and each of the accommodation chambers is provided with one lifting device; each of the lifting devices can be The central control device controls to connect or separate the plurality of connection terminals and the plurality of the accommodation chamber terminals of the wafer testing device provided in the accommodation chamber. The wafer test system according to claim 2, wherein the power supply member of the wafer test device is a receiving antenna, and the power supply member of the device body is a transmitting antenna, and the receiving antenna can be coupled with the transmitting antenna , And the chip testing device can receive the power transmitted by the power supply device in a wireless manner through the receiving antenna. The wafer test system according to claim 2, wherein the wafer test device further includes a plurality of first data transmission terminals, the plurality of first data transmission terminals are provided on the circuit board, and the device body A plurality of second data transmission terminals are arranged in each of the accommodating chambers; the plurality of first data transmission terminals are used to connect with a plurality of second data transmission terminals to transmit data to each other. The chip testing system according to claim 2, wherein the chip testing device further includes at least one first data transmission antenna, and the first data transmission antenna is used to communicate with at least one second data transmission antenna provided in the environmental control device 2. The data transmission antenna transmits data wirelessly. The chip testing system according to claim 2, wherein each of the test modules completes the predetermined test procedure for the chips on the plurality of electrical connection sockets connected to them, the test module The test result data and test parameter data of each of the chips will be written into the chip, so that the test result data and test parameter data are stored in each of the chips. The wafer testing system according to claim 2, wherein each of the environmental control equipment further includes a plurality of covers and at least one air extraction device; each of the containing chambers is provided with one of the covers; The wafer testing device is arranged in one of the accommodating chambers, and when the wafer testing device is powered, the cover in the accommodating chamber can be arranged on the circuit board, and the cover A closed space can be formed together with the circuit board, a plurality of the electrical connection seats are correspondingly located in the closed space, and the central control device can control the action of the extractor device to move the closed space The air is drawn outward. The wafer test system according to claim 9, wherein each of the temperature adjusting devices includes a contact structure, and when each of the temperature adjusting devices is controlled by the central control device to operate, the temperature of the contact structure will increase or Lowered to the predetermined temperature; when the cover is set on the circuit board of the wafer testing device provided in the containing chamber, and the air extraction device is controlled by the central control device When the gas in the enclosed space is drawn out, the contact structure of the temperature adjusting device will abut against the multiple wafers on the multiple electrical connection seats of the wafer testing device. One side. The wafer testing system according to claim 1, wherein each of the environmental control equipment further includes a plurality of limit devices, and each of the accommodation chambers is provided with one limit device, and each of the limit devices can It is controlled by the central control device and connected with the wafer testing device arranged in the containing chamber, so as to limit the movement range of the wafer testing device in the containing chamber. The wafer test system according to claim 1, wherein the wafer test system further includes a pre-test device connected to the central control device, and the pre-test device includes at least one electrical connector, so The electrical connector of the pre-test equipment is used to carry at least one of the wafers, and the pre-test equipment can perform a short circuit test and a leakage current test on the wafers it carries; the central control device can control the Transfer equipment, so that the wafer mounting equipment first installs each wafer on the electrical connection seat of the pre-test equipment before mounting each wafer on the wafer testing device to perform The short circuit test and the leakage current test. The wafer test system according to claim 1, wherein the wafer test system further includes a final test device, the final test device is connected to the central control device, and the final test device includes at least one electrical connector, so The electrical connection seat of the final test equipment is used to carry at least one of the wafers, and the final test equipment can perform a short circuit test and a leakage current test on the wafers it carries; the central control device can control the transfer Equipment, after unloading each of the wafers from the wafer testing device, first install each of the wafers on the electrical connection seat of the final test equipment to perform the short circuit test and the leakage test on the wafer Current test.

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