CN112798922B

CN112798922B - Environment control equipment and chip test system

Info

Publication number: CN112798922B
Application number: CN201911106204.2A
Authority: CN
Inventors: 蔡振龙; 基因·罗森塔尔
Original assignee: First Inspection Co ltd
Current assignee: First Inspection Co ltd
Priority date: 2019-11-13
Filing date: 2019-11-13
Publication date: 2024-09-10
Anticipated expiration: 2039-11-13
Also published as: CN112798922A

Abstract

The invention discloses an environment control device and a chip test system. The equipment body of the environment control equipment is provided with a plurality of accommodating chambers, and each accommodating chamber is provided with a temperature regulating device. Each temperature regulating device comprises a temperature regulator, a contact structure, a frame body and an elastic annular sealing piece. When the chip testing device bearing a plurality of chips is arranged in the accommodating chamber and the contact structure is contacted with one side of the chips, the elastic annular sealing piece correspondingly presses the chip testing device, and a closed space is formed between the chip testing device and the contact structure. The air extractor connected with the environment control equipment can extract the air in the enclosed space outwards, and the temperature regulator can correspondingly regulate the temperature of the contact structure, so that each chip is subjected to a preset test program by the chip test device in a specific temperature environment.

Description

Environment control equipment and chip test system

Technical Field

The present invention relates to an environmental control apparatus and a chip test system, and more particularly, to an environmental control apparatus and a chip test system suitable for testing semiconductor devices (e.g., memories).

Background

The existing memory test device is designed to detect a large amount of memory, and when the existing memory test device is operated, a large amount of power must be consumed, and correspondingly, a high amount of electricity fee is generated. Thus, it is necessary for the relevant developer to avoid sending small amounts of memory into the memory test equipment for testing during development unless it is not necessary.

In addition, in the existing memory test device, only the same predetermined stroke test can be performed on the same batch of memories in the same period, so if two batches of memories need to be tested with different predetermined strokes, one batch of memories must wait for the other batch of memories to finish all the tests, and then the memories can be tested in the memory test device, thus the overall test time of the memories is long.

Disclosure of Invention

The embodiment of the invention provides an environment control device and a chip test system, which are used for improving the existing memory test device, wherein in the same time period, only a single predetermined test can be performed on a batch of memories, and a relevant manufacturer cannot perform different predetermined tests on different memories in the same time period.

One embodiment of the present invention is an environmental control apparatus for performing a predetermined test procedure on a plurality of chips disposed on a chip test device in an environment of a predetermined high temperature or a predetermined low temperature, the chip test device including at least a first power supply member, the environmental control apparatus being connected to an air extraction device, the environmental control apparatus comprising: an apparatus body including a plurality of accommodating chambers; at least one second power supply component is arranged in each accommodating chamber, and the equipment body is connected with a power supply equipment; when the chip testing device is arranged in one of the accommodating chambers, the power supply equipment can provide power for the chip testing device through the first power supply component and the second power supply component; an environmental state control device connected with the equipment body; a plurality of temperature adjusting devices connected to the environmental state control device, one temperature adjusting device being provided in each of the accommodating chambers, each of the temperature adjusting devices comprising: at least one temperature regulator; at least one contact structure having a contact surface for contacting a side surface of a plurality of chips carried by the chip testing device; the temperature regulator can be controlled to raise the temperature of the contact structure to a predetermined high temperature, and the temperature regulator can be controlled to lower the temperature of the contact structure to a predetermined low temperature; the frame body is arranged around the contact structure and is provided with a ring pressing surface, and the ring pressing surface is flush with the contact surface or the contact surface is higher than the ring pressing surface; an elastic annular sealing element arranged on the annular pressing surface; when the contact surface is contacted with one side surface of a plurality of chips carried by the chip testing device, the elastic annular sealing element correspondingly presses the chip testing device, and a closed space is correspondingly formed between the contact structure and the chip testing device; the air extracting device can be controlled to extract air in the enclosed space outwards; wherein each temperature regulating device can be controlled by the environmental state control device to operate independently of the other temperature regulating devices; when the chip testing device is arranged in one of the accommodating chambers, the contact structure is abutted against one side surface of a plurality of chips borne by the chip testing device, the chip testing device is powered, the contact structure reaches a preset high temperature or a preset low temperature, and air in the closed space is pumped out by the air pumping device, the chip testing device can be controlled to carry out a preset testing program on the plurality of chips borne by the chip testing device.

Preferably, the environmental control equipment further comprises a plurality of limiting devices, wherein each of the accommodating chambers is provided with one limiting device, and each limiting device is connected with the environmental state control device; each limiting device can be controlled by the environment state control device and is connected with the chip testing device arranged in the accommodating chamber, so that the movable range of the chip testing device in the accommodating chamber is limited.

Preferably, the environment control device further comprises a plurality of lifting devices, wherein one lifting device is arranged in each accommodating chamber, and each lifting device is connected with the environment state control device; each lifting device can be controlled by the environment state control device so that the chip testing device arranged in the accommodating chamber moves in the accommodating chamber.

Preferably, the environmental control apparatus further comprises a chip test device, the chip test device comprising: at least one circuit board, two opposite sides of which are respectively defined as a first side and a second side; the circuit board is provided with a plurality of positioning holes and a plurality of circuit board locking holes, each positioning hole does not penetrate through the circuit board, and each circuit board locking hole penetrates through the circuit board; the fixing assembly comprises a first fixing member and a second fixing member, the first fixing member is fixedly arranged on the first side surface, the second fixing member is fixedly arranged on the second side surface, the first fixing member is provided with a plurality of first lock holes, the second fixing member is provided with a plurality of second lock holes, and the plurality of first lock holes, the plurality of circuit board lock holes and the plurality of second lock holes are correspondingly arranged; the locking parts are locked in the first lock holes, the circuit board lock holes and the second lock holes, the circuit board is fixed between the first fixing component and the second fixing component; a plurality of electric connection seats, each electric connection seat is provided with an electric connection seat body; one side of each electric connection seat body is used for bearing a chip, the other side of the electric connection seat body is provided with at least two positioning pieces, each positioning piece is mutually clamped with a plurality of positioning holes, and each electric connection seat is arranged on the first side face of the circuit board; the first fixing component comprises a plurality of propping structures, the plurality of propping structures correspondingly prop against a part of the plurality of electric connecting seats, each electric connecting seat is propped by the first fixing component and is fixed on the first side surface of the electric connecting seat, the first fixing component comprises a plurality of through holes, and a part of each electric connecting seat correspondingly exposes out of each through hole; the control unit is arranged on the second side surface of the circuit board and comprises a plurality of test modules, and each test module is connected with a part of the electric connecting seat; the second fixing member is provided with a plurality of avoidance holes, and a part of the plurality of test modules penetrate through the plurality of avoidance holes; and

A first power supply member connected to the circuit board; the chip testing device must be connected to the power supply device through the first power supply component to obtain the power required by each testing module during operation.

Preferably, each test module comprises: a graphics generator (Pattern Generator, PG), a component power supply module (Device Power Supplies, DPS), and a Driver circuit (Driver); the chip is a memory, and the predetermined test program comprises: at least one of a read test, a write test, and an electrical test; the plurality of electric connection base areas are a plurality of electric connection base groups, and each electric connection base group comprises at least one electric connection base; the plurality of test modules are connected with the electric connection seats of the plurality of electric connection seat groups, and each test module is connected with all electric connection seats in the corresponding electric connection seat groups.

Preferably, the first fixing member further includes a fixing body, each pressing structure is detachably fixed on the fixing body, each fixing body has a plurality of group accommodating holes, and each group accommodating hole is used for accommodating a plurality of electrical connection seats in the same electrical connection seat group.

Preferably, the circuit board has a plurality of first contact structures on the second side, each test module has at least one second contact structure, and the second contact structure of each test module can be detachably contacted with one of the first contact structures.

Preferably, the first power supply member includes a plurality of connection terminals, the plurality of connection terminals are disposed on a first side surface of the circuit board, and the plurality of connection terminals are exposed from the first fixing member; the second power supply member in each of the accommodation chambers includes a plurality of accommodation chamber terminals; the plurality of connecting terminals are used for connecting with the plurality of accommodating chamber terminals in each accommodating chamber; when the plurality of connection terminals are connected with the plurality of housing terminals in one of the housings, the power supply device can supply power to the chip testing device.

Preferably, the first power supply member is a receiving antenna, the second power supply member is a transmitting antenna, the receiving antenna is used for being mutually coupled with the transmitting antenna, and the chip testing device can receive the power transmitted by the power supply device in a wireless mode through the receiving antenna.

Preferably, the chip testing device further comprises at least one first data transmission terminal, wherein the first data transmission terminal is arranged on the circuit board, and the first data transmission terminal is exposed out of the first fixing component; each accommodating chamber also comprises at least one second data transmission terminal; the first data transmission terminals are used for contacting with the second data transmission terminals in the accommodating chambers to mutually transmit data.

Preferably, the chip testing device further comprises at least one first data transmission antenna; the equipment body also comprises at least one second data transmission antenna; the first data transmission antenna is used for wirelessly transmitting data with the second data transmission antenna.

Preferably, after the predetermined test procedure is completed on the chips on the plurality of electrical connection seats connected to the test module, the test module writes the test result data and the test parameter data of each chip into the chip, so that the test result data and the test parameter data are stored in each chip.

Preferably, each electrical connector comprises: the base body is provided with a top wall and a ring side wall, the top wall is provided with an opening, one end of the ring side wall is connected with the periphery of the top wall, the other end of the ring side wall is propped against the circuit board, and the top wall, the ring side wall and the circuit board jointly form a containing groove; the two opposite side surfaces of the top wall are defined as an outer side surface and an inner side surface, and the inner side surface is positioned in the accommodating groove; the side of the top wall opposite to the circuit board is defined as an outer side surface, and the outer side surface is flush with a propped top surface of the first fixing member opposite to the circuit board; the supporting structure is propped against the circuit board and is positioned in the accommodating groove, and the supporting structure comprises a plurality of positioning holes, and each positioning hole is provided with a positioning piece; the lifting structure is arranged in the accommodating groove and is provided with a base part and a bearing part, the base part is positioned in the accommodating groove, the base part extends to one side to form the bearing part, and at least one part of the bearing part is positioned in the opening; the bearing part extends to one side far away from the base part to form a plurality of limiting parts, at least one part of the limiting parts penetrates out of the open hole, and the limiting parts and the bearing part jointly form a chip accommodating groove for accommodating a chip; the lifting structure is also provided with a plurality of connecting holes which penetrate through the base part and the bearing part; the elastic components are arranged in the accommodating grooves, one end of each elastic component is fixed on the lifting structure, the other end of each elastic component is fixed on the supporting structure, the elastic restoring force generated by the compression of the plurality of elastic components enables the base to be propped against the inner side surface of the top wall, and a gap is formed between the lifting structure and the supporting structure; one end of each probe assembly is fixedly arranged on the supporting structure, the other end of each probe assembly is propped against the electric contact structure of the circuit board, and the other ends of the probe assemblies penetrate through the connecting holes; when the chip accommodating groove is provided with a chip and the limiting part is not pressed by the contact structure, the probe assemblies in the plurality of connecting holes are not connected with the plurality of contact parts of the chip, and part of the lifting structure protrudes out of the outer side surface of the top wall; when the chip accommodating groove is provided with a chip, the limiting part is pressed by the contact structure to shrink inwards towards the base body, and the elastic annular sealing piece and the propping surface of the first fixing member are mutually propped, the plurality of probe assemblies are propped against the electric contact structure of the circuit board.

Preferably, at least one air extraction gap is formed between the frame body of each temperature adjusting device and the contact structure, the frame body is provided with at least one air extraction hole, the air extraction hole is communicated with the air extraction gap, and the air extraction device can extract the air in the closed space outwards through the air extraction hole and the air extraction gap.

One embodiment of the present disclosure is a chip test system comprising: the chip testing device is used for bearing a plurality of chips and comprises at least one first power supply component; a central control device, which comprises an environment state control device; at least one environment control device, the environment control device is connected with an air extracting device, the environment control device comprises: an apparatus body including a plurality of accommodating chambers; at least one second power supply component is arranged in each accommodating chamber, and the equipment body is connected with a power supply equipment; when the chip testing device is arranged in one of the accommodating chambers, the power supply equipment can provide power for the chip testing device through the first power supply component and the second power supply component; a plurality of temperature adjusting devices connected to the environmental state control device, one temperature adjusting device being provided in each of the accommodating chambers, each of the temperature adjusting devices comprising: at least one temperature regulator; at least one contact structure having a contact surface for contacting a side surface of a plurality of chips carried by the chip testing device; the temperature regulator can be controlled to raise the temperature of the contact structure to a predetermined high temperature, and the temperature regulator can be controlled to lower the temperature of the contact structure to a predetermined low temperature; the frame body is arranged around the contact structure and is provided with a ring pressing surface, and the ring pressing surface is flush with the contact surface or the contact surface is higher than the ring pressing surface; an elastic annular sealing element arranged on the annular pressing surface; when the contact surface is contacted with one side surface of a plurality of chips carried by the chip testing device, the elastic annular sealing element correspondingly presses the chip testing device, and a closed space is correspondingly formed between the contact structure and the chip testing device; the air extracting device can be controlled to extract air in the enclosed space outwards; wherein each temperature regulating device can be controlled by the environmental state control device to operate independently of the other temperature regulating devices; when the chip testing device is arranged in one of the accommodating chambers, the contact structure is abutted against one side surface of a plurality of chips borne by the chip testing device, the chip testing device is powered, the contact structure reaches a preset high temperature or a preset low temperature, and air in the closed space is pumped out by the air pumping device, the chip testing device can be controlled to carry out a preset testing program on the plurality of chips borne by the chip testing device.

In summary, the environment control device and the chip testing system disclosed in the embodiments of the present invention provide a plurality of chambers, each of which can accommodate a chip testing device carrying a plurality of chips (e.g. memories), and the temperature of each of the chambers is adjusted by a temperature adjusting device in the chamber, so that the chip testing devices disposed in different chambers can simultaneously perform testing in different temperature environments.

Drawings

Fig. 1 is a schematic diagram of a chip testing system according to the present disclosure.

Fig. 2 is a block diagram of a chip testing system according to the present disclosure.

Fig. 3 is a schematic diagram of a chip testing apparatus according to the present disclosure.

Fig. 4 is a partially exploded schematic view of a chip testing apparatus according to the present disclosure.

FIG. 5 is another partially exploded view of the chip testing apparatus of the present disclosure.

Fig. 6 is an enlarged schematic view of a portion of a chip testing apparatus according to the present invention.

Fig. 7 is an exploded schematic view of the pressing structure and the fixing body of the chip testing device disclosed by the invention.

Fig. 8 is an exploded view of an electrical connection base and a circuit board of the chip testing device disclosed by the invention.

Fig. 9 is an exploded schematic view of a test module, a circuit board and a second fixing member of the chip test device disclosed by the invention.

Fig. 10 is a block diagram of a chip testing apparatus according to the present disclosure.

Fig. 11 is a schematic diagram of an electrical connection socket of the chip testing device disclosed by the invention.

Fig. 12 is a schematic exploded view of a cross section of an electrical connection socket of a chip testing apparatus according to the present invention.

Fig. 13 is a schematic cross-sectional view of the electrical connection socket of the chip testing apparatus disclosed in the present invention without a chip.

Fig. 14 is a schematic cross-sectional view of an electrical connection pad of a chip testing apparatus according to the present invention provided with a chip.

Fig. 15 is an exploded view of a pressing structure and a fixing body of another embodiment of a chip testing device according to the present disclosure.

Fig. 16 is a schematic view of an electrical connection socket of another embodiment of a chip testing apparatus according to the present disclosure.

FIG. 17 is a schematic diagram of an environmental control apparatus of the chip test system disclosed in the present invention.

Fig. 18 is a block diagram of a device and a central control device included in an environmental control apparatus of a chip test system according to the present invention.

Fig. 19 is a schematic diagram of a temperature adjusting device of a chip testing system according to the present disclosure.

Fig. 20 is a schematic partial cross-sectional view of a chip testing apparatus of the chip testing system disclosed in the present invention.

Fig. 21 is a schematic cross-sectional view of a temperature adjusting device of a chip testing system according to the present invention disposed on the chip testing device.

Fig. 22 is an enlarged partial schematic view of fig. 19.

Fig. 23 is an enlarged view of a portion of a single electrical connection pad pressed by a contact structure.

Fig. 24 is a flowchart of a first embodiment of a chip testing method used by the chip testing system of the present invention to test a plurality of chips.

Fig. 25 is a flowchart of a second embodiment of a chip testing method used by the chip testing system of the present invention to test a plurality of chips.

Fig. 26 is a flowchart of a third embodiment of a chip testing method used by the chip testing system of the present invention to test a plurality of chips.

Fig. 27 is a flowchart of a chip testing method used by the chip testing system for testing a plurality of chips according to a fourth embodiment of the present invention.

Fig. 28 is a flowchart of a fifth embodiment of a chip testing method used by the chip testing system for testing a plurality of chips according to the present invention.

Fig. 29 is a flowchart of a chip testing method used by the chip testing system for testing a plurality of chips according to a sixth embodiment of the present invention.

Fig. 30 is a flowchart of a seventh embodiment of a chip testing method used by the chip testing system for testing a plurality of chips according to the present invention.

Fig. 31 is a flowchart of an eighth embodiment of a chip testing method used by the chip testing system for testing a plurality of chips according to the present invention.

Detailed Description

Referring to fig. 1 to 5, fig. 1 is a schematic diagram of a chip testing system according to the present invention, fig. 2 is a block schematic diagram of a chip testing system according to the present invention, fig. 3 is a schematic diagram of a chip testing device according to the present invention, and fig. 4 and 5 are partial exploded schematic diagrams of the chip testing device according to the present invention. The chip test system E is used for testing a plurality of chips C. The chip test system E includes: a central control device E1, a chip mounting equipment E2, at least a chip testing device 1, a plurality of environment control equipment E3, a transfer equipment E4 and a classification equipment E5.

The central control device E1 is connected with the chip mounting equipment E2, a plurality of environment control equipment E3, a transfer equipment E4 and a classification equipment E5, and the central control device E1 can control the operation of each equipment; the central control device E1 is not limited to this, and may be, for example, a server, various computer devices, or the like. In practical applications, the central control device E1 may include a plurality of environmental status control devices (such as various processors, computers, etc.), and the device body E31 (fig. 17) of each environmental control device E3 may be correspondingly provided with one environmental status control device, that is, each environmental control device E3 may include one environmental status control device. The chip mounting apparatus E2 may include a mechanical arm (not shown), which can be controlled by the central control device E1 to take out the plurality of chips C on the tray (tray) one by one and then place the chips C on the plurality of electrical connection seats 2 of the chip testing device 1 one by one.

The chip testing apparatus 1 is used for carrying a plurality of chips C, and the chip testing apparatus 1 can be carried by a transferring device E4 to be transferred between a plurality of workstations (e.g. a chip mounting device E2, a plurality of environmental control devices E3, a transferring device E4 and a sorting device E5).

As shown in fig. 3 to 5, the chip test apparatus 1 includes: a circuit board 10, a fixing component 11, a plurality of electrical connection bases 2, a control unit 3 and at least a first power supply member 4. Opposite sides of the circuit board 10 are respectively defined as a first side 101 and a second side 102 (as shown in fig. 9). The plurality of electrical connection sockets 2 are fixedly disposed on the first side 101 of the circuit board 10, and each electrical connection socket 2 is used for carrying one chip C. The form of the electrical connection base 2 may be varied according to different chips C, and is not limited herein.

The fixing assembly 11 includes a first fixing member 111 and a second fixing member 112. The first fixing member 111 is disposed on the first side 101, and the second fixing member 112 is fixedly disposed on the second side 102. The first fixing member 111 has a plurality of first locking holes 1111, the second fixing member 112 has a plurality of second locking holes 1121, and the circuit board 10 has a plurality of circuit board locking holes 103, each of the first locking holes 1111 is provided through the first fixing member 111, each of the second locking holes 1121 is provided through the second fixing member 112, each of the circuit board locking holes 103 is provided through the circuit board 10, and the plurality of first locking holes 1111, the plurality of circuit board locking holes 103, and the plurality of second locking holes 1121 are provided correspondingly. In practical applications, the number, shape and distribution of the first locking holes 1111, the circuit board locking holes 103 and the second locking holes 1121 may be changed according to needs, and only one exemplary embodiment is shown in the drawings.

A plurality of locking members (not shown), such as screws, are locked to the plurality of first locking holes 1111, the plurality of circuit board locking holes 103, and the plurality of second locking holes 1121, and the circuit board 10 is fixed between the first fixing member 111 and the second fixing member 112. That is, the circuit board 10 is clamped between the first fixing member 111 and the second fixing member 112, and the overall structural strength of the circuit board 10 is improved by the arrangement of the first fixing member 111 and the second fixing member 112. In practical applications, the first fixing member 111 and the second fixing member 112 may be made of a high-hardness material such as stainless steel; the circuit board 10 may have only each of the circuit board locking holes 103 provided through the circuit board 10, and the circuit board 10 has no other holes penetrating through the circuit board 10.

Specifically, in practical applications, each first locking hole 1111 may not be disposed through the first fixing member 111, and each first locking hole 1111 may be a blind hole, or a part of the first locking holes 1111 may be through holes and another part of the first locking holes 1111 may be blind holes; in the case that the first locking hole 1111 is a blind hole, the corresponding second locking hole 1121 is a through hole penetrating the second fixing member 112. In the case where the first locking hole 1111 is a through hole, at least a part of the second locking hole 1121 may be a blind hole.

Referring to fig. 4,6 and 7 together, fig. 6 is a schematic enlarged view of a portion of a chip testing device according to the present disclosure, and fig. 7 is an exploded schematic view of a pressing structure and a fixing body of the chip testing device according to the present disclosure. In practical applications, the first fixing member 111 may include a plurality of pressing structures 1112 and a fixing body 1114, each pressing structure 1112 and the fixing body 1114 are independent members, and each pressing structure 1112 is detachably fixed on the fixing body 1114. Each pressing structure 1112 is substantially in a lattice shape, and a plurality of perforations 1113 are formed in each pressing structure 1112.

When the first fixing member 111 is fixed to the first side 101 of the circuit board 10, the plurality of pressing structures 1112 correspondingly press against a portion of the electrical connector body 21 of the plurality of electrical connectors 2, and a portion of each electrical connector 2 correspondingly exposes out of each through hole 1113. That is, the first fixing member 111 is used to cooperate with the second fixing member 112 to clamp the circuit board 10, and the first fixing member 111 is also used to fix the plurality of electrical connection pads 2 disposed on the first side 101 of the circuit board 10 to the first side 101 of the circuit board 10.

The fixing body 1114 includes a plurality of group receiving holes 1115, and each group receiving hole 1115 is disposed through the fixing body 1114. Each group accommodating hole 1115 is used for accommodating a plurality of electrical connection seats 2. The fixing body 1114 further includes a plurality of auxiliary fixing portions 1116, and each auxiliary fixing portion 1116 is formed by forming a sidewall of each group accommodating hole 1115 to extend toward the center of the group accommodating hole 1115. When the fixing body 1114 is fixed to the circuit board 10, the height of each auxiliary fixing portion 1116 with respect to the circuit board 10 is smaller than the depth of each group accommodating hole 1115.

Each pressing structure 1112 and the auxiliary fixing portion 1116 may have a plurality of corresponding locking holes 11121, 1117, respectively, and each pressing structure 1112 may be the auxiliary fixing portion 1116 locked in each group accommodating hole 1115 by a plurality of locking members (not shown, for example, screws). When the pressing structure 1112 and the auxiliary fixing portion 1116 are locked, the pressing structure 1112 presses the pressing portions 213 (shown in fig. 7, described later) of the electrical connector bodies 21 of the plurality of electrical connectors 2 located in the group accommodating hole 1115, and a portion of the plurality of electrical connectors 2 is exposed through the plurality of through holes 1113 of the pressing structure 1112. As shown in fig. 6, in the present embodiment, when the first fixing member 111 is fixed to the circuit board 10, the side of the pressing structure 1112 opposite to the circuit board 10 is lower than the side of the fixing body 1114 opposite to the circuit board 10, i.e. the height from the side of the pressing structure 1112 opposite to the circuit board 10 to the side of the circuit board 10 where the electrical connection socket 2 is provided is lower than the height from the side of the fixing body 1114 opposite to the circuit board 10 to the side of the circuit board 10 where the electrical connection socket 2 is provided, but not limited thereto; in various embodiments, the side of the pressing structure 1112 opposite to the circuit board 10 may be flush with the side of the fixing body 1114 opposite to the circuit board 10.

As described above, the first fixing member 111 is locked to the first side 101 of the circuit board 10 by a plurality of locking members, and the plurality of pressing structures 1112 of the first fixing member 111 correspondingly press a portion of each electrical connection base 2, so that each electrical connection base 2 can be directly fixed to the circuit board 10 by the first fixing member 111 in a pressing manner without using screws.

Referring to fig. 6 to 8, fig. 8 is an exploded schematic view of the electrical connection base and the circuit board of the chip testing device according to the present invention. On the first side 101 of the circuit board 10, a plurality of sets of electrical contact structures 1011 are formed (only two sets of electrical contact structures 1011 are shown in fig. 8, but the number of electrical contact structures 1011 corresponds to the number of electrical connection pads 2). Each set of electrical contact structures 1011 includes a plurality of contact pads 10111 (e.g., metal pads). When each electrical connection socket 2 is pressed by the pressing structure 1112 and is fixedly disposed on the first side 101 of the circuit board 10, one end of a plurality of probe assemblies 20 (described in detail below) of the electrical connection socket 2 is correspondingly pressed against a plurality of contact pads 10111 included in a set of electrical contact structures 1011, so that, when the chip testing apparatus 1 is powered, the plurality of probe assemblies 20 of the electrical connection socket 2 can be electrically connected with electronic components disposed on the circuit board 10 through the plurality of contact pads 10111. Regarding the number, arrangement, and placement of the electrical contact structures 1011, the number, shape, arrangement, etc. of the contact pads 10111 of each set of electrical contact structures 1011 may vary according to requirements, and only one exemplary embodiment is shown.

It should be noted that, the above description of the present embodiment takes the case that the plurality of pressing structures 1112 and the fixing body 1114 are independent members, but in practical application, the pressing structures 1112 and the fixing body 1114 may be integrally formed, that is, the first fixing member 111 is integrally formed in a fence shape.

In practical applications, each contact pad 10111 may be formed substantially flat on the first side 101 of the circuit board 10, and for convenience of personnel or machinery, each electrical connection seat 2 is correctly disposed on each set of electrical contact structures 1011, the first side 101 of the circuit board 10 may further be concavely formed with at least two positioning holes 104 around each set of electrical contact structures 1011, and each positioning hole 104 is not disposed through the circuit board 10. In contrast, each electrical connection base 2 is configured to abut against one side of the first side 101 of the circuit board 10, and may have a positioning member 25 correspondingly, and each positioning member 25 may be engaged with the positioning hole 104, so that, by matching the positioning member 25 with the positioning hole 104, a person or a machine can easily and correctly set the electrical connection base 2 on each set of electrical contact structures 1011. In practical applications, the positioning member 25 and the electrical connection seat 2 may be two independent components, or the positioning member 25 may be integrally formed with the base structure 231 of the electrical connection seat 2.

As described above, since each electrical connection seat 2 is fixedly disposed on the first side 101 of the circuit board 10 only by the pressing of the pressing structure 1112, when assembling the electrical connection seat 2, the first fixing member 111, the second fixing member 112 and the circuit board 10, it is necessary to dispose a plurality of electrical connection seats 2 on the first side 101 of the circuit board 10, and then lock the first fixing member 111 on the first side 101 of the circuit board 10, during this process, each electrical connection seat 2 is limited by the positioning piece 25 and the positioning hole 104, each electrical connection seat 2 is not easy to move relative to the circuit board 10, and the related personnel or machinery can easily lock the first fixing member 111 on the first side 101 of the circuit board 10. The number of the positioning elements 25 disposed between the single electrical connector 2 and the circuit board 10 is not limited to two, and the number of the positioning elements 25 and the positioning holes 104 can be changed according to the requirement.

In summary, in the chip testing apparatus 1 of the present invention, the first fixing member 111 and the second fixing member 112 are matched with the plurality of locking members to clamp and fix the plurality of electrical connection sockets 2 on the first side 101 of the circuit board 10, so that the electrical connection sockets 2 and the circuit board 10 can be not locked with each other by the locking members, and the number of through holes of the circuit board 10 can be greatly reduced.

Referring to fig. 5 and fig. 9 together, fig. 9 is an exploded schematic view of a test module, a circuit board and a second fixing member of the chip test device according to the present invention. The control unit 3 is arranged on the second side 102 of the circuit board 10. The control unit 3 includes a plurality of test modules 30, and each test module 30 is fixedly disposed on the second side 102 of the circuit board 10. The second fixing member 112 has a plurality of escape holes 1122. When the second fixing member 112 is fixedly disposed on the second side 102 of the circuit board 10, a portion of each test module 30 can be correspondingly disposed through the corresponding avoidance hole 1122.

In practical applications, the second side 102 of the circuit board 10 may have a plurality of first contact structures 1021. Each test module 30 may have a test module body 32 and two second contact structures 33, the test module body 32 is internally provided with electronic components for testing the chip C disposed on the electrical connection base 2, the second contact structures 33 are exposed at one side of the test module body 32, and the second contact structures 33 of each test module body 32 are used for contacting with the first contact structures 1021 of the circuit board 10. When each test module 30 is fixedly disposed on the second side 102 of the circuit board 10, the second contact structure 33 of each test module 30 passes through the corresponding avoidance hole 1122 to contact with the first contact structure 1021 of the circuit board 10. The number of the second contact structures 33 included in each test module 30 is not limited to two, and the number of the second contact structures 33 may be changed according to the requirement.

When the second contact structure 33 of each test module 30 contacts the first contact structure 1021 of the circuit board 10, the associated electronic component within each test module 30 can be connected to the associated electronic component provided on the circuit board 10. In a specific application, the first contact structure 1021 and the second contact structure 33 may be, for example, board-to-board connectors, which may be, for example, pogo pins or reeds, but not limited thereto. The number of the second contact structures 33 of each test module 30 is not limited to two, and may be changed according to the different patterns of the second contact structures 33.

Through the design of the first contact structure 1021 and the second contact structure 33, each test module 30 can be detachably and fixedly arranged on the second side 102 of the circuit board 10, and through the design that each test module 30 is detachably arranged on the circuit board 10, a user can replace the test module 30 according to the requirement, and related maintenance personnel can easily disassemble, assemble and maintain the specific test module 30. As shown in fig. 5 and 9, in practical application, the test module body 32 may have two auxiliary fixing structures 321, each auxiliary fixing structure 321 may have a plurality of fixing holes 3211, and the second fixing member 112 may have a plurality of corresponding fixing holes 1123. Each of the test module bodies 32 may be detachably fixed to the second fixing member 112 by a plurality of fasteners (e.g. screws) that cooperate with the plurality of fixing holes 3211 and the plurality of fixing holes 1123. In practical applications, the auxiliary fixing structure 321 may be integrally formed with the test module body 32, or the auxiliary fixing structure 321 may be a member (e.g., angle-steel-like structure) independent of the test module body 32. Of course, the test module body 32 is not limited to the method of locking the test module body 32 to the second fixing member 112 by using a screw or other member, and any method of detachably assembling the test module body 32 to the second fixing member 112 falls within the scope of the present embodiment.

Referring to fig. 3 again, in practical application, the plurality of electrical connection pads 2 may be divided into a plurality of electrical connection pad groups, each of the electrical connection pad groups includes at least one electrical connection pad 2, and each of the test modules 30 is correspondingly connected to all of the electrical connection pads 2 of one electrical connection pad group. For example, in fig. 3 of the present embodiment, 72 electrical connection seats 2 are disposed on the circuit board 10, which may be divided into 6 groups of electrical connection seats, each group of electrical connection seats includes 12 electrical connection seats 2, and 12 electrical connection seats 2 in each group of electrical connection seats are located in the same group accommodating hole 1115, and 12 electrical connection seats 2 in each group of electrical connection seats are connected to the same test module 30; as shown in fig. 5, the circuit board 10 is provided with 6 test modules 30. Of course, the number of the electrical connection sockets 2 and the number of the electrical connection socket groups corresponding to the number of the electrical connection socket groups may be changed according to the requirements.

As shown in fig. 6, it is specifically described that by the design of the pressing structure 1112 and the fixing body 1114, each electrical connection socket 2 is directly fixed on the circuit board 10 in a pressing manner, and each group of electrical connection socket groups is correspondingly pressed by one pressing structure 1112, so that when any electrical connection socket 2 fails, the related personnel only need to remove the screw between the pressing structure 1112 and the fixing body 1114 corresponding to the electrical connection socket 2, and then the electrical connection socket 2 can be directly removed and replaced. That is, by the design of the pressing structure 1112 and the fixing body 1114, the maintenance personnel or the machine can easily and quickly repair, replace and install the specific electrical connection base 2.

When each test module 30 is powered, a predetermined test procedure can be performed on a plurality of chips C on a plurality of electrical connection bases 2 to which it is connected, for example, the chips C may be various memories (for example NAND FLASH, etc.), and each test module 30 can perform at least one of a read test, a write test and an electrical test on each memory. In an embodiment in which each test module 30 is used to test memory, the test module body 32 of each test module 30 may include a graphics generator (Pattern Generator, PG), a parameter measurement unit (PARAMETRIC MEASUREMENT UNIT, PMU), a component power supply module (Device Power Supplies, DPS), and a Driver circuit (Driver).

By the design that the plurality of electrical connection seats 2 arranged on the circuit board 10 are respectively connected to the plurality of different test modules 30, the test modules 30 and the plurality of chips C on the electrical connection seats 2 connected with the test modules can transfer signals between each other more quickly and are not easy to attenuate. More specifically, if the circuit board 10 provided with 72 electrical connection sockets 2 is connected to only one signal input source, when a signal sent from the signal input source is transmitted from one side of the circuit board 10 to the other side of the circuit board 10, the signal will be significantly attenuated, which may cause a problem of inaccurate chip test results.

In practical applications, all the electrical connection sockets 2 in each electrical connection socket group may be connected in parallel, and all the electrical connection sockets 2 in the same electrical connection socket group that are connected in parallel are connected to the same test module 30; in other words, all the electrical connection pads 2 to which the respective test modules 30 are connected in parallel. In addition, any one of the electrical connection pads 2 in each electrical connection pad group is not connected to any one of the electrical connection pads 2 in the other electrical connection pad groups. For example, assume that the circuit board 10 is provided with four electrical connection sockets 2, respectively: z1, Z2, Q1, Q2, four electrical connection sockets 2 are partitioned into two groups of electrical connection sockets, a first group of electrical connection sockets comprising Z1, Z2 and a second group of electrical connection sockets comprising Q1, Q2, then Z1 and Z2 are connected in parallel, Q1 and Q2 are connected in parallel, and Z1 is not connected with Q1 (whether in parallel or in series), Z1 is not connected with Q2 (whether in parallel or in series), Z2 is not connected with Q1 (whether in parallel or in series), and Z2 is not connected with Q2 (whether in parallel or in series).

By the design that the plurality of electrical connection sockets 2 of different electrical connection socket groups are not mutually connected, when the chip testing device 1 fails, related maintenance personnel can quickly find out the damaged electrical connection socket 2 by testing each electrical connection socket group one by one, and related maintenance personnel can replace only the damaged electrical connection socket 2, components of the electrical connection socket 2, the electrical connection sockets 2 of the same group or the test modules 30, without replacing all the electrical connection sockets 2 or all the test modules 30 of the whole circuit board 10.

In practical application, as shown in fig. 5, the chip testing apparatus 1 may further include a housing 31, where the housing 31 is fixedly disposed on the second fixing member 112, and the housing 31 correspondingly encloses the plurality of testing modules 30 to protect the plurality of testing modules 30. In a specific implementation, the casing 31 may be further provided with related heat dissipation devices, such as a fan, a heat dissipation fin, etc., according to requirements. In fig. 5 of the present embodiment, the chip testing apparatus 1 includes only a single housing 31, and the housing 31 correspondingly encloses a plurality of testing modules 30, but the number of the housings 31 of the chip testing apparatus 1 is not limited to a single one, and in different applications, the chip testing apparatus 1 may also include a plurality of housings 31, and each housing 31 may be enclosed with a single testing module 30 or two, three, etc. testing modules 30.

As shown in fig. 4 to 6, the first power supply member 4 is connected to the circuit board 10, and the first power supply member 4 may be connected to a plurality of test modules 30 through the circuit board 10. The first power supply member 4 may be, for example, a board-to-board connector, which may be in the form of a Pogo pin or a reed, but is not limited thereto. In fig. 4 of the present embodiment, the first power supply member 4 includes a plurality of connection terminals, and the first power supply member 4 is disposed on the first side 101 of the circuit board 10 and exposed to the first fixing member 111, but the form and number of the first power supply members 4 and the positions of the first power supply members 4 disposed on the circuit board are not limited to the illustration.

The first power supply member 4 is configured to be connected to a second power supply member (not shown) of the environmental control device E3, and the power supply device connected to the environmental control device E3 may supply power to each test module 30 through the second power supply member, the first power supply member 4, a plurality of first contact structures 1021 (as shown in fig. 9), and a plurality of second contact structures 33 (as shown in fig. 5), where the power supply device is a power supply device independent of the chip test apparatus 1, and the power supply device may be any device capable of providing power, which is not limited herein. That is, the chip testing apparatus 1 performs a predetermined test procedure on the plurality of chips C to which each test module 30 is connected, substantially without power, without being connected to the power supply device through the first power supply member 4. Of course, in different embodiments, the chip testing apparatus 1 may also be provided with at least one battery, where the battery is connected to the plurality of testing modules 30, and the battery can supply power to the plurality of testing modules 30.

In another embodiment, the first power supply member 4 may include a receiving antenna, and the first power supply member 4 may receive power wirelessly to provide power to each test module 30. In the embodiment where the first power supply member 4 is a receiving antenna, the chip testing device 1 may include a rechargeable battery module, and the first power supply member 4 is connected to the rechargeable battery module, and the first power supply member 4 can receive power in a wireless manner to charge the rechargeable battery module; in a specific implementation, the power required for testing the chip C carried by each test module 30 may be provided from the rechargeable battery module and the power supply device through the receiving antenna (the first power supply member 4). In the embodiment where the first power supply member 4 is a receiving antenna, the first power supply member 4 may be disposed at a position not exposed to the chip testing apparatus 1, but embedded in the circuit board 10 or hidden in the chip testing apparatus 1. The number of the first power supply members 4 included in each chip test apparatus 1 may be changed according to the need, and may be not limited to a single one, but may be two or more.

Referring to fig. 10, a block diagram of a chip testing apparatus 1 according to the present disclosure is shown. The chip testing apparatus 1 includes a first power supply member 4, where the first power supply member 4 is connected to a plurality of testing modules 30, and each testing module 30 is connected to a plurality of electrical connection sockets 2. The chip testing apparatus 1 may further comprise a plurality of first data transmission terminals 8. Each first data transmission terminal 8 may be connected to one test module 30. The plurality of first data transmission terminals 8 are used to connect with a plurality of second data transmission terminals E32 (shown in fig. 18) in a housing chamber E311 (shown in fig. 17, described in detail later) of the environmental control apparatus E3, and the chip testing device 1, the environmental control apparatus E3, and the central control apparatus E1 (shown in fig. 1) can transmit data to each other. In practical applications, each of the first data transmission terminals 8 and each of the second data transmission terminals E32 may have a Pogo pin or reed structure, but not limited thereto. The number of the first data transmission terminals 8 and the second data transmission terminals E32 and the arrangement positions thereof may be varied according to the requirements, and are not limited thereto.

In a different embodiment, the chip testing apparatus 1 may also include at least one first data transmission antenna (not shown), and the accommodating chamber E311 may be correspondingly provided with at least one second data transmission antenna (not shown). The first data transmission antenna is capable of interacting with the second data transmission antenna to wirelessly transmit information to each other. In practical applications, the position of the first data transmission antenna is not limited to the accommodating chamber E311, as long as the first data transmission antenna can mutually transmit information with the second data transmission antenna disposed in the accommodating chamber E311, and the first data transmission antenna can be disposed at any position of the environmental control device E3.

Referring to fig. 11 to 14, fig. 11 is a schematic diagram of an electrical connection socket of a chip testing apparatus according to the present invention, fig. 12 is a schematic exploded cross-sectional view of an electrical connection socket of a chip testing apparatus according to the present invention, fig. 13 is a schematic cross-sectional view of an electrical connection socket of a chip testing apparatus according to the present invention without a chip, and fig. 14 is a schematic cross-sectional view of an electrical connection socket of a chip testing apparatus according to the present invention with a chip.

Each electrical connection socket 2 comprises: a plurality of probe assemblies 20, an electrical connector body 21, a lifting structure 22, a supporting structure 23 and a plurality of elastic assemblies 24. Each probe assembly 20 includes a needle 201 and a spring 202. One end of the needle 201 is used to connect with an electrical connection C1 (shown in fig. 14) of the chip C. The spring 202 is sleeved on the needle 201, and when one end of the needle 201 is pressed, the spring 202 is correspondingly pressed to generate elastic restoring force, so that when the needle 201 is not pressed any more, the needle 201 is restored to an unpressurized position under the action of the elastic restoring force.

The electrical connector body 21 has a top wall 211, a ring side wall 212 and a supporting portion 213. The top wall 211 has an opening 21A, one side of the ring side wall 212 is connected to the periphery of the top wall 211, the other side of the ring side wall 212 is fixedly disposed on the circuit board 10, and the top wall 211, the ring side wall 212 and the circuit board 10 together form a receiving slot 21B. Opposite sides of top wall 211 define an outer side 2111 and an inner side 2112 (as shown in fig. 13). In practical applications, the top wall 211 and the ring side wall 212 may be integrally formed.

The ring side wall 212 is also formed with an abutment 213 protruding outwards. As shown in fig. 6 and 7, when the pressing structure 1112 is fixed to the fixing body 1114, the pressing structure 1112 will correspondingly abut against the abutting portion 213 of each electrical connection socket 2. That is, each of the pressing portions 213 is configured to facilitate pressing of the pressing structure 1112, and the shape of the pressing portion 213 may be designed corresponding to the pressing structure 1112 and the through hole 1113.

The lifting structure 22 includes a base 221 and a carrying portion 222. The base 221 is completely disposed in the accommodating groove 21B, the base 221 extends to one side to form a bearing portion 222, and a portion of the bearing portion 222 can be disposed through the opening 21A. The carrying portion 222 extends to a side far away from the base 221 to form four limiting portions 223, the four limiting portions 223 may be located at four corners of the carrying portion 222, and the four limiting portions 223 and the carrying portion 222 together form a chip accommodating groove 22B, the chip accommodating groove 22B is used for providing a chip C, and the four limiting portions 223 are used for mutually clamping with the chip C. The lifting structure 22 further has a plurality of connection holes 22A (as shown in fig. 12), and each connection hole 22A is disposed through the base 221 and the carrying portion 222.

A portion of the plurality of probe assemblies 20 is fixedly disposed in the supporting structure 23, and the plurality of probe assemblies 20 are fixedly disposed at one end of the supporting structure 23 for connecting with the electrical contact structure 1011 (shown in fig. 8) of the circuit board 10; the other ends of the plurality of probe assemblies 20 are located in the plurality of connection holes 22A, and one end of the probe assembly 20 located in the plurality of connection holes 22A is connected to the electrical connection portion C1 of the chip C.

In practical applications, the supporting structure 23 may include a base structure 231 and an auxiliary structure 232. The base structure 231 is disposed in the accommodating groove 21B, and the base structure 231 and the electrical connector body 21 are fixed to each other (e.g., fixed to the electrical connector body 21 by a plurality of screws). The base structure 231 has a plurality of through holes 2311, and one end of the plurality of probe assemblies 20 is fixedly disposed in the plurality of through holes 2311 of the base structure 231. The auxiliary structure 232 is disposed in the accommodating groove 21B, and the auxiliary structure 232 is disposed between the base structure 231 and the top wall 211, and the auxiliary structure 232 and the base structure 231 are fixed (e.g. locked by screws). The auxiliary structure 232 has a plurality of support holes 2321 disposed at intervals, the plurality of support holes 2321 are in communication with the plurality of through holes 2311 of the base structure 231, and the plurality of support holes 2321 are disposed corresponding to the plurality of connection holes 22A, and the plurality of connection holes 22A, the plurality of support holes 2321 and the plurality of through holes 2311 together form a plurality of probe channels, in which the plurality of probe assemblies 20 are disposed correspondingly.

As shown in fig. 8 and 12, it should be noted that the base structure 231 may include a plurality of positioning holes 2312, and each positioning hole 2312 is configured to provide the positioning member 25 to pass through. In practical applications, each positioning hole 2312 may be disposed through the base structure 231, but is not limited thereto.

As shown in fig. 13, the supporting structure 23 is disposed in the accommodating groove 21B, and the elastic member 24 is disposed between the supporting structure 23 and the lifting structure 22. The elastic component 24 can make the base 221 of the lifting structure 22 abut against the inner side surface 2112 of the top wall 211, and a gap S is correspondingly formed between the base 221 and the supporting structure 23.

In practical application, when the electrical connector 2 is fixed on the circuit board 10 and the limiting portion 223 of the electrical connector 2 is not pressed by an external force, the four elastic components 24 between the lifting structure 22 and the supporting structure 23 may be slightly compressed, and the elastic restoring force generated by the compression of the elastic components 24 will make the lifting structure 22 firmly abut against the inner side surface 2112 of the top wall 211.

As shown in fig. 14, when the chip C is fixedly disposed in the chip accommodating groove 22B and the lifting structure 22 is not pressed, the plurality of electrical connection portions C1 of the chip C are correspondingly accommodated in the plurality of connection holes 22A, and the respective probe assemblies 20 are not connected (e.g. not in contact with) with the plurality of electrical connection portions C1. When the lifting structure 22 is pressed, at least a portion of the lifting structure 22 will retract into the electrical connector body 21, i.e. the lifting structure 22 will move towards the circuit board 10 relative to the supporting structure 23, and the plurality of probe assemblies 20 will be correspondingly connected with the plurality of electrical connectors C1 (shown in fig. 23) of the chip C.

Referring back to fig. 7, in the embodiment shown in fig. 7, the number of the through holes 1113 of the pressing structure 1112 corresponds to the number of the electrical connectors 2 in the group accommodating hole 1115, and when the pressing structure 1112 is disposed in the group accommodating hole 1115, each through hole 1113 of the pressing structure 1112 correspondingly penetrates out a portion of one electrical connector 2. Referring to fig. 15, in a different embodiment, the number of through holes 1113 of the pressing structure 1112 may not completely correspond to the number of electrical connectors 2. For example, the pressing structure 1112 may have only three through holes 1113, and when the pressing structure 1112 presses the plurality of electrical connectors 2 disposed in the group accommodating hole 1115, each through hole 1113 penetrates a portion of the plurality of electrical connectors 2. In other words, the number or shape of the through holes 1113 of the pressing structure 1112 may be changed according to the requirement, and is not limited to the number or shape shown in fig. 7 or fig. 15.

Referring to fig. 15 and fig. 16, when the pressing structure 1112 is in the form shown in fig. 15, the shape of each electrical connection base 2 can be as shown in fig. 16. The electrical connection socket 2 shown in fig. 16 is different from the electrical connection socket 2 shown in fig. 11 in the following point: the top portion 213 of each electrical connection seat 2 has an annular top surface 2131, and the annular side wall 212 is correspondingly located in the area surrounded by the annular top surface 2131. When the pressing structure 1112 presses the plurality of electrical connection bases 2 located in the group accommodating hole 1115, the pressing structure 1112 will correspondingly press a partial area of the annular pressing surface 2131 of each electrical connection base 2.

Referring to fig. 13, 17 and 18 together, fig. 17 is a schematic diagram of an environmental control device of a chip testing system according to the present disclosure, and fig. 18 is a block schematic diagram of an environmental control device and a central control device of a chip testing system according to the present disclosure. The plurality of environmental control apparatuses E3 are connected to the central control device E1, and the central control device E1 can control any one of the environmental control apparatuses E3 to operate independently. Each of the environment control devices E3 is configured to perform a predetermined test procedure on a plurality of chips C disposed on the chip test apparatus 1 in an environment with a predetermined temperature (e.g., a predetermined high temperature or a predetermined low temperature).

Each environmental control apparatus E3 includes an apparatus body E31. The apparatus body E31 includes a plurality of accommodating chambers E311. The accommodating chamber E311 is mainly used for accommodating the chip testing device 1, and the plurality of accommodating chambers E311 included in the environmental control apparatus E3 may be mutually connected or not mutually connected, which is not limited herein. In practical applications, the central control device E1 may include a plurality of environmental status control devices (such as various microprocessors) and a central computer, and each environmental status control device may be disposed in each environmental control apparatus E3 and connected to the central computer.

It should be noted that, in an embodiment in which the plurality of chambers E311 included in the environmental control apparatus E3 are independent of each other and not communicated with each other, each chamber E311 may be provided with a movable door, and the environmental control apparatus E3 may be connected with an air extracting device E37. When the chip testing apparatus 1 is disposed in the accommodating chamber E311, the central control apparatus E1 can control the corresponding movable door to actuate so that the accommodating chamber E311 becomes a closed space, and then, the central control apparatus E1 can control the air extractor E37 to actuate so that the accommodating chamber E311 is in a state similar to a vacuum, so that the temperature in the accommodating chamber E311 is not easily affected by the external environment.

In an embodiment in which the first power supply member 4 of the chip testing apparatus 1 includes a plurality of connection terminals, a second power supply member may be disposed in each of the receiving chambers E311, and the second power supply member may include a plurality of receiving chamber terminals E33 (a pattern corresponding to the first power supply member 4), and the plurality of receiving chamber terminals E33 are configured to be connected to the plurality of connection terminals of the chip testing apparatus 1. The installation position of the housing chamber terminal E33 may be designed according to the position of the chip testing apparatus 1 in the housing chamber E311 and the positions of the plurality of connection terminals of the first power feeding member 4, and is not limited thereto. In the embodiment where the first power supply member 4 of the chip testing apparatus 1 is a receiving antenna for wireless charging, the second power supply member disposed in each of the accommodating chambers E311 may be a transmitting antenna for wireless charging, where the transmitting antenna is connected to a power supply device, and when the chip testing apparatus 1 is disposed at a predetermined position in the accommodating chamber E311, the transmitting antenna in the accommodating chamber E311 can be coupled with the receiving antenna (the first power supply member 4) of the chip testing apparatus 1, and the power supply device can provide power to each of the test modules 30.

Each temperature adjusting device E34 is connected to the central control device E1, and each temperature adjusting device E34 can be controlled by the central control device E1 to enable the ambient temperature of the chips C on the plurality of electrical connection seats 2 of the chip testing device 1 in the corresponding accommodating chamber E311 to reach a predetermined temperature.

Referring to fig. 19, each temperature adjusting device E34 may include a contact structure E341, a frame E35, and an elastic annular seal E36. The temperature adjusting device E34 is provided with a temperature adjuster, which is connected to the contact structure E341 and can be controlled to raise the temperature of the contact structure E341 to a predetermined high temperature, and also controlled to lower the temperature of the contact structure E341 to a predetermined low temperature. In practical applications, the temperature regulator may be, for example, a heating coil; or the temperature regulator may also include a plurality of fluid channels for accommodating the high temperature fluid or the low temperature fluid, and of course, the temperature regulator has a fluid inlet and a fluid outlet correspondingly, and the central control device E1 may control the device for providing the high temperature fluid or the device for providing the low temperature fluid to operate according to the requirement, so that the high temperature fluid or the low temperature fluid passes through the fluid inlet of the temperature regulator and enters the fluid channels of the temperature regulator; when the high temperature fluid or the low temperature fluid flows in the fluid channel, the temperature of the contact structure E341 is affected by the high temperature fluid or the low temperature fluid, and rises to the predetermined high temperature or falls to the predetermined low temperature.

In practical applications, the single temperature adjusting device E34 may have only heating coils or only fluid channels, and the temperature of the contact structure E341 of the single temperature adjusting device E34 will only rise to the predetermined high temperature or fall to the predetermined low temperature along with the corresponding temperature regulator. That is, the single temperature adjusting device E34 can only raise the ambient temperature of the plurality of chips C carried by the corresponding chip testing device 1 to a predetermined high temperature or lower the ambient temperature to a predetermined low temperature through the contact structure E341. More specifically, the temperature adjusting device E34 in the single accommodating chamber E311 can only make the chip C carried by the chip testing device 1 disposed therein at a predetermined high temperature or a predetermined low temperature, and if the chip testing device 1 needs to be in different temperature conditions, the chip testing device 1 must be moved to another accommodating chamber E311 by the related transfer device (e.g. a robot arm).

In another embodiment, the single temperature adjusting device E34 may also include two temperature adjusting devices, for example, one of the temperature adjusting devices E34 may be a heating coil, and the other temperature adjusting device may include a fluid channel for passing a low temperature fluid, so that the single temperature adjusting device E34 may be controlled to raise the temperature of the contact structure E341 to a predetermined high temperature or lower the temperature of the contact structure E341 to a predetermined low temperature. That is, after the chip testing apparatus 1 is disposed in one of the accommodating chambers E311, the temperature adjusting device E34 can make the chip C carried by the chip testing apparatus 1 contact the contact structure E341 reaching the predetermined high temperature according to the testing requirement, and then make the chip C carried by the chip testing apparatus 1 contact the contact structure E341 reaching the predetermined low temperature; or, the chip C carried by the chip testing device 1 is first contacted with the contact structure E341 reaching the predetermined low temperature, and then the chip C carried by the chip testing device 1 is contacted with the contact structure E341 reaching the predetermined high temperature.

The frame E35 of the temperature adjusting device E34 is disposed around the contact structure E341, and a contact surface E3411 of the contact structure E341 may be disposed flush with an annular pressing surface E351 of the frame E35, and the annular pressing surface E351 is correspondingly provided with an elastic annular sealing member E36. In a different embodiment, the contact surface E3411 may be disposed higher than the ring pressing surface E351, but the contact surface E3411 is disposed not lower than the ring pressing surface E351. The elastic annular sealing element E36 is disposed on the ring pressing surface E351, and the elastic annular sealing element E36 is disposed correspondingly around the contact structure E341. The elastic ring seal E36 may be made of a material that can be restored to original shape by pressing such as rubber according to the requirement, which is not limited herein; the cross-sectional shape of the elastic ring seal E36 may be, for example, circular, elliptical, trapezoidal, etc., and is not limited thereto.

Referring to fig. 19 and 20 together, fig. 20 is a schematic partial cross-sectional view of a chip testing apparatus 1. In the chip testing apparatus 1, when not pressed by the temperature adjusting device E34, a pressing surface 11141 of the fixing body 1114 of the first fixing member 111 is flush with the outer side surface 2111 of each electrical connection seat body 21, and a portion of the lifting structure 22 of each electrical connection seat 2 is higher than the pressing surface 11141. That is, when each chip C is disposed in the electrical connection base 2 and the chip testing device 1 is not pressed by the temperature adjusting device E34, part of the lifting structure 22 may be higher than the pressing surface 11141; the chip C disposed in the lifting structure 22 may be higher than the supporting surface 11141 or not higher than the supporting surface 11141, which is not limited herein.

Referring to fig. 17 and 21 together, fig. 21 is a schematic cross-sectional view of the temperature adjusting device E34 pressed against the chip testing device 1. When the chip testing apparatus 1 is transferred to one of the accommodating chambers E311 by a transfer apparatus (e.g., a robot arm), the lifting device E38 disposed in the accommodating chamber E311 is controlled by the central control device E1, so that the chip testing apparatus 1 moves toward the temperature adjusting device E34 until one side of the plurality of chips C carried by the chip testing apparatus 1 is pressed by the contact structure E341 of the temperature adjusting device E34. As shown in fig. 21, when the contact structure E341 presses against one side of the chips C carried by the chip testing device 1, a portion of the contact structure E341 simultaneously presses against the pressing surface 11141 of the fixing body 1114, and the elastic annular sealing element E36 correspondingly presses against the pressing surface 11141 of the fixing body 1114, and the contact structure E341, the fixing body 1114, the pressing structure 1112 and the circuit board 10 together form a closed space SP, and the plurality of electrical connection pads 2 are correspondingly located in the closed space SP.

When the contact structure E341 presses against one side of the chips C carried by the chip testing device 1 and the plurality of electrical connection seats 2 are correspondingly located in the enclosed space SP, the central control device E1 can control the air extraction device E37 to extract air in the enclosed space SP outwards, so that the enclosed space SP is in a state similar to vacuum, and during the process of extracting air outwards by the air extraction device E37, the chip testing device 1 is under negative pressure and is pressed against the temperature adjusting device E34 more tightly. As shown in fig. 19 and 22, fig. 22 is an enlarged partial schematic view of fig. 19. In practical applications, an air-extracting gap H may be formed between the contact structure E341 and the frame E35, the air-extracting gap H may be disposed around the contact structure E341, and the frame E35 may be formed with a plurality of air-extracting holes E352, the air-extracting holes E352 are in communication with the air-extracting gap H (e.g. the frame E35 has a corresponding channel therein), and the air-extracting holes E352 are used for communicating with the air-extracting device E37. In the present embodiment, the air extraction gap H is disposed around the contact structure E341, but the specific location and shape of the air extraction gap H are not limited thereto, so long as the enclosed space SP can be communicated with the air extraction device E37 through the air extraction gap H and the air extraction hole E352. In addition, the number, shape and arrangement positions of the air extraction holes E352 can be changed according to requirements.

It should be noted that, in practical application, after the chip testing apparatus 1 is disposed in one of the accommodating chambers E311, the central control apparatus E1 may control the lifting apparatus E38 to move a predetermined distance so that the chip testing apparatus 1 moves to a position contacting the temperature adjusting apparatus E34, that is, a state that the elastic annular sealing member E36 contacts the top surface 11141 of the chip testing apparatus 1; then, the central control device E1 may control the air extractor E37 and the lifting device E38 to act together, so that the enclosed space SP gradually assumes a state similar to a vacuum state, and at the same time, the contact structure E341 will press the lifting structure 22 of each electrical connection seat 2, so that each lifting structure 22 is retracted into the corresponding electrical connection seat 2.

As shown in fig. 21 and 23, fig. 23 is an enlarged view of a portion of a single electrical connection socket pressed by a contact structure, and when the contact structure E341 presses the lifting structure 22 of each electrical connection socket 2, and each lifting structure 22 is retracted into the corresponding electrical connection socket 2, a plurality of probe assemblies 20 in each electrical connection socket 2 are correspondingly connected to a plurality of electrical connection parts C1 of the chip C. When the plurality of probe assemblies 20 are connected to the plurality of electrical connection parts C1 of the chip C, the plurality of connection terminals of the first power supply member 4 (shown in fig. 6) are correspondingly connected to the plurality of receiving chamber terminals E33 (shown in fig. 18) in the receiving chamber E311 (shown in fig. 17), and the respective test modules 30 are supplied with power, whereby the central control device E1 can control the respective test modules 30 to perform a predetermined test procedure on the chip C on the electrical connection pad 2 to which it is connected.

In practical applications, the central control device E1 controls the air extractor E37, and the time point of extracting the air in the enclosed space SP can be designed according to the requirement. For example, the central control device E1 may determine whether the chip testing device 1 is already disposed at a predetermined position in the accommodating chamber E311 by at least one sensor (for example, an optical sensor or a mechanical pressing sensor) disposed in the accommodating chamber E311 (as shown in fig. 17), and when the central control device E1 determines that the chip testing device 1 is disposed at the predetermined position in the accommodating chamber E311 by the sensor, the air extracting device E37 is controlled to extract air in the enclosed space SP.

As shown in fig. 19 and 20, by the design that the outer side surface 2111 of each electrical connection seat 2 is flush with the abutting surface 11141, the contact surface E3411 of the contact structure E341 is flush with the annular abutting surface E351 (or the contact surface E3411 is not lower than the annular abutting surface E351), the elastic annular sealing member E36 is disposed on the annular abutting surface E351, and the like, the acting force required by the lifting device E38 to push against the chip testing device 1 can be greatly reduced by cooperating with the action of the air extracting device E37. More specifically, the lifting device E38 is to make the chip testing device 1 approach to the contact structure E341 of the temperature adjusting device E34, so that the contact structure E341 contacts the chips C on the plurality of electrical connection seats 2 at the same time. As described above, when the contact structure E341 contacts the chips C on the plurality of electrical connection seats 2 at the same time, the lifting device E38 must resist the elastic restoring force generated by the pressing of the elastic components 24 of each electrical connection seat 2 and the elastic restoring force generated by the pressing of each probe component 20 of each electrical connection seat 2 at the same time; therefore, the air in the enclosed space SP is pumped out by the air pumping device E37, so that the enclosed space SP is in a negative pressure state, and the force required by the lifting device E38 when pushing against the chip testing device 1 can be greatly reduced.

In particular, according to the above description of the chip testing apparatus 1, since only the circuit board locking hole 103 is provided through the circuit board 10 of the chip testing apparatus 1, when the temperature adjusting device E34 abuts against the first fixing member 111, the sealing property of the enclosed space SP will be easily controlled, and the air extracting device E37 will be relatively easy to reach the state of near vacuum in the process of extracting the air in the enclosed space SP. That is, in the chip testing apparatus 1 of the present invention, the number of through holes of the circuit board 10 is greatly reduced by the design of the first fixing member 111, the second fixing member 112, and the like, so that the air extractor E37 is relatively easy to reach the vacuum state in the closed space SP when the air extractor extracts the closed space SP.

Referring back to fig. 1 and 2, the transferring apparatus E4 is disposed between the plurality of environmental control apparatuses E3, and the transferring apparatus E4 is used for carrying the chip testing device 1. The transferring apparatus E4 may include a robot arm and a holding component for holding the chip testing device 1. The central control device E1 is connected to the transfer equipment E4, and the central control device E1 can control the transfer equipment E4 to set the chip testing device 1 carrying a plurality of chips C in any accommodating chamber E311 (as shown in fig. 17) of any environmental control equipment E3. In contrast, the transferring apparatus E4 may also be controlled by the central control device E1 to move the chip testing device 1 disposed in any one of the accommodating chambers E311 out of the accommodating chamber E311.

The sorting device E5 is connected to the central control device E1, and the sorting device E5 can be controlled by the central control device E1 to detach the chips C from the electrical connection bases 2 of the chip testing device 1, and the sorting device E5 can place the chips C on the carrier tray of the good product area A1 or the carrier tray of the defective product area A2 according to the test result after the chips C pass through the predetermined test program. The sorting device E5 may for example be a robotic arm. In the embodiment in which the sorting device E5 and the chip mounting device E2 are disposed at adjacent positions, the chip mounting device E2 and the sorting device E5 may share the same robot arm. In practical applications, the good area A1 may be divided into a plurality of areas according to the requirements, and the classification device E5 may set the chips C in different areas of the good area A1 according to the test results of the chips C after passing through the predetermined test procedure, for example, the classification device may be used to distinguish the chips C according to the operation performance of the chips C.

Fig. 24 is a schematic flow chart of a first embodiment of a chip testing method according to the present disclosure. The chip test system E may be a chip test method for performing a predetermined test procedure on a plurality of chips C, the chip test method including:

A chip mounting step S1: transferring a plurality of chips (C) from a carrier disc to a plurality of electric connection seats (2) of the chip testing device (1) through chip mounting equipment (E2);

moving to step S2: transferring a chip testing device (1) carrying a plurality of chips (C) to one of the accommodating chambers (E311) of one of the environmental control equipment (E3);

A temperature adjusting step S3: controlling the operation of a temperature regulating device (E34) in the accommodating chamber (E311) so as to enable the plurality of chips (C) to be in an environment with a preset temperature;

a test step S4: supplying power to the chip testing device (1) arranged in the accommodating chamber (E311) so that each testing module (30) performs a predetermined testing procedure on a plurality of chips (C) connected with the testing module;

A step S6 of moving out: removing the chip testing device (1) from the accommodating chamber (E311), and transferring the chip testing device (1) to the sorting equipment (E5);

A classification step S7: and (3) utilizing the classification equipment (E5) to respectively place the chips (C) into the good product area (A1) or the defective product area (A2) according to the test results of the chips (C) after the preset test program is completed.

In an embodiment in which the first power supply member 4 of the chip testing apparatus 1 includes a plurality of connection terminals, before the testing step S4, a connection step may be further included: the plurality of connection terminals of the first power supply member 4 of the chip testing apparatus 1 are connected to the plurality of housing chamber terminals E33 provided in the housing chamber E311. In a specific implementation, the connection step may be located between the moving-in step S2 and the temperature adjusting step S3, or the connection step may be located between the temperature adjusting step S3 and the testing step S4.

Fig. 25 is a schematic flow chart of a second embodiment of a chip testing method according to the present invention. The biggest difference between this embodiment and the embodiment shown in fig. 24 is that: an air pumping step S21 may be further included between the moving step S2 and the temperature adjusting step S3. In the moving-in step S2, the elastic annular sealing member E36 of the temperature adjusting device E34 disposed in the accommodating chamber E311 is connected with the circuit board 10 of the chip testing apparatus 1, so that the temperature adjusting device E34 and the circuit board 10 together form a closed space SP (as shown in fig. 21), and then, in the air exhausting step S21, the air exhausting device E37 connected with the closed space SP is actuated to exhaust the air in the closed space SP.

As shown in fig. 21 and described in the foregoing corresponding embodiment, when the temperature adjusting device E34 and the circuit board 10 together form the enclosed space SP, each electrical connection seat 2 is correspondingly located in the enclosed space SP. After the pumping step S21 is performed, each electrical connection pad 2 is located in a near-vacuum environment, so that the temperature of the enclosed space SP is not easily affected by the external environment when the temperature adjusting step S3 is performed, and the ambient temperature of the electrical connection pad 2 and the chip C carried by the electrical connection pad 2 is easily maintained at a predetermined temperature.

Fig. 26 is a schematic flow chart of a third embodiment of a chip testing method according to the present disclosure. The present embodiment is most different from the foregoing embodiments in that: the step between the test step S4 and the removal step S6 may further comprise the following steps:

A separation step S5: after the chip testing device (1) completes a predetermined test program for all chips (C) connected thereto, the first power supply member (4) of the chip testing device (1) is controlled to be separated from the plurality of housing chamber terminals (E33) in the housing chamber (E311).

As shown in fig. 3, 17 and 18, in practical applications, the environmental control apparatus E3 may further include a plurality of lifting devices E38, and each of the accommodating chambers E311 is provided with one lifting device E38. Each lifting device E38 is connected to an environmental state control device of the central control device E1. The elevating devices E38 are controlled by the central control device E1 to elevate the chip testing device 1 disposed in the housing chamber E311, and further connect or disconnect the plurality of connection terminals of the first power feeding member 4 of the chip testing device 1 and the housing chamber terminal E33.

In practical applications, when each chip testing apparatus 1 is transferred into the accommodating chamber E311 by the transferring device E4, the plurality of first power supply members 4 of the chip testing apparatus 1 may not be connected to the plurality of accommodating chamber terminals E33, and when the central control apparatus E1 determines that any accommodating chamber E311 is provided with the chip testing apparatus 1, the central control apparatus E1 may control the corresponding lifting apparatus E38 to actuate, so as to move the chip testing apparatus 1 in the accommodating chamber E311, thereby connecting the plurality of connection terminals of the first power supply members 4 with the accommodating chamber terminals E33, and thereby, the power supply device may provide power to the plurality of test modules 30 through the first power supply member 4.

In practical applications, the manner how the central control device E1 determines whether the chip testing device 1 is disposed in any of the accommodating chambers E311 may be designed according to the requirements, which is not limited herein. For example, a sensor (for example, an optical sensor or any mechanical push switch) may be disposed in the accommodating chamber E311, and when the chip testing device 1 enters the accommodating chamber E311, the sensor generates a corresponding signal and transmits the signal to the central control device E1, and the central control device E1 may determine whether the chip testing device 1 is disposed in the accommodating chamber E311 according to the signal transmitted by the sensor. Of course, the sensor may be used to confirm whether the chip testing device 1 is disposed at a predetermined position in the accommodating chamber E311, and the sensor may transmit a corresponding signal to the central control device E1 according to the position of the chip testing device 1 in the accommodating chamber E311, and the central control device E1 may determine whether the chip testing device 1 is disposed at the predetermined position in the accommodating chamber E311 according to the signal transmitted by the sensor, and if the central control device E1 determines that the chip testing device 1 is disposed at the predetermined position in the accommodating chamber E311, the central control device E1 may control the lifting device E38 to actuate; on the contrary, if the central control device E1 determines that the chip testing device 1 is not located at the predetermined position in the accommodating chamber E311, the central control device E1 may control the relevant warning device to act to warn the user, for example, the central control device E1 may control the relevant warning light to emit a specific color light, control the relevant display screen to display an error message, etc.

In the embodiment where the first power supply member 4 is a receiving antenna, when the chip testing apparatus 1 is disposed in the accommodating chamber E311, the corresponding transmitting antenna in the accommodating chamber E311 may be coupled with the receiving antenna, and the chip testing apparatus 1 may obtain the electric power through the first power supply member 4. Of course, in another embodiment, the receiving antenna may be correspondingly coupled to the receiving antenna when the chip testing device 1 is disposed at a predetermined position in the accommodating chamber E311, which is not limited herein.

In practical applications, before the temperature adjustment step S3, the central control device E1 will control the air extractor E37 to extract air from the enclosed space SP so that the enclosed space SP is in a state close to vacuum, and thus, after the temperature adjustment step S3, the temperature in the enclosed space SP will not be easily affected by the external environment.

In the test step S4, the chip test apparatus 1 is coupled or connected with the corresponding transmitting antenna or the corresponding receiving chamber terminal through the receiving antenna or the plurality of connecting terminals, so as to obtain the power, so that each test module 30 can test the chip C connected thereto.

As shown in fig. 17 and 18, in practical application, in order to enable the plurality of connection terminals of the first power supply member 4 of the chip testing apparatus 1 and the plurality of housing chamber terminals E33 to be firmly connected to each other, the environmental control apparatus E3 may further include a plurality of limiting devices E39, and the plurality of limiting devices E39 are disposed in the plurality of housing chambers E311. Each limiting device E39 is connected with the central control device E1. Each limiting device E39 can be controlled by the central control device E1 to limit the movable range of the chip testing device 1 in the accommodating chamber E311. The specific structure of the limiting device E39 may be designed according to the requirement, for example, the chip testing device 1 may be provided with a clamping hole, and the limiting device E39 includes a corresponding clamping hook structure, and when the limiting device E39 acts, the clamping hook structure may be correspondingly clamped in the clamping hole; alternatively, the limiting device E39 may include a plurality of telescopic pins, and the telescopic pins may be correspondingly inserted into the engaging holes of the chip testing device 1.

In the above embodiment, in which each of the accommodating chambers E311 of each of the environmental control apparatuses E3 has the contact structure E341, the lifting device E38 and the limiting device E39, the above chip testing method may include the following steps in the moving step S2:

A step of moving into the accommodating chamber: moving the chip testing device (1) into the accommodating chamber (E311);

A rising step: controlling a lifting device (E38) in the accommodating chamber (E311) so as to enable the chip testing device (1) to move towards the contact structure (E341);

a locking step: and controlling a limiting device (E39) in the accommodating chamber (E311) so that the limiting device (E39) limits the movable range of the chip testing device (1) in the accommodating chamber (E311).

In the above-mentioned manner, the chip testing method of the present invention may be that a plurality of chips are mounted on the chip testing device 1; then, the chip testing apparatus 1 is moved into one of the accommodation chambers E311 of the environmental control equipment E3; then, the lifting device E38 is controlled to lift the chip testing device 1, so that one side of the plurality of chips C of the chip testing device 1 is adjacent to the contact structure E341 of the temperature adjusting device E34, and the elastic annular sealing member E36 of the temperature adjusting device E34 is pressed against the circuit board 10 of the chip testing device 1 to form a closed space SP; subsequently, the air extractor E37 is controlled to extract air from the closed space SP so that one side of the plurality of chips C on the chip testing device 1 is attached to the contact structure E341, and at the same time, the temperature adjusting device E34 is controlled to operate so that the chips C reach a predetermined temperature; when the temperature adjusting device E34 is activated, power is supplied to the chip testing device 1 so that the plurality of test modules 30 test the plurality of chips C.

Referring to fig. 27, a flow chart of a fourth embodiment of a chip testing method according to the present invention is shown, and the chip testing system E can test a plurality of memories (i.e. the chips) by using the chip testing method. The chip testing method disclosed in this embodiment is different from the chip testing method described above in the greatest point: after moving into step S2 and before separating step S5, the temperature adjusting step S3 and the testing step S4 may be repeated twice, which are the temperature adjusting step S31, the testing step S41, the temperature adjusting step S32, and the testing step S42, respectively.

In the temperature adjustment step S31 and the test step S41 (i.e. the temperature adjustment step S3 and the test step S4 are performed for the first time), the temperature adjustment device E34 corresponding to the accommodating chamber E311 is controlled first, so that the plurality of chips C are in an environment with a temperature above 115 ℃, and then each test module 30 is controlled to perform at least one of a read test, a write test and an electrical test on the plurality of chips C. The temperature adjustment step S31 and the test step S41 are the Burn-In test for the memory.

In the temperature adjustment step S32 and the test step S42 (i.e. the temperature adjustment step S3 and the test step S4 are performed for the second time), the temperature adjustment device E34 corresponding to the accommodating chamber E311 is controlled first, so that the plurality of chips C are in an environment with a temperature of 75 ℃ to 95 ℃, and then each test module 30 is controlled to perform at least one of a read test, a write test and an electrical test on the plurality of chips C. The temperature adjustment step S32 and the test step S42 are performed to test the memory at a high temperature.

Specifically, in different embodiments, the test step S41 and the temperature adjustment step S32 may include a moving-out step and a moving-in step; the removing step is to remove the chip testing device 1 from the accommodating chamber E311, and the moving step is to move the chip testing device 1 into the other accommodating chamber E311. That is, the chip testing apparatus 1 may be sequentially located in two different chambers E311 (may be located in the same environmental control device E3 or located in different environmental control devices E3) with a temperature above 115 ℃ and a temperature between 75 ℃ and 95 ℃.

Referring to fig. 28, a flow chart of a fifth embodiment of a chip testing method according to the present invention is shown, and the chip testing system E can test a plurality of memories (i.e. the chips) by using the chip testing method. The chip testing method disclosed in this embodiment is different from the chip testing method shown in fig. 27 in the following greatest points: after moving into step S2 and before separating step S5, the temperature adjusting step S3 and the testing step S4 may be repeatedly performed three times, which are the temperature adjusting step S31, the testing step S41, the temperature adjusting step S32, the testing step S42, the temperature adjusting step S33 and the testing step S43, respectively.

After the temperature adjustment step S32 and the test step S42 are performed, the temperature adjustment step S33 and the test step S43 (i.e. the temperature adjustment step S3 and the test step S4 are performed for the third time) are performed by controlling the temperature adjustment device E34 corresponding to the accommodating chamber E311, so that the plurality of chips C are in an environment with a temperature of-55 ℃ to-35 ℃, and then controlling each test module 30 to perform at least one of a read test, a write test and an electrical test on the plurality of chips C. In other words, the chip testing method disclosed In this embodiment sequentially performs Burn-In (Burn-In), high temperature test and low temperature test on the plurality of chips C.

Referring to fig. 29, a flowchart of a sixth embodiment of a chip testing method according to the present invention is shown, and the chip testing system E can test a plurality of memories (i.e. the chips) by using the chip testing method. The chip testing method disclosed in this embodiment is different from the chip testing method shown in fig. 28 in the following greatest points: after moving into step S2 and before separating step S5, the temperature adjusting step S3 and the testing step S4 may be repeatedly performed four times, which are the temperature adjusting step S31, the testing step S41, the temperature adjusting step S32, the testing step S42, the temperature adjusting step S33, the testing step S43, the temperature adjusting step S34 and the testing step S44, respectively.

After the temperature adjustment step S33 and the test step S43 are performed, the temperature adjustment step S34 and the test step S44 (i.e. the temperature adjustment step S3 and the test step S4 are performed for the fourth time) are performed by controlling the temperature adjustment device E34 corresponding to the accommodating chamber E311, so that the plurality of chips C are in an environment with a temperature (normal temperature) of 20 ℃ to 30 ℃, and then controlling each test module 30 to perform at least one of a read test, a write test and an electrical test on the plurality of chips C. In other words, the chip testing method disclosed In this embodiment sequentially performs Burn-In (Burn-In), high temperature, low temperature and normal temperature tests on the plurality of chips C.

As described above, the chip testing method of the present embodiment may be performed by using the chip testing system E in which each temperature adjusting device E34 in each environmental control apparatus E3 can be controlled to raise the temperature of the contact structure E341 and can also be controlled to lower the temperature of the contact structure E341. After the chip test apparatus 1 is moved into the housing chamber E311 of the environment control device E3, at least one of a read test, a write test, and an electrical test, that is, a Burn-In (Burn-In) test, a high temperature test, a low temperature test, and a normal temperature test are sequentially performed on the plurality of chips C In an environment of 115 ℃ or higher, an environment of 75 ℃ to 95 ℃, an environment of-55 ℃ to-35 ℃, and an environment of 20 ℃ to 30 ℃. Of course, in practical applications, the order of Burn-In (Burn-In), high temperature test, low temperature test and normal temperature test of the chips C by the chip test apparatus 1 may be arranged according to the requirement, and is not limited to the above order.

Referring to fig. 30, a flow chart of a seventh embodiment of a chip testing method according to the present invention is shown, and the chip testing system E can test a plurality of memories (i.e. the chips) by using the chip testing method. The chip testing method disclosed in this embodiment is different from the chip testing method shown in fig. 27 in the following greatest points: the steps between the removing step S6 and the classifying step S7 may further include the following steps:

A shift-in step SX1: transferring a chip testing device (1) carrying a plurality of chips (C) to a containing chamber (E311) of another environmental control equipment (E3);

A temperature adjustment step SX2: controlling the operation of the temperature regulating means (E34) in the housing chamber (E311) so as to bring the plurality of chips (C) into an environment of-55 ℃ to-35 ℃;

A test step SX3: the chip testing device (1) arranged in the accommodating chamber (E311) is supplied with power so that each testing module (30) performs a predetermined testing procedure on a plurality of chips (C) connected with the testing module.

The chip testing method of the present embodiment is to set the chip testing device 1 in the accommodating chamber E311 of one of the environmental control equipment E3, and sequentially make the plurality of chips C in the environment with the temperature above 115 ℃ and the environment with the temperature between 75 ℃ and 95 ℃ to perform at least one of the read test, the write test and the electrical test; then, the chip testing apparatus 1 is moved out of the accommodating chamber E311, and the chip testing apparatus 1 is moved into one of the accommodating chambers E311 of the different environmental control devices E3 (or into the other accommodating chamber E311 of the same environmental control device E3); subsequently, the temperature adjusting device E34 of the accommodating chamber E311 is controlled to operate, so that the plurality of chips C carried by the chip testing device 1 are subjected to at least one of a read test, a write test and an electrical test in an environment with a temperature of-55 ℃ to-35 ℃.

The chip testing method of the present embodiment may be performed by using the chip testing system E described above, and in particular, the temperature adjusting devices E34 of the respective environmental control apparatuses E3 may be controlled only to raise or lower the temperature of the contact structure E341.

In the chip testing method of the present embodiment, since the temperature of the single accommodating chamber E311 does not drop from the temperature above 100 ℃ to the temperature below 0 ℃, the time for the temperature around each chip C to reach the predetermined high temperature and the predetermined low temperature can be greatly shortened, and the energy consumption required by each temperature adjusting device E34 for the accommodating chamber E311 to reach the predetermined temperature can be greatly reduced.

Fig. 31 is a schematic flow chart of an eighth embodiment of the chip testing method disclosed in the present invention, by which the chip testing system E can test a plurality of memories (i.e. the chips). The chip testing method disclosed in this embodiment is different from the chip testing method described above in the greatest point: after the temperature adjustment step SX2 and the test step SX3, the method may further include a temperature adjustment step SX4 and a test step SX5. In the temperature adjustment step SX4, the temperature adjustment device E34 in the accommodating chamber E311 is controlled to operate, so that the plurality of chips C are in an environment of 20 ℃ to 30 ℃. In the test step SX5, power is supplied to the chip test apparatus 1 disposed in the accommodating chamber E311, so that each test module 30 performs a predetermined test procedure on the plurality of chips C connected thereto. That is, in the temperature adjustment step SX2 and the test step SX3, the plurality of chips C are tested in a low-temperature environment, and in the temperature adjustment step SX4 and the test step SX5, the plurality of chips C are tested in a normal-temperature environment.

It should be noted that, in different embodiments, after each test module 30 completes a predetermined test procedure for the chips C on the plurality of electrical connection seats 2 connected thereto, the test module 30 may write the test result data and the corresponding test parameters of each chip C into each chip C, so that the test result data and the test parameter data are stored in each chip C. Further, the test result data may, for example, include: the test conditions of the chip C in the high temperature test, the burn-in test, the low temperature test, and the normal temperature test, respectively, may be that only whether the chip C passes the high temperature test, the burn-in test, the low temperature test, and the normal temperature test is recorded. In a specific chip testing method, after each of the testing steps S41, S42, S43, S44 (as shown in fig. 29), the method may include: a test result writing step: and storing the test result data after each memory completes the preset test program and the corresponding test parameter data in each memory.

The test parameter data may be, for example, data including: the identification Number (ID Number) of the chip test apparatus 1, the identification Number of the test module 30, the identification Number of the electrical connection holder 2, the identification Number of the environmental control device E3 and the identification Number of the housing chamber E311 thereof, the temperature value at the time of the high temperature test, the temperature value at the time of the burn-in test, the temperature value at the time of the low temperature test, the temperature value at the time of the normal temperature test, and the like.

Through the above design that the test module 30 writes the test result data and the test parameter data of the chip C into the chip C, when any chip C is handed to the consumer, the consumer can read the data stored in the chip C by the relevant device to confirm the test status performed during the production; and when any chip C returned by a consumer is received by a relevant producer, the detection process of the chip C can be traced rapidly by reading the test result data and the test parameter data stored in the chip C, so that the producer can be effectively assisted to find possible defects in the detection process.

In a different embodiment, the chip testing method may also include, after the classifying step S7 (as shown in fig. 29): a test result writing step: and storing the test result data after each memory completes the preset test program and the corresponding test parameter data in each memory. Specifically, when the memories carried by the chip testing apparatus 1 complete all the tests (such as burn-in test and high temperature test, or burn-in test, high temperature test, low temperature test, and normal temperature test) according to the requirements, the central control apparatus E1 may control the classification device E5 first, and classify each memory according to the test results of each memory. Then, the central control device E1 controls the related read-write equipment again, and performs related read-write operation on the memories classified into the good area A1, so as to store the corresponding test result data and test parameter data in each memory. That is, only the memory divided into good products stores therein the test result data and the test parameter data.

The chip testing method may also include, before the classifying step S7 (as shown in fig. 29): a test result writing step: and storing the corresponding test result data and test parameter data in the corresponding memories passing through the memories of the preset test programs. Specifically, when the memory carried by the chip testing device1 is completed according to the requirement and passes all the tests (such as a burn-in test and a high temperature test, or a burn-in test, a high temperature test, a low temperature test, and a normal temperature test), the chip testing device1 writes the test result corresponding to the memory and the related test parameter data into the memory; conversely, if the memory fails at least one of the tests, the chip test apparatus 1 will not write any test related data corresponding to the memory into the memory. In this way, in the classifying step S7, the classifying device may determine whether the memory passes the test by determining whether any test related data is written in the memory, and if the classifying device determines that the memory is not written with the data, the classifying device may classify the memory directly into the defective area.

In addition, it should be emphasized that in the embodiment in which any of the above power supply members includes a plurality of connection terminals, both the connection terminals and the housing terminals may be directly replaced with the receiving antenna and the transmitting antenna. Of course, since the receiving antenna and the transmitting antenna perform power transmission in a wireless manner, when the connecting terminal and the housing terminal are directly replaced with the receiving antenna and the transmitting antenna, the related process steps of contacting or separating the connecting terminal and the housing terminal in some of the above embodiments may be omitted.

In summary, the chip testing system, the chip testing device and the chip testing method suitable for the chip testing system disclosed by the invention have the advantages of cost and better testing efficiency compared with the existing chip testing equipment. In addition, the chip test system disclosed by the invention is characterized in that a plurality of chips are arranged on the chip test device, and then the chip test device is transferred, so that the chips are in different temperature environments for relevant test operation, and therefore, the chips are arranged on the same chip test device in the process of testing in different temperature environments, and therefore, the chips cannot be repeatedly detached and installed in the whole test process, and the chips are not easy to be damaged unexpectedly. In contrast, in the conventional memory inspection apparatus, the memory is repeatedly detached and installed on the electrical connection base in different temperature environments, so that unexpected damage is easy to occur after the memory is repeatedly detached and installed.

The foregoing disclosure is only illustrative of the preferred embodiments of the present invention and is not to be construed as limiting the scope of the invention, as all changes which come within the meaning and range of equivalency of the description and drawings are therefore intended to be embraced therein.

Claims

1. An environmental control apparatus for performing a predetermined test procedure on a plurality of chips disposed on a chip test device in an environment of a predetermined high temperature or a predetermined low temperature, the chip test device including at least a first power supply member, the environmental control apparatus being connected to an air extraction device, the environmental control apparatus comprising:

An apparatus body including a plurality of accommodating chambers; at least one second power supply component is arranged in each accommodating chamber, and the equipment body is connected with power supply equipment; when the chip testing device is arranged in one of the accommodating chambers, the power supply equipment can supply power to the chip testing device through the first power supply component and the second power supply component;

an environmental state control device connected to the device body;

A plurality of temperature adjusting devices connected to the environmental state control device, one of the temperature adjusting devices being provided in each of the accommodating chambers, each of the temperature adjusting devices comprising:

at least one temperature regulator;

At least one contact structure, which is provided with a contact surface, wherein the contact surface is used for contacting with one side surface of a plurality of chips carried by the chip testing device; the temperature regulator is controllable to raise the temperature of the contact structure to the predetermined high temperature, and the temperature regulator is also controllable to lower the temperature of the contact structure to the predetermined low temperature;

A frame body arranged around the contact structure, the frame body having a ring pressing surface, the ring pressing surface being flush with the contact surface, or the contact surface being higher than the ring pressing surface;

An elastic annular seal member disposed on the annular pressing surface; when the contact surface is contacted with one side surface of a plurality of chips carried by the chip testing device, the elastic annular sealing element correspondingly presses the chip testing device, and a closed space is correspondingly formed between the contact structure and the chip testing device; the air extraction device can be controlled to extract air in the enclosed space outwards;

Wherein each of said temperature adjustment devices is controllable by said environmental condition control device to operate independently of the other of said temperature adjustment devices;

When the chip testing device is arranged in one of the accommodating chambers, the contact structure is abutted against one side surface of a plurality of chips borne by the chip testing device, the chip testing device is powered, the contact structure reaches the preset high temperature or the preset low temperature, and air in the closed space is pumped out by the air pumping device, the chip testing device can be controlled to perform the preset testing procedure on the chips borne by the chip testing device;

At least one air extraction gap is formed between the frame body of each temperature adjusting device and the contact structure, the frame body is provided with at least one air extraction hole, the air extraction holes are communicated with the air extraction gaps, and the air extraction devices can extract air in the closed space outwards through the air extraction holes and the air extraction gaps.

2. The environmental control apparatus according to claim 1, further comprising a plurality of limiting devices, one of the limiting devices being provided in each of the accommodation chambers, each of the limiting devices being connected to the environmental state control device; each limiting device can be controlled by the environment state control device and is connected with the chip testing device arranged in the accommodating chamber, so that the movable range of the chip testing device in the accommodating chamber is limited.

3. The environmental control apparatus according to claim 1, further comprising a plurality of lifting devices, one of the lifting devices being provided in each of the accommodating chambers, each of the lifting devices being connected to the environmental state control device; each lifting device can be controlled by the environment state control device so that the chip testing device arranged in the accommodating chamber moves in the accommodating chamber.

4. The environmental control apparatus according to claim 1, wherein the environmental control apparatus further comprises the chip test device, the chip test device comprising:

At least one circuit board, two opposite sides of which are respectively defined as a first side and a second side; the circuit board is provided with a plurality of positioning holes and a plurality of circuit board locking holes, each positioning hole does not penetrate through the circuit board, and each circuit board locking hole penetrates through the circuit board;

The fixing assembly comprises a first fixing member and a second fixing member, the first fixing member is fixedly arranged on the first side surface, the second fixing member is fixedly arranged on the second side surface, the first fixing member is provided with a plurality of first lock holes, the second fixing member is provided with a plurality of second lock holes, and the first lock holes, the circuit board lock holes and the second lock holes are correspondingly arranged; a plurality of locking pieces are locked in a plurality of the first locking holes, a plurality of the circuit board locking holes and a plurality of the second locking holes, and the circuit board is fixed between the first fixing component and the second fixing component;

The plurality of electric connection seats are provided with an electric connection seat body; one side of each electric connection seat body is used for bearing one chip, the other side of each electric connection seat body is provided with at least two positioning pieces, each positioning piece is mutually clamped with a plurality of positioning holes, and each electric connection seat is arranged on the first side face of the circuit board; the first fixing member comprises a plurality of pressing structures, the pressing structures correspondingly press against a part of the electric connecting seats, each electric connecting seat is pressed by the first fixing member to be fixed on the first side surface of the electric connecting seat, the first fixing member comprises a plurality of through holes, and a part of each electric connecting seat is correspondingly exposed out of each through hole;

The control unit is arranged on the second side surface of the circuit board and comprises a plurality of test modules, and each test module is connected with a part of the electric connection seat; the second fixing member is provided with a plurality of avoidance holes, and a part of the plurality of test modules penetrate through the plurality of avoidance holes; and

The first power supply component is connected with the circuit board;

the chip testing device must be connected with the power supply equipment through the first power supply component so as to obtain the power required by the operation of each testing module.

5. The environmental control apparatus of claim 4 wherein each of the test modules comprises: a pattern generator, a component power supply module and a driving circuit; the chip is a memory, and the predetermined test program comprises: at least one of a read test, a write test, and an electrical test; the plurality of electric connection seat areas are a plurality of electric connection seat groups, and each electric connection seat group comprises at least one electric connection seat; the plurality of test modules are connected with the electric connection seats of the plurality of electric connection seat groups, and each test module is connected with all the electric connection seats in the corresponding electric connection seat groups.

6. The environmental control apparatus of claim 5 wherein the first fixing member further comprises a fixing body, each of the pressing structures is detachably fixed to the fixing body, each of the fixing bodies has a plurality of group receiving holes, each of the group receiving holes is configured to receive a plurality of the electrical connection sockets in a same group of the electrical connection sockets.

7. The environmental control apparatus of claim 6 wherein said circuit board has a plurality of first contact structures on said second side, each of said test modules having at least one second contact structure, said second contact structure of each of said test modules being capable of detachably contacting one of said first contact structures.

8. The environmental control apparatus according to claim 4, wherein the first power supply member includes a plurality of connection terminals provided on the first side surface of the circuit board, and the plurality of connection terminals are exposed from the first fixing member; the second power supply member in each of the accommodation chambers includes a plurality of accommodation chamber terminals; the plurality of connection terminals are used for being connected with the plurality of accommodating chamber terminals in each accommodating chamber; when the plurality of connection terminals are connected with the plurality of accommodation chamber terminals in one of the accommodation chambers, the power supply device and the power supply device can supply power to the chip testing device.

9. The environmental control apparatus of claim 4 wherein the first power supply means is a receiving antenna and the second power supply means is a transmitting antenna, the receiving antenna being configured to couple to the transmitting antenna, and the chip test device being configured to wirelessly receive power transmitted by the power supply means via the receiving antenna.

10. The environmental control apparatus of claim 4, wherein the chip testing device further comprises at least one first data transmission terminal, the first data transmission terminal is disposed on the circuit board, and the first data transmission terminal is exposed from the first fixing member; each accommodating chamber further comprises at least one second data transmission terminal; the first data transmission terminals are used for contacting with the second data transmission terminals in the accommodating chambers to mutually transmit data.

11. The environmental control apparatus of claim 4 wherein the chip test device further comprises at least a first data transmission antenna; the equipment body also comprises at least one second data transmission antenna; and the first data transmission antenna is used for wirelessly transmitting data with the second data transmission antenna.

12. The environmental control apparatus of claim 4 wherein each of said test modules writes test result data and test parameter data of each of said chips into said chip after said predetermined test procedure is completed for said chip on a plurality of said electrical connection pads to which it is connected, such that each of said chips stores test result data and test parameter data.

13. The environmental control apparatus of claim 4 wherein each electrical connection pad comprises:

the base body is provided with a top wall and a ring side wall, the top wall is provided with an opening, one end of the ring side wall is connected with the periphery of the top wall, the other end of the ring side wall is propped against the circuit board, and a containing groove is formed among the top wall, the ring side wall and the circuit board; the two opposite side surfaces of the top wall are defined as an outer side surface and an inner side surface, and the inner side surface is positioned in the accommodating groove; the side of the top wall opposite to the circuit board is defined as an outer side surface, and the outer side surface is flush with an abutting top surface of the first fixing member opposite to the circuit board;

the supporting structure is propped against the circuit board and is positioned in the accommodating groove, and comprises a plurality of positioning holes, and each positioning hole is provided with one positioning piece;

The lifting structure is arranged in the accommodating groove and is provided with a base part and a bearing part, the base part is positioned in the accommodating groove, the base part extends to one side to form the bearing part, and at least one part of the bearing part is positioned in the opening; the bearing part extends to one side far away from the base part to form a plurality of limiting parts, at least one part of the limiting parts penetrates out of the open hole, and the limiting parts and the bearing part jointly form a chip accommodating groove which is used for accommodating the chip; the lifting structure is also provided with a plurality of connecting holes, and the connecting holes penetrate through the base part and the bearing part;

The elastic components are arranged in the accommodating grooves, one end of each elastic component is fixed on the lifting structure, the other end of each elastic component is fixed on the supporting structure, the elastic restoring force generated by the compression of the elastic components enables the base to be propped against the inner side surface of the top wall, and a gap is formed between the lifting structure and the supporting structure;

The probe assemblies are fixedly arranged on the supporting structure at one end, the other ends of the probe assemblies are propped against the electric contact structure of the circuit board, and the other ends of the probe assemblies penetrate through the connecting holes;

When the chip accommodating groove is provided with the chip and the limiting part is not pressed by the contact structure, the probe assemblies in the plurality of connecting holes are not connected with the plurality of contact parts of the chip, and a part of the lifting structure protrudes out of the outer side surface of the top wall;

When the chip accommodating groove is provided with the chip, the limiting part is pressed by the contact structure to shrink inwards towards the base body, and the elastic annular sealing piece and the propping surface of the first fixing member are mutually propped, the probe assemblies are propped against the electric contact structure of the circuit board.

14. A chip testing system, the chip testing system comprising:

a chip testing device for carrying a plurality of chips, the chip testing device comprising at least a first power supply member;

a central control device, the central control device comprises an environmental state control device; and

At least one environmental control device, the environmental control device is connected with an air extracting device, the environmental control device comprises:

an apparatus body including a plurality of accommodating chambers; at least one second power supply component is arranged in each accommodating chamber, and the equipment body is connected with power supply equipment; when the chip testing device is arranged in one of the accommodating chambers, the power supply equipment can supply power to the chip testing device through the first power supply component and the second power supply component; and

at least one temperature regulator;

At least one contact structure, which is provided with a contact surface, wherein the contact surface is used for contacting with one side surface of a plurality of chips carried by the chip testing device; the temperature regulator is controllable to raise the temperature of the contact structure to a predetermined high temperature, and the temperature regulator is also controllable to lower the temperature of the contact structure to a predetermined low temperature;

A frame body arranged around the contact structure, the frame body having a ring pressing surface, the ring pressing surface being flush with the contact surface, or the contact surface being higher than the ring pressing surface; and

15. The chip test system according to claim 14, wherein the environmental control apparatus further comprises a plurality of limiting devices, one of the limiting devices is disposed in each of the accommodating chambers, and each of the limiting devices is connected to the environmental state control device; each limiting device can be controlled by the environment state control device and is connected with the chip testing device arranged in the accommodating chamber, so that the movable range of the chip testing device in the accommodating chamber is limited.

16. The chip testing system of claim 14, wherein said environmental control apparatus further comprises a plurality of lifters, one of said lifters being disposed in each of said compartments, each of said lifters being coupled to said environmental condition control means; each lifting device can be controlled by the environment state control device so that the chip testing device arranged in the accommodating chamber moves in the accommodating chamber.

17. The chip testing system of claim 14, wherein the environmental control apparatus further comprises the chip testing device, the chip testing device comprising:

The first power supply component is connected with the circuit board;

18. The chip testing system of claim 17, wherein each of said test modules comprises: a pattern generator, a component power supply module and a driving circuit; the chip is a memory, and the predetermined test program comprises: at least one of a read test, a write test, and an electrical test; the plurality of electric connection seat areas are a plurality of electric connection seat groups, and each electric connection seat group comprises at least one electric connection seat; the plurality of test modules are connected with the electric connection seats of the plurality of electric connection seat groups, and each test module is connected with all the electric connection seats in the corresponding electric connection seat groups.

19. The chip testing system of claim 18, wherein the first fixing member further comprises a fixing body, each of the pressing structures is detachably fixed to the fixing body, each of the fixing bodies has a plurality of group receiving holes, and each of the group receiving holes is configured to receive a plurality of the electrical connection sockets in a same group of the electrical connection sockets.

20. The chip testing system of claim 19, wherein said circuit board has a plurality of first contact structures on said second side, each of said test modules having at least one second contact structure, said second contact structure of each of said test modules being capable of detachably contacting one of said first contact structures.

21. The chip testing system according to claim 17, wherein the first power supply member includes a plurality of connection terminals, the plurality of connection terminals are disposed on the first side surface of the circuit board, and the plurality of connection terminals are exposed from the first fixing member; the second power supply member in each of the accommodation chambers includes a plurality of accommodation chamber terminals; the plurality of connection terminals are used for being connected with the plurality of accommodating chamber terminals in each accommodating chamber; when the plurality of connection terminals are connected with the plurality of accommodation chamber terminals in one of the accommodation chambers, the power supply device and the power supply device can supply power to the chip testing device.

22. The chip testing system of claim 17, wherein the first power supply member is a receiving antenna, the second power supply member is a transmitting antenna, the receiving antenna is configured to couple with the transmitting antenna, and the chip testing device is configured to wirelessly receive the power transmitted by the power supply device through the receiving antenna.

23. The chip testing system according to claim 17, wherein the chip testing device further comprises at least one first data transmission terminal, the first data transmission terminal is disposed on the circuit board, and the first data transmission terminal is exposed from the first fixing member; each accommodating chamber further comprises at least one second data transmission terminal; the first data transmission terminals are used for contacting with the second data transmission terminals in the accommodating chambers to mutually transmit data.

24. The chip test system according to claim 17, wherein the chip test device further comprises at least a first data transmission antenna; the equipment body also comprises at least one second data transmission antenna; and the first data transmission antenna is used for wirelessly transmitting data with the second data transmission antenna.

25. The chip test system according to claim 17, wherein each of said test modules writes test result data and test parameter data of each of said chips into said chip after said predetermined test procedure is completed for said chips on said plurality of said electrical connection pads to which said test module is connected, so that each of said chips stores test result data and test parameter data.

26. The chip testing system of claim 17, wherein each of said electrical connection sockets comprises: