CN112305785A

CN112305785A - Preparation method of thermo-optic phase shifter based on SOI substrate

Info

Publication number: CN112305785A
Application number: CN201910690187.5A
Authority: CN
Inventors: 蔡艳; 俞文杰; 王书晓; 刘强; 余明斌
Original assignee: Shanghai Institute of Microsystem and Information Technology of CAS
Current assignee: Shanghai Institute of Microsystem and Information Technology of CAS
Priority date: 2019-07-29
Filing date: 2019-07-29
Publication date: 2021-02-02

Abstract

The invention provides a preparation method of a thermo-optic phase shifter based on an SOI substrate, which comprises the following steps: forming a graphical SOI substrate, wherein the SOI substrate sequentially comprises a bottom silicon layer, an insulating layer and a top silicon layer from bottom to top, a groove is formed in the SOI substrate, the lower surface of the groove and the lower surface of the bottom silicon layer have a distance, and the top silicon layer covers the groove; photoetching the top silicon layer above the groove to form a silicon waveguide; forming a dielectric layer, a heating resistor and a metal electrode; the dielectric layer at least covers the silicon waveguide; the heating resistor is positioned above the silicon waveguide or on one side of the silicon waveguide, and a distance is reserved between the heating resistor and the silicon waveguide; the metal electrode is connected with the heating resistor. The invention is beneficial to improving the production yield and the device performance, further simplifying the preparation flow and reducing the production cost.

Description

Preparation method of thermo-optic phase shifter based on SOI substrate

Technical Field

The invention belongs to the field of optical device manufacturing, and particularly relates to a preparation method of a thermo-optic phase shifter based on an SOI (silicon on insulator) substrate.

Background

Thermo-optic phase shifters are an important component in silicon-based optoelectronic devices. The phase-locked loop realizes the regulation and control of the phase of the optical wave based on the thermo-optic effect of the material, can be used in various occasions such as sensing, optical switches, high-order modulators, delay lines, variable optical attenuators, neural networks and the like, and plays an irreplaceable role in an optical communication system.

Thermal modulation power consumption is a very important performance criterion for thermo-optic phase shifter devices, and refers to the power consumption required when the phase of light propagating in a waveguide changes by pi. How to reduce the thermo-modulation loss of thermo-optic devices to improve thermo-optic efficiency is an important research direction of current thermo-optic phase shifters. One conventional method is to form a suspended structure by hollowing out the lower portion of the silicon waveguide after the silicon waveguide is formed, so as to reduce heat leakage from the substrate, thereby reducing the thermal modulation loss, and thus improving the thermo-optical efficiency. However, this method has many problems. For example, since the silicon waveguide is hollowed by etching or other processes after being formed, the device performance is likely to be reduced due to damage of the silicon waveguide in the etching process; and the device structure manufactured based on this method is likely to expose the substrate to air, and moisture and the like in the air may diffuse into the device, resulting in a failure in the reliability of the device. The complexity of the process is further increased if the hollowed-out structure needs to be re-sealed.

Disclosure of Invention

In view of the above drawbacks of the prior art, an object of the present invention is to provide a method for fabricating a thermo-optic phase shifter based on an SOI substrate, which is used to solve the problems that the existing method for fabricating a silicon-optic phase shifter is easy to damage a silicon waveguide, and moisture may diffuse into a device, resulting in performance degradation and even complete failure of the device.

To achieve the above and other related objects, the present invention provides a method for fabricating a thermo-optic phase shifter based on an SOI substrate, the method comprising the steps of:

forming a graphical SOI substrate, wherein the SOI substrate sequentially comprises a bottom silicon layer, an insulating layer and a top silicon layer from bottom to top, a groove is formed in the SOI substrate, the lower surface of the groove and the lower surface of the bottom silicon layer have a distance, and the top silicon layer covers the groove;

photoetching the top silicon layer above the groove to form a silicon waveguide;

forming a dielectric layer, a heating resistor and a metal electrode; the dielectric layer at least covers the silicon waveguide; the heating resistor is positioned above the silicon waveguide or on one side of the silicon waveguide, and a distance is reserved between the heating resistor and the silicon waveguide; the metal electrode is connected with the heating resistor.

In an alternative, the recess is located in the bottom silicon layer, and an upper surface of the recess is flush with a lower surface of the insulating layer.

Optionally, a horizontal area of the silicon waveguide is smaller than a horizontal area of the groove; and completely etching the top silicon layer positioned at the periphery of the silicon waveguide to expose the insulating layer in the process of photoetching the top silicon layer above the groove to form the silicon waveguide.

In an alternative, the heating resistor is a metal resistor, and the process of forming the dielectric layer, the heating resistor and the metal electrode includes:

forming a first dielectric layer, wherein the first dielectric layer covers the silicon waveguide and the insulating layer;

forming a metal resistance layer, wherein the metal resistance layer is positioned on the surface of the first dielectric layer;

carrying out graphical etching on the metal resistance layer to form the heating resistor positioned above the silicon waveguide;

forming a second dielectric layer, wherein the second dielectric layer covers the heating resistor;

forming a through hole in the second dielectric layer, wherein the through hole exposes out of the heating resistor;

and depositing metal in the through hole to form the metal electrode, wherein the metal electrode is connected with the heating resistor.

In another alternative, the heating resistor is a doped silicon resistor; the process of forming the silicon waveguide also comprises defining a heating resistance area at the same time, wherein the heating resistance area and the silicon waveguide are positioned on the same horizontal plane and have a distance with the silicon waveguide; the process of forming the dielectric layer, the heating resistor and the metal electrode comprises the following steps:

ion implanting the heating resistor region to form the heating resistor of a doped silicon resistor;

forming a dielectric layer, wherein the dielectric layer covers the heating resistor and the silicon waveguide;

forming a through hole in the dielectric layer, wherein the through hole exposes out of the heating resistor;

In yet another alternative, the recess extends through the insulating layer, an upper surface of the recess being flush with a lower surface of the top silicon layer, and a lower surface of the recess being flush with an upper surface of the bottom silicon layer.

In yet another alternative, the recess extends through the insulating layer and down into the bottom silicon layer, an upper surface of the recess being flush with a lower surface of the top silicon layer.

Optionally, the horizontal area of the silicon waveguide is smaller than the horizontal area of the groove, and the top silicon layer located at the periphery of the silicon waveguide is partially etched in the process of performing photolithography etching on the top silicon layer above the groove to form the silicon waveguide, so that the groove is still covered by the top silicon layer.

In an alternative, the heating resistor is a metal resistor; the process of forming the dielectric layer, the heating resistor and the metal electrode comprises the following steps:

forming a first dielectric layer, wherein the first dielectric layer covers the top silicon layer and the silicon waveguide;

In one alternative, the heating resistor is a doped silicon resistor; the process of forming the silicon waveguide also comprises defining a heating resistance area at the same time, wherein the heating resistance area and the silicon waveguide are positioned on the same horizontal plane and have a distance with the silicon waveguide; the process of forming the dielectric layer, the heating resistor and the metal electrode comprises the following steps:

As described above, the method for manufacturing a thermo-optic phase shifter based on an SOI substrate according to the present invention has the following advantageous effects:

according to the invention, the groove is formed below the position where the silicon waveguide is to be formed, so that the damage and water vapor diffusion of the silicon waveguide, which are easily caused in the traditional preparation method of hollowing after the silicon waveguide is formed, are avoided, and the production yield and the device performance are improved. The preparation method is simple, and can realize large-scale production through graphical customization of the SOI substrate, thereby being beneficial to further simplifying the preparation flow and reducing the production cost.

Drawings

FIG. 1 is a flow chart showing a method for fabricating a thermo-optic phase shifter based on an SOI substrate according to the present invention.

Fig. 2 to 11 are schematic structural diagrams showing steps in an embodiment of the present invention.

Fig. 12 to 21 are schematic structural diagrams showing steps in the second embodiment of the present invention.

Fig. 22 to 26 are schematic views showing a process of manufacturing an SOI substrate in the second embodiment of the present invention.

Fig. 27 to fig. 36 are schematic structural diagrams showing three steps according to the embodiment of the present invention.

Description of the element reference numerals

11 bottom silicon layer

12 insulating layer

13 top silicon layer

14 groove

15 silicon waveguide

16 dielectric layer

161 first dielectric layer

162 second dielectric layer

17 heating resistor

171 heating the resistive area

18 metal electrode

21 first silicon wafer

22 second silicon wafer

23 oxide layer

24 opening

S01-S03

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structures are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.

For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.

Example one

As shown in fig. 1 to 11, the present invention provides a method for fabricating a thermo-optic phase shifter based on an SOI substrate, the method comprising the steps of:

s01: forming a patterned SOI substrate, wherein the SOI substrate sequentially comprises a bottom silicon layer 11, an insulating layer 12 and a top silicon layer 13 from bottom to top, a groove 14 is formed in the SOI substrate, the lower surface of the groove 14 and the lower surface of the bottom silicon layer 11 have a distance, namely the groove 14 does not penetrate through the bottom silicon layer 11, and the top silicon layer 13 covers the groove 14;

s02: photoetching the top silicon layer 13 above the groove 14 to form a silicon waveguide 15;

s03: forming a dielectric layer 16, a heating resistor 17 and a metal electrode 18; the dielectric layer 16 at least covers the silicon waveguide 15; the heating resistor 17 is positioned above the silicon waveguide 15 or on one side of the silicon waveguide 15, and a gap is formed between the heating resistor 17 and the silicon waveguide 15; the metal electrode 18 is connected to the heating resistor 17.

According to the invention, the groove 14 is formed below the position where the silicon waveguide 15 is to be formed, so that the silicon waveguide 15 is prevented from being damaged easily in the traditional preparation method of hollowing after the silicon waveguide 15 is formed, water vapor is prevented from being diffused into the formed device structure, and the production yield and the device performance are improved. The preparation method is simple, and can realize large-scale production through graphical customization of the SOI substrate, thereby being beneficial to further simplifying the preparation flow and reducing the production cost.

By way of example, the materials of the top silicon layer 13 and the bottom silicon layer 11 are preferably the same, such as both silicon materials or other types of silicon materials, such as germanium, sapphire or other commonly used optical materials. In this embodiment, the silicon material is preferred, and the single crystal silicon is more preferred, which helps to reduce the transmission loss of light and the thermal modulation loss. The thickness of the bottom silicon layer 11 is preferably greater than the thickness of the top silicon layer 13, such as in one example, the thickness of the bottom silicon layer 11 is 650 μm to 750 μm; the thickness of the top silicon layer 13 is 200nm (nanometer) to 5 μm (micrometer), such as 220nm, 340nm, 3um, etc. The horizontal plane shape (i.e. the top view shape) of the groove 14 may be a rectangle, a circle, a ring or other shapes, and a rectangle or a circle is preferred in this embodiment, which is beneficial to simplify the preparation of the device and to improve the thermo-optic conversion uniformity of the device. The insulating layer 12 is preferably a silicon dioxide layer, and the thickness is preferably 1-5 μm, such as 2um, 3um, etc.

In this embodiment, as shown in fig. 2, the groove 14 is located in the bottom silicon layer 11, and an upper surface of the groove 14 is flush with a lower surface of the insulating layer 12, that is, the groove 14 is located only in the bottom silicon layer 11; the bottom surface of the recess 14 is spaced from the bottom surface of the bottom silicon layer 11, i.e. the recess 14 does not penetrate the bottom silicon layer 11.

As an example, the horizontal area of the silicon waveguide 15 is smaller than that of the groove 14, and the shape of the silicon waveguide 15 may be set as needed, such as a circular column, a rectangular column, a cylinder, a serpentine ridge, or other shapes, to transmit light in a predetermined direction, so as to reduce transmission loss. In this embodiment, as an example, in the process of performing photolithography etching on the top silicon layer 13 above the groove 14 to form the silicon waveguide 15, the top silicon layer 13 located at the periphery of the silicon waveguide 15 is completely etched to expose the insulating layer 12, and the silicon waveguide 15 is located right above the groove 14, as shown in fig. 3 in particular, this structure helps to reduce the transmission loss of light by strictly limiting the transmission path of light in the silicon waveguide 15.

As shown in fig. 4 to 7, in an example, the heating resistor 17 is a metal resistor, and the process of forming the dielectric layer 16, the heating resistor 17 and the metal electrode 18 includes:

forming a first dielectric layer 161, where the first dielectric layer 161 covers the silicon waveguide 15 and the insulating layer 12, as shown in fig. 4 specifically;

forming a metal resistance layer, wherein the metal resistance layer is positioned on the surface of the first dielectric layer 161;

performing a patterned etching on the metal resistance layer to form the heating resistor 17 located above the silicon waveguide 15, as shown in fig. 5;

forming a second dielectric layer 162, wherein the second dielectric layer 162 covers the heating resistor 17, as shown in fig. 6 specifically;

forming a through hole (not shown) in the second dielectric layer 162, the through hole exposing the heating resistor 17;

depositing metal in the through hole to form the metal electrode 18, wherein the metal electrode 18 is connected to the heating resistor 17, as shown in fig. 7.

The first dielectric layer 161 and the second dielectric layer 162 are preferably made of the same material, such as silicon dioxide, silicon nitride, etc., to ensure that they have the same optical properties, such as the same refractive index and reflectivity, so as to reduce the transmission loss of light. Methods for forming the first dielectric layer 161 and the second dielectric layer 162 include, but are not limited to, vapor deposition methods, and a planarization process may be performed after forming the first dielectric layer 161 and/or the second dielectric layer 162 to improve the flatness of the device surface to reduce scattering of incident light, if necessary. The thickness of the first dielectric layer 161 is greater than the height of the silicon waveguide 15, the thickness of the second dielectric layer 162 is greater than the height of the heating resistor 17, and the first dielectric layer 161 and the second dielectric layer 162 jointly form the dielectric layer 16.

The material of the metal resistance layer includes but is not limited to metal or metal-like materials compatible with CMOS process, such as tungsten, titanium nitride, etc., and the method for forming the metal resistance layer includes but is not limited to chemical vapor deposition or physical vapor deposition method; the heating resistor 17 is preferably formed directly above the silicon waveguide 15 and at a reasonable distance from the silicon waveguide 15, that is, the orthographic projection of the heating resistor 17 covers the silicon waveguide 15, so as to facilitate uniform heating of the silicon waveguide 15 and improve heating efficiency. Because if the pitch is too small, light propagating in the silicon waveguide 15 is liable to leak into the heating resistor 17, resulting in additional light propagation loss due to the absorption effect of metal; if the spacing is too large, the heating efficiency is reduced. The inventor finds that through multiple experiments and comprehensive consideration of practical process tolerance, when the distance is 200 nm-2000 nm, more preferably 500-1000 nm, better balance between transmission loss and heating efficiency can be achieved.

The method for forming the through hole in the second dielectric layer 162 includes, but is not limited to, photolithography and etching, and the area of the top opening 24 of the through hole is preferably larger than the area of the bottom opening 24, so as to facilitate metal deposition; the method for depositing metal in the through holes to form the metal electrode 18 includes, but is not limited to, one or more of a physical vapor deposition method and an electroplating method, the number of the through holes is preferably multiple, and the multiple through holes are uniformly distributed so that the metal electrode 18 formed subsequently can achieve uniform heat conduction effect; the material of the metal electrode 18 includes, but is not limited to, gold, silver, aluminum, copper or other materials. The heating resistor 17 made of metal materials is beneficial to improving the heating efficiency and improving the performance of the prepared thermo-optic phase shifter.

As shown in fig. 8 to 11, in another example, the heating resistor 17 is a doped silicon resistor; the process of forming the silicon waveguide 15 further includes defining a heating resistor region 171 at the same time, the heating resistor region 171 is preferably also located above the groove 14, the heating resistor region 171 is located on the same horizontal plane as the silicon waveguide 15 and has a distance from the silicon waveguide 15, the distance is preferably 200nm to 1000nm, and more preferably 300 nm to 500nm, taking into consideration practical process tolerance, so as to achieve a better balance between transmission loss and heating efficiency, and the heating resistor region 171 may be located on one side of the silicon waveguide 15, may also be located on both sides thereof, and may also be distributed along the circumferential direction of the silicon waveguide 15, which is not strictly defined in this embodiment, and it is important to ensure that the silicon waveguide 15 can be uniformly heated, so that the metal electrode 18 formed subsequently needs to be matched with the heating resistor 17; the process of forming the dielectric layer 16, the heating resistor 17 and the metal electrode 18 includes:

the heating resistor region 171 is ion-implanted to form the heating resistor 17 of a doped silicon resistor, specifically, as shown in fig. 8 and 9, the doped ions may be one or more of boron, phosphorus, arsenic, indium, carbon, etc., and the total doping concentration is preferably greater than 1 × 10¹⁶ions/cm³(ii) a Of course, it should be noted that this step is preferably performed under the condition that the photoresist mask on the surface of the silicon waveguide 15 remains after the heating resistor region 171 is defined by using a photolithography and etching method, and the photoresist mask is removed after ion implantation is performed, or a protective layer at least covering the silicon waveguide 15 is formed (preferably, other regions except the heating resistor region 171 are all covered by the protective layer) to ensure that implanted ions do not diffuse into the silicon waveguide 15;

forming a dielectric layer 16, wherein the dielectric layer 16 covers the heating resistor 17 and the silicon waveguide 15, as shown in fig. 10 specifically;

forming a through hole in the dielectric layer 16, wherein the through hole exposes the heating resistor 17;

depositing metal in the through hole to form the metal electrode 18, wherein the metal electrode 18 is connected to the heating resistor 17, as shown in fig. 11.

The formation method, parameters and material selection of the above steps can refer to the above contents, and are not repeated for the sake of brevity. The doped silicon resistor is adopted as the heating resistor 17, which is beneficial to the simplification of the preparation process of the thermo-optic phase shifter and the reduction of the production cost.

Example two

As shown in fig. 12 to 21, the present invention also provides another method for fabricating a thermo-optic phase shifter based on an SOI substrate. The preparation method of the embodiment is different from the first embodiment in that: in the first embodiment, the groove 14 is only located in the bottom silicon layer 11, and in the process of etching the top silicon layer 13 to form the silicon waveguide 15, preferably, all the top silicon layer 13 on the periphery of the silicon waveguide 15 is etched and removed; in this embodiment, the groove 14 penetrates through the insulating layer 12, the upper surface of the groove 14 is flush with the lower surface of the top silicon layer 13, and the lower surface of the groove 14 is flush with the upper surface of the bottom silicon layer 11, that is, the groove 14 is only located in the insulating layer 12, as shown in fig. 12 specifically; in this embodiment, the horizontal area of the silicon waveguide 15 is smaller than the horizontal area of the groove 14, in the process of performing the photolithography etching on the top silicon layer 13 above the groove 14 to form the silicon waveguide 15, the top silicon layer 13 located at the periphery of the silicon waveguide 15 is partially etched to make the groove 14 still covered by the top silicon layer 13, a part of the top silicon layer 13 is left for mechanical support, and the height of the top silicon layer 13 at the periphery of the silicon waveguide 15 is smaller than the height of the silicon waveguide 15, specifically as shown in fig. 13.

In an example, as shown in fig. 14 to 17, the heating resistor 17 is a metal resistor, and the heating resistor 17 made of a metal material is beneficial to improving the heating efficiency and improving the performance of the prepared thermo-optic phase shifter; the process of forming the dielectric layer 16, the heating resistor 17 and the metal electrode 18 includes:

forming a first dielectric layer 161, wherein the first dielectric layer 161 covers the top silicon layer 13 and the silicon waveguide 15, as shown in fig. 14;

performing patterned etching on the metal resistance layer to form the heating resistor 17 located above the silicon waveguide 15, as shown in fig. 15;

forming a second dielectric layer 162, wherein the second dielectric layer covers the heating resistor 17, as shown in fig. 16 in particular;

forming a through hole in the second dielectric layer 162, wherein the through hole exposes the heating resistor 17;

depositing metal in the through hole to form the metal electrode 18, wherein the metal electrode 18 is connected to the heating resistor 17, as shown in fig. 17.

For the above-mentioned forming method, parameters and material selection of each step, please refer to the description in the first embodiment, and details are not repeated for the sake of brevity.

As shown in fig. 18 to 21, in another example, the heating resistor 17 is a doped silicon resistor; the process of forming the silicon waveguide 15 further includes defining a heating resistor region 171, wherein the heating resistor region 171 is located on the same horizontal plane as the silicon waveguide 15 and has a distance from the silicon waveguide 15; the process of forming the dielectric layer 16, the heating resistor 17 and the metal electrode 18 includes:

the heating resistor region 171 is ion-implanted to form the heating resistor 17 of a doped silicon resistor, as shown in fig. 18 and 19:

forming a dielectric layer 16, wherein the dielectric layer 16 covers the heating resistor 17 and the silicon waveguide 15, as shown in fig. 20 specifically;

depositing metal in the through hole to form the metal electrode 18, wherein the metal electrode 18 is connected to the heating resistor 17, as shown in fig. 21.

Similarly, please refer to the description in the first embodiment for the formation method, parameters, and material selection of the above steps, which are not repeated for brevity. The doped silicon resistor is adopted as the heating resistor 17, which is beneficial to the simplification of the preparation process of the thermo-optic phase shifter and the reduction of the production cost.

It should be noted that although the specific forming positions of the grooves 14 are different in different examples, the process of forming the patterned SOI substrate may be substantially the same as long as the shape and depth of the grooves 14 are predefined as required. The process of forming the SOI substrate will be schematically described in this embodiment, but the process is also applicable to forming the SOI substrate in other embodiments.

As shown in fig. 22 to 26, a first silicon wafer 21, such as a single crystal silicon wafer (as shown in fig. 22), is provided, and an oxide layer 23 (as shown in fig. 23, the oxide layer 23 corresponds to the insulating layer 12 of the SOI substrate of this embodiment) is formed on the surface of the first silicon wafer 21, the oxide layer 23 is preferably silicon oxide, and methods for forming the oxide layer 23 include, but are not limited to, a thermal oxidation method and a vapor deposition method. In this embodiment, as an example, the thickness of the oxide layer 23 is preferably 1 to 5 μm, such as 2um, 3um, etc.;

as shown in fig. 24, performing ion implantation on the first silicon wafer 21 by using the surface of the oxide layer 23 as an implantation surface to implant ions to a predetermined depth in the first silicon wafer 21 (as shown in the position shown by the dotted line in fig. 24, the first silicon wafer 21 above the predetermined depth corresponds to the top silicon layer 13 of the SOI substrate in this embodiment), which corresponds to the thickness of the top silicon layer 13 of the SOI substrate in this embodiment; the implanted ions can be one or more of H ions and He ions, and the implantation dosage is 1 x 10¹⁶ions/cm²～1×10¹⁸ions/cm²The injection process can be sequential injection or simultaneous injection;

as shown in fig. 25, the oxide layer 23 is etched by photolithography to define an opening 24 (the opening 24 corresponds to the groove 14 in the SOI substrate), in this embodiment, the opening 24 is only located in the oxide layer 23 and penetrates through the oxide layer 23;

providing a second silicon wafer 22 (in this embodiment, the second silicon wafer 22 corresponds to the bottom silicon layer 11 of the SOI substrate), for example, another monocrystalline silicon wafer, and bonding the second silicon wafer 22 to the first silicon wafer 21 having the opening 24 formed on the surface thereof, where the surface where the opening 24 is located is a bonding surface; the bonded structure is then stripped from the predetermined depth, such as by high temperature annealing to strip the portion of the first silicon wafer 21 below the predetermined depth, or by chemical mechanical polishing to remove the portion of the first silicon wafer 21 below the predetermined depth, so as to obtain the SOI substrate shown in fig. 26.

Naturally, the forming method and step of the SOI substrate may have other options, for example, in the above example, the opening 24 may be formed by photolithography etching without performing ion implantation after the oxide layer 23 is formed on the surface of the first silicon wafer 21, the second silicon wafer 22 without the oxide layer 23 formed on the surface is subjected to ion implantation and implanted to a predetermined depth, then the first silicon wafer 21 and the second silicon wafer 22 are bonded, and the bonded wafer is peeled from the region where the predetermined depth is located, so that the SOI substrate is obtained, in this step, the first silicon wafer 21 corresponds to the bottom silicon layer 11 of the SOI substrate, and the non-peeled portion of the second silicon wafer 22 bonded to the oxide layer 23 corresponds to the top silicon layer 13 of the SOI substrate.

In another example, the SOI substrate in the present application may be obtained by bonding the first silicon wafer 21 having the opening 24 formed on the surface thereof to an SOI structure having a release structure layer (typically, a structure layer of an oxide material) formed in the middle thereof, peeling the bonded structure from the release structure layer of the SOI structure, and removing the release structure layer.

Appropriate adjustments (e.g., adjusting the depth of the opening 24) in accordance with the above-described method may result in the desired SOI substrate in other embodiments without further expansion.

The SOI substrate can be customized according to needs to realize large-scale production, and is beneficial to further simplifying the preparation flow of the thermo-optic phase shifter and reducing the production cost.

EXAMPLE III

As shown in fig. 27 to 36, the present invention provides another method for fabricating a thermo-optic phase shifter based on an SOI substrate. The preparation method of the embodiment is different from the second embodiment in that: in the second embodiment, the groove 14 is only located in the insulating layer 12, but in this embodiment, the groove 14 penetrates through the insulating layer 12 and extends all the way down into the bottom silicon layer 11, and the upper surface of the groove 14 is flush with the lower surface of the top silicon layer 13, that is, the groove 14 is located in the insulating layer 12 and in the bottom silicon layer 11. Otherwise, the manufacturing method of this embodiment is completely the same as that of the second embodiment, for example, the heating resistor 17 in this embodiment may also be a metal resistor, which is also located above the silicon waveguide 15 and has a distance with the silicon waveguide 15 (specifically, as shown in fig. 27 to 32); the heating resistor 17 may also be a doped silicon resistor, and is located at one side of the silicon waveguide 15 and has a distance from the silicon waveguide 15 (specifically, as shown in fig. 33 to fig. 36), and the forming method, parameters, and material selection of each step are described in the first embodiment, which is not repeated for brevity.

The thermo-optic phase shifter prepared by the preparation method can be used as a basic unit in a series of optical devices with phase change functions, such as a tunable micro-ring resonator, a micro-ring modulator, an optical switch, a Mach-Zehnder modulator and the like, is favorable for reducing the thermal modulation power consumption, and is favorable for improving the performance of related optical devices.

In summary, the present invention provides a method for fabricating a thermo-optic phase shifter based on an SOI substrate, the method comprising the steps of: forming a graphical SOI substrate, wherein the SOI substrate sequentially comprises a bottom silicon layer, an insulating layer and a top silicon layer from bottom to top, a groove is formed in the SOI substrate, the lower surface of the groove and the lower surface of the bottom silicon layer have a distance, namely the groove at least cannot penetrate through the bottom silicon layer, and the top silicon layer covers the groove; photoetching the top silicon layer above the groove to form a silicon waveguide; forming a dielectric layer, a heating resistor and a metal electrode; the dielectric layer at least covers the silicon waveguide; the heating resistor is positioned above the silicon waveguide or on one side of the silicon waveguide, and a distance is reserved between the heating resistor and the silicon waveguide; the metal electrode is connected with the heating resistor. According to the invention, the groove is formed below the position where the silicon waveguide is to be formed, so that the damage and water vapor diffusion of the silicon waveguide, which are easily caused in the traditional preparation method of hollowing after the silicon waveguide is formed, are avoided, and the production yield and the device performance are improved. The preparation method is simple, and can realize large-scale production through graphical customization of the SOI substrate, thereby being beneficial to further simplifying the preparation flow and reducing the production cost.

Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims

1. A method for fabricating a thermo-optic phase shifter based on an SOI substrate, the method comprising the steps of:

2. The method for manufacturing a thermo-optic phase shifter based on an SOI substrate according to claim 1, characterized in that: the groove is positioned in the bottom silicon layer, and the upper surface of the groove is flush with the lower surface of the insulating layer.

3. The method for manufacturing a thermo-optic phase shifter based on an SOI substrate according to claim 2, characterized in that: the horizontal area of the silicon waveguide is smaller than that of the groove; and completely etching the top silicon layer positioned at the periphery of the silicon waveguide to expose the insulating layer in the process of photoetching the top silicon layer above the groove to form the silicon waveguide.

4. The method of claim 3, wherein the heating resistor is a metal resistor, and the steps of forming the dielectric layer, the heating resistor and the metal electrode comprise:

5. The method of claim 3, wherein the heating resistor is a doped silicon resistor; the process of forming the silicon waveguide also comprises defining a heating resistance area at the same time, wherein the heating resistance area and the silicon waveguide are positioned on the same horizontal plane and have a distance with the silicon waveguide; the process of forming the dielectric layer, the heating resistor and the metal electrode comprises the following steps:

6. The method for manufacturing a thermo-optic phase shifter based on an SOI substrate according to claim 1, characterized in that: the recess runs through the insulating layer, the upper surface of recess with the lower surface looks parallel and level of top silicon layer, the lower surface of recess with the upper surface looks parallel and level of end silicon layer.

7. The method for manufacturing a thermo-optic phase shifter based on an SOI substrate according to claim 1, characterized in that: the groove penetrates through the insulating layer and extends downwards into the bottom silicon layer, and the upper surface of the groove is flush with the lower surface of the top silicon layer.

8. The method for manufacturing a thermo-optic phase shifter based on an SOI substrate according to claim 6 or 7, characterized in that: and the horizontal area of the silicon waveguide is smaller than that of the groove, and the top silicon layer positioned on the periphery of the silicon waveguide is partially etched in the process of photoetching the top silicon layer above the groove to form the silicon waveguide so that the groove is still covered by the top silicon layer.

9. The method of claim 8, wherein the heating resistor is a metal resistor; the process of forming the dielectric layer, the heating resistor and the metal electrode comprises the following steps:

10. The method of claim 8, wherein the heating resistor is a doped silicon resistor; the process of forming the silicon waveguide also comprises defining a heating resistance area at the same time, wherein the heating resistance area and the silicon waveguide are positioned on the same horizontal plane and have a distance with the silicon waveguide; the process of forming the dielectric layer, the heating resistor and the metal electrode comprises the following steps: