CN112286747A - Method, system, device and medium for detecting server cable - Google Patents
Method, system, device and medium for detecting server cable Download PDFInfo
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Abstract
The invention discloses a method, a system, equipment and a storage medium for detecting a server cable, wherein the method comprises the following steps: determining whether the cable to be tested placed between the first component and the second component is in a reference line sequence and meets the one-to-one relation between the pins at one end of the cable and the pins at the other end of the cable; the method comprises the steps that in response to the fact that a cable to be tested is in a reference line sequence and the condition that the pin at one end of the cable and the pin at the other end of the cable are in one-to-one relation is met, a first confirmation signal is sent from a sideband channel to a second part by a first part; responding to the second component to receive the first confirmation signal, and sequentially detecting whether each differential channel of the cable to be detected is conducted; and responding to the conduction of all the differential channels, and confirming the conduction of the cable to be tested. According to the invention, cable connectivity detection mechanisms with different modes are designed according to the requirements of different applications, the universality is very strong, and the test development and detection processes of common high-speed cables are greatly simplified.
Description
Technical Field
The present invention relates to the field of cable detection, and more particularly, to a method, a system, a computer device and a readable medium for detecting a server cable.
Background
With the continuous development of the internet artificial intelligence technology, the traditional server architecture is difficult to adapt to the changing data processing and data storage requirements. Increasing demand is constantly catalyzing, deriving various forms of server forms that fuse heterogeneous computing. The new heterogeneous computing server is improved to different degrees: on one hand, under the condition of complying with the size requirement of a standard rack, the height of a server case is continuously increased, and a larger space is designed in the server case to increase more computing units, heterogeneous acceleration modules, FPGA acceleration network cards, GPU processors and the like; on the other hand, the traditional management node is separated from the special accelerated computing node and the special storage node, and the management node is connected with the special extended computing node and the special storage node in an external system level and backed up.
However, in the design form of the integrated chassis or the interconnection among a plurality of system chassis, the traditional board-level interconnection mode is difficult to meet the design requirement, and a large number of high-speed interconnection cables are inevitably used as the transmission media between systems. The high-speed cables are various in types, and different combinations can be selected even in the same application. In view of this, selecting suitable cables to ensure the reliability of cable interconnection becomes a problem to be faced in board-level and cross-system level design.
At present, in other technical fields, there are some simple testing methods for cable detection, for example, voltage division is performed by using external resistors with different resistances in combination with Analog to Digital Converter (ADC), cable channel voltage is measured to determine cable on-off, a special encoder/decoder is externally designed by using micro programmed Control Unit (MCU), two logic changes 0/1 are implemented by using the encoder to determine cable on-off, and correctness of cable sequence is determined by combining several traversal modes.
Through the method of measuring the voltage value by the divider resistor and the analog-to-digital conversion, when the number of cable channels is large, a plurality of different divider resistance values need to be calculated, so that not only a large area of a test fixture PCB (printed circuit board) is occupied, but also the accuracy of the analog-to-digital conversion ADC is easily misjudged due to the accuracy of the resistance value, the power interference and the like.
The mode of MCU collocation encoder/decoder receives the influence of encoder/decoder digit width, will no longer be suitable for when cable channel quantity is great, and the coding relation is definite can not change in a flexible way moreover, corresponds the line sequence passageway and only uses 0/1 two kinds of invariable level logics, and under the condition that cable channel quantity is big, line sequence relation is changeable, encoder/decoder mechanism will no longer be suitable for.
In particular, the above approach is clearly not applicable when slim x4 has 38 pins and slim x8 has 74 pins.
In addition, a specific test fixture can be manufactured to test the connectivity of a specific high-speed cable, but once the cable sequence corresponding relation is changed, the cable sequence corresponding relation needs to be developed again, hardware equipment is modified, or software is optimized, and the cable sequence corresponding relation is limited to a certain extent under the condition of meeting multiple requirements of different application scenes.
Disclosure of Invention
In view of this, embodiments of the present invention provide a method, a system, a computer device, and a computer readable storage medium for detecting a server cable, which fully utilize the characteristics of rich resource and flexible programming of an Input/Output (IO) component, and develop a cable connectivity detection mechanism in different modes according to the requirements of different applications, so that the method has strong universality, avoids the problem of repeatedly developing a test fixture/test environment due to the special cable sequence, and greatly simplifies the test development and detection process of a commonly used high-speed cable.
Based on the above object, an aspect of the embodiments of the present invention provides a method for detecting a server cable, including the following steps: determining whether the cable to be tested placed between the first component and the second component is in a reference line sequence and meets the one-to-one relation between the pins at one end of the cable and the pins at the other end of the cable; responding to the fact that the cable to be tested is in a reference line sequence and meets the one-to-one relation between the pin at one end of the cable and the pin at the other end of the cable, and sending a first confirmation signal from the sideband channel to the second component by the first component; responding to the second component to receive the first confirmation signal, and sequentially detecting whether each differential channel of the cable to be detected is conducted; and responding to the conduction of all the differential channels, and confirming the conduction of the cable to be tested.
In some embodiments, the sequentially detecting whether each differential channel of the cable to be tested is conducted includes: and the first component sends a second confirmation signal to the second component from the first differential channel and judges whether the second component receives the second confirmation signal.
In some embodiments, the sequentially detecting whether each differential channel of the cable to be tested is conducted includes: in response to the second component receiving the second acknowledgement signal, the second component sends a third acknowledgement signal to the first component and determines whether the first component received the third acknowledgement signal.
In some embodiments, the sequentially detecting whether each differential channel of the cable to be tested is conducted includes: continuing to detect a next differential lane in response to the first component receiving the third acknowledgement signal.
In some embodiments, further comprising: responding to the fact that the cable to be tested is not in a reference line sequence but meets the one-to-one relation between the pin at one end of the cable and the pin at the other end of the cable, and sending confirmation data with pin codes to the second component by the first component; and analyzing the confirmation data in response to the second component receiving the confirmation data, and judging whether the cable is conducted or not based on the analyzed data.
In some embodiments, the determining whether the cable is conductive based on the parsed data comprises: and matching the analyzed pin codes with the pin codes of the first part, and judging whether the pin codes which are not successfully matched exist.
In some embodiments, further comprising: and responding to the condition that the cable to be tested is not in the reference line sequence and does not meet the one-to-one relationship between the pin at one end of the cable and the pin at the other end of the cable, sequentially sending confirmation data of each pin by the first component, and receiving and analyzing each confirmation data by the second component.
In another aspect of the embodiments of the present invention, a system for detecting a server cable is further provided, including: the reference module is configured to determine whether the cable to be tested placed between the first component and the second component is in a reference line sequence and meets the one-to-one relationship between the pins at one end of the cable and the pins at the other end of the cable; the first detection module is configured to respond to the fact that the cable to be detected is in a reference line sequence and meets the one-to-one relation between the pin at one end of the cable and the pin at the other end of the cable, and the first component sends a first confirmation signal to the second component from the sideband channel; the second detection module is configured to respond to the second component receiving the first confirmation signal and sequentially detect whether each differential channel of the cable to be detected is conducted or not; and the display module is configured to respond to the conduction of all the differential channels and confirm the conduction of the cable to be tested.
In another aspect of the embodiments of the present invention, there is also provided a computer device, including: at least one processor; and a memory storing computer instructions executable on the processor, the instructions when executed by the processor implementing the steps of the method as above.
In a further aspect of the embodiments of the present invention, a computer-readable storage medium is also provided, in which a computer program for implementing the above method steps is stored when the computer program is executed by a processor.
The invention has the following beneficial technical effects: by fully utilizing the characteristics of abundant IO (input/output) resources and flexible programming of parts, cable connectivity detection mechanisms in different modes are developed according to different application requirements, the universality is very strong, the problem of repeated development of test fixtures/test environments due to special cable line sequences is solved, and the test development and detection processes of common high-speed cables are greatly simplified.
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In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.
FIG. 1 is a schematic diagram of an embodiment of a method for detecting a server cable provided by the present invention;
FIG. 2 is a schematic topology diagram of server cable detection;
FIG. 3 is a schematic view of a cable detection unit interconnection topology;
fig. 4 is a schematic hardware structure diagram of an embodiment of the computer device for detecting a server cable provided in the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.
It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it should be noted that "first" and "second" are merely for convenience of description and should not be construed as limitations of the embodiments of the present invention, and they are not described in any more detail in the following embodiments.
In view of the above object, a first aspect of the embodiments of the present invention proposes an embodiment of a method for detecting a server cable. Fig. 1 is a schematic diagram illustrating an embodiment of a method for detecting a server cable provided by the present invention. As shown in fig. 1, the embodiment of the present invention includes the following steps:
s1, determining whether the cable to be tested placed between the first component and the second component is in a reference line sequence and meeting the one-to-one relation between the pins at one end of the cable and the pins at the other end of the cable;
s2, in response to the fact that the cable to be tested is in a reference line sequence and the condition that the pin at one end of the cable and the pin at the other end of the cable are in one-to-one relation, the first component sends a first confirmation signal to the second component from the sideband channel;
s3, responding to the second component receiving the first confirmation signal, and sequentially detecting whether each differential channel of the cable to be detected is conducted; and
and S4, responding to the conduction of all the differential channels, and confirming the conduction of the cable to be tested.
In the embodiment of the present invention, an FPGA (Field Programmable Gate Array) is used as a component for description, but this is not a limitation, and other components rich in IO resources are within the protection scope of the present invention.
The embodiment of the invention also discloses a high-speed cable detection device, FPGA modules are integrated on a detection support plate, unique IO ID codes are designed, two groups of FPGAs are interconnected through the high-speed cable, and the two groups of FPGAs are connected according to different modules: and automatically negotiating a bandwidth, a parallel mode and a single traversal mode, finishing data sending/receiving, encoding/decoding actions, and reporting the detection data to a LabVIEW upper computer through an Ethernet by one of the FPGAs, wherein the LabVIEW upper computer is responsible for controlling the whole detection process. Fig. 2 is a schematic topology diagram of server cable detection. As shown in fig. 2, the detection device mainly includes a detection carrier plate 1 and a LabVIEW upper computer software module 2. As shown in fig. 2, 10 groups of cable inspection units 1/2/…/9/10 with the same specification are integrated on the PCB, which can perform 10 groups of operations at a time, and each group of cable inspection units is composed of 2 FPGAs and high-speed connector ports, which are the main parts for completing the inspection logic; A100M Ethernet exchange chip module is integrated on the detection carrier plate, 10 100M Ethernet interfaces are designed to be respectively connected with 10 cable detection units, and 1 100M Ethernet interface is designed to be connected with an external LabVIEW upper computer to complete data exchange and data forwarding. The LabVIEW upper computer software module is interconnected with the cable detection support plate through an RJ45 cable, and has the main functions of controlling execution of a detection program, collecting and displaying detection data, comparing original data and storing and outputting the data.
Fig. 3 is a schematic diagram of a cable detection unit interconnection topology. As shown in fig. 3, the cable detection unit includes a first FPGA (FPGA module 1 in the figure) and a second FPGA (FPGA module 2 in the figure). Designing interconnection signals between the first FPGA and the second FPGA, comprising: two GPIOs (General Purpose Input/Output) are used for controlling the start and stop of the communication between the FPGAs; the SPI (Serial Peripheral Interface) is used by the FPGA module 2 to notify the FPGA module 1 of the current cable detection port type and the working mode; the FPGA module 2 is also responsible for packaging the test data and sending the test data to an upper computer through an Ethernet interface.
The inside, outside high-speed interconnection cable connector terminal of server that has designed commonly used on the detection support plate includes: vertical and quarter bend slim line x4/x8 cable connector terminals; internal, vertical and right angle bend MiniSAS HD x16 cable connector terminals; external MiniSAS HD x16 cable connector terminal.
The cable connector terminal IO is connected with the FPGA GPIO, wherein the slim signals of the x4 type are defined consistently, the two can be cascaded, and similarly, the slim x8 and the internal MiniSAS HD x16 are also cascaded, so that the occupation amount of the FPGA IO can be reduced by the same definition.
The two FPGA modules are respectively in a symmetrical design mode, and the FPGAs on the two sides are connected by using a cable to be tested. Before each test is started, an upper computer sends an instruction to the FPGA module 2, and the type of the test cable is selected.
The present embodiment is described below with reference to fig. 2 and 3:
and placing the cable to be tested between the first component and the second component, and determining whether the cable to be tested is in a reference line sequence and meets the one-to-one relation between the pins at one end of the cable and the pins at the other end of the cable. That is, the cable to be tested is placed between the first FPGA and the second FPGA, and before the cable is detected each time, the type of the cable to be tested and related parameters of the cable can be known, for example, whether the cable is a reference line sequence or not, and whether a pin at one end of the cable and a pin at the other end of the cable are in a one-to-one relationship or not.
And the first component sends a first confirmation signal to the second component from the sideband channel in response to the cable to be tested being in the reference line sequence and meeting the one-to-one relationship between the pin at one end of the cable and the pin at the other end of the cable. When the cable to be tested is in the reference line sequence and meets the one-to-one relationship between the pin at one end of the cable and the pin at the other end of the cable, an auto-negotiation bandwidth mode can be adopted. The first FPGA directly sends a level '1' to a sideband signal, and the second FPGA receives the level '1' and considers the sideband to be turned on.
And responding to the second component to receive the first confirmation signal, and sequentially detecting whether each differential channel of the cable to be detected is conducted.
In some embodiments, the sequentially detecting whether each differential channel of the cable to be tested is conducted includes: and the first component sends a second confirmation signal to the second component from the first differential channel and judges whether the second component receives the second confirmation signal.
In some embodiments, the sequentially detecting whether each differential channel of the cable to be tested is conducted includes: in response to the second component receiving the second acknowledgement signal, the second component sends a third acknowledgement signal to the first component and determines whether the first component received the third acknowledgement signal.
In some embodiments, the sequentially detecting whether each differential channel of the cable to be tested is conducted includes: continuing to detect a next differential lane in response to the first component receiving the third acknowledgement signal. For RX and TX signals, level "1" is first transmitted by the first FPGA on the TX1 channel, if the second FPGA receives level "1" correctly through RX1, level "1" is continuously transmitted by the second FPGA on the TX1 channel, and if the first FPGA receives level "1" correctly through RX1, the TX1 channel is on.
And responding to the conduction of all the differential channels, and confirming the conduction of the cable to be tested. Therefore, TX1/RX1 → TX2/RX2 is carried out until all the differential channels are detected, if a certain RX/TX in the midway fails to receive data normally, the detection is finished, and the data result is sent to the upper computer for processing by the second FPGA.
In some embodiments, further comprising: responding to the fact that the cable to be tested is not in a reference line sequence but meets the one-to-one relation between the pin at one end of the cable and the pin at the other end of the cable, and sending confirmation data with pin codes to the second component by the first component; and analyzing the confirmation data in response to the second component receiving the confirmation data, and judging whether the cable is conducted or not based on the analyzed data.
If the wire sequence of the wire is not a standard wire, but the relationship that the pin at one end of the wire and the pin at the other end of the wire are one-to-one is satisfied, the parallel mode can be adopted. At the moment, the first FPGA outputs a data byte sequence with a certain format on each connector port pin (pin), wherein the data byte sequence comprises a start/end code and an IO/pin code, the second FPGA is responsible for receiving and decoding the data on each pin and recording the data, and the FPGA IOs can be processed in parallel, so that cable channels are not influenced mutually.
In some embodiments, the determining whether the cable is conductive based on the parsed data comprises: and matching the analyzed pin codes with the pin codes of the first part, and judging whether the pin codes which are not successfully matched exist. If the pin codes which are not successfully matched exist, the fact that the non-conductive part exists in the cable to be tested is indicated.
In some embodiments, further comprising: and responding to the fact that the cable to be tested is not in a reference line sequence and does not meet the one-to-one relation between the pin at one end of the cable and the pin at the other end of the cable, the first FPGA sequentially sends the confirmation data of each pin, and the second FPGA receives and analyzes each confirmation data. If the cable to be tested does not know clear information, the condition that one pin at one end of the cable corresponds to a plurality of pins of the cable is existed because the line sequence is unknown and whether the one-to-one relationship between the pin at one end of the cable and the pin at the other end of the cable is met is not clear. In this scenario, the first FPGA outputs a data byte sequence of a certain format on each connector port pin in sequence each time, the second FPGA is responsible for receiving and decoding data on each pin, and recording the data, and since there is a non-unique correspondence between the pins, the traversal of each pin is only possible, so that the traversal method takes a long time. And after all the pins are detected, if the unmatched pins exist, the cable to be detected is not conducted.
LabVIEW upper computer software module composition and software execution flow:
(1) the ethernet port data processing module calls a TCP (Transmission Control Protocol)/IP (Internet Protocol) function, and is responsible for issuing a host computer Control instruction and analyzing and storing the received data returned by the FPGA module.
(2) The detection control and data display module is responsible for completing the functions of selecting a detection mode, detecting the type of a cable and controlling starting and stopping, and displaying the received return data on a window interface in an array form;
(3) the original data and comparison module calls an excel file opening function, can read excel file data typeset according to a certain format, compares the read cable terminal line sequence relation with the received array and displays a comparison result;
(4) and the data storage module is responsible for storing the received cable data result and outputting the cable data result to an excel file, so that the detection result can be conveniently stored and filed.
The method and the device fully utilize the characteristics of abundant FPGA IO resources and flexible programming, develop cable connectivity detection mechanisms in different modes according to the requirements of different applications, have strong universality, avoid the problem of repeatedly developing test fixtures/test environments due to special cable line sequences, and greatly simplify the test development and detection processes of the commonly used high-speed cables; in addition, the LabVIEW software development environment is adopted to develop the upper computer module, the visibility of a human-computer interaction interface is strong, the conventional development component is called, the independent development of different detection function interfaces can be realized, the function expansion is convenient, meanwhile, the functions of detecting data output excel, data comparison and the like can be realized, and the detection result can be conveniently filed.
It should be particularly noted that, the steps in the embodiments of the method for detecting a server cable described above can be mutually intersected, replaced, added, or deleted, and therefore, these methods for detecting a server cable that are reasonably changed in permutation and combination also belong to the scope of the present invention, and the scope of the present invention should not be limited to the embodiments.
In view of the above object, according to a second aspect of the embodiments of the present invention, there is provided a system for detecting a server cable, including: the reference module is configured to determine whether the cable to be tested placed between the first component and the second component is in a reference line sequence and meets the one-to-one relationship between the pins at one end of the cable and the pins at the other end of the cable; the first detection module is configured to respond to the fact that the cable to be detected is in a reference line sequence and meets the one-to-one relation between the pin at one end of the cable and the pin at the other end of the cable, and the first component sends a first confirmation signal to the second component from the sideband channel; the second detection module is configured to respond to the second component receiving the first confirmation signal and sequentially detect whether each differential channel of the cable to be detected is conducted or not; and the display module is configured to respond to the conduction of all the differential channels and confirm the conduction of the cable to be tested.
In some embodiments, the second detection module is configured to: and the first component sends a second confirmation signal to the second component from the first differential channel and judges whether the second component receives the second confirmation signal.
In some embodiments, the second detection module is configured to: in response to the second component receiving the second acknowledgement signal, the second component sends a third acknowledgement signal to the first component and determines whether the first component received the third acknowledgement signal.
In some embodiments, the second detection module is configured to: continuing to detect a next differential lane in response to the first component receiving the third acknowledgement signal.
In some embodiments, the system further comprises: the third detection module is configured to respond to the fact that the cable to be detected is not in a reference line sequence but meets the one-to-one relation between the pin at one end of the cable and the pin at the other end of the cable, and the first component sends confirmation data with the pin codes to the second component; and analyzing the confirmation data in response to the second component receiving the confirmation data, and judging whether the cable is conducted or not based on the analyzed data.
In some embodiments, the third detection module is configured to: and matching the analyzed pin codes with the pin codes of the first part, and judging whether the pin codes which are not successfully matched exist.
In some embodiments, the system further comprises: and the fourth detection module is configured to respond that the cable to be detected is not in a reference line sequence and does not meet the one-to-one relationship between the pin at one end of the cable and the pin at the other end of the cable, the first component sequentially sends the confirmation data of each pin, and the second component receives and analyzes each confirmation data.
In view of the above object, a third aspect of the embodiments of the present invention provides a computer device, including: at least one processor; and a memory storing computer instructions executable on the processor, the instructions being executable by the processor to perform the steps of: s1, determining whether the cable to be tested placed between the first component and the second component is in a reference line sequence and meeting the one-to-one relation between the pins at one end of the cable and the pins at the other end of the cable; s2, in response to the fact that the cable to be tested is in a reference line sequence and the condition that the pin at one end of the cable and the pin at the other end of the cable are in one-to-one relation, the first component sends a first confirmation signal to the second component from the sideband channel; s3, responding to the second component receiving the first confirmation signal, and sequentially detecting whether each differential channel of the cable to be detected is conducted; and S4, responding to the conduction of all the differential channels, and confirming the conduction of the cable to be tested.
In some embodiments, the sequentially detecting whether each differential channel of the cable to be tested is conducted includes: and the first component sends a second confirmation signal to the second component from the first differential channel and judges whether the second component receives the second confirmation signal.
In some embodiments, the sequentially detecting whether each differential channel of the cable to be tested is conducted includes: in response to the second component receiving the second acknowledgement signal, the second component sends a third acknowledgement signal to the first component and determines whether the first component received the third acknowledgement signal.
In some embodiments, the sequentially detecting whether each differential channel of the cable to be tested is conducted includes: continuing to detect a next differential lane in response to the first component receiving the third acknowledgement signal.
In some embodiments, the steps further comprise: responding to the fact that the cable to be tested is not in a reference line sequence but meets the one-to-one relation between the pin at one end of the cable and the pin at the other end of the cable, and sending confirmation data with pin codes to the second component by the first component; and analyzing the confirmation data in response to the second component receiving the confirmation data, and judging whether the cable is conducted or not based on the analyzed data.
In some embodiments, the determining whether the cable is conductive based on the parsed data comprises: and matching the analyzed pin codes with the pin codes of the first part, and judging whether the pin codes which are not successfully matched exist.
In some embodiments, the steps further comprise: and responding to the condition that the cable to be tested is not in the reference line sequence and does not meet the one-to-one relationship between the pin at one end of the cable and the pin at the other end of the cable, sequentially sending confirmation data of each pin by the first component, and receiving and analyzing each confirmation data by the second component.
Fig. 4 is a schematic hardware structure diagram of an embodiment of the computer device for detecting a server cable according to the present invention.
Taking the apparatus shown in fig. 4 as an example, the apparatus includes a processor 301 and a memory 302, and may further include: an input device 303 and an output device 304.
The processor 301, the memory 302, the input device 303 and the output device 304 may be connected by a bus or other means, and fig. 4 illustrates the connection by a bus as an example.
The memory 302 is a non-volatile computer-readable storage medium, and can be used for storing non-volatile software programs, non-volatile computer-executable programs, and modules, such as program instructions/modules corresponding to the method for detecting a server cable in the embodiment of the present application. The processor 301 executes various functional applications and data processing of the server by executing the nonvolatile software program, instructions and modules stored in the memory 302, that is, implements the method of detecting a server cable of the above-described method embodiment.
The memory 302 may include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function; the storage data area may store data created according to the use of the method of detecting the server cable, and the like. Further, the memory 302 may include high speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid state storage device. In some embodiments, memory 302 optionally includes memory located remotely from processor 301, which may be connected to a local module via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The input device 303 may receive information such as a user name and a password that are input. The output means 304 may comprise a display device such as a display screen.
Program instructions/modules corresponding to one or more methods of detecting a server cable are stored in the memory 302 and, when executed by the processor 301, perform the method of detecting a server cable in any of the above-described method embodiments.
Any embodiment of the computer device executing the method for detecting the server cable can achieve the same or similar effects as any corresponding method embodiment.
The invention also provides a computer readable storage medium storing a computer program which, when executed by a processor, performs the method as above.
Finally, it should be noted that, as one of ordinary skill in the art can appreciate that all or part of the processes of the methods of the above embodiments can be implemented by a computer program to instruct related hardware, and the program of the method for detecting a server cable can be stored in a computer readable storage medium, and when executed, the program can include the processes of the embodiments of the methods as described above. The storage medium of the program may be a magnetic disk, an optical disk, a Read Only Memory (ROM), a Random Access Memory (RAM), or the like. The embodiments of the computer program may achieve the same or similar effects as any of the above-described method embodiments.
The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.
The numbers of the embodiments disclosed in the embodiments of the present invention are merely for description, and do not represent the merits of the embodiments.
It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.
Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.
Claims (10)
1. A method of detecting a server cable, comprising the steps of:
determining whether the cable to be tested placed between the first component and the second component is in a reference line sequence and meets the one-to-one relation between the pins at one end of the cable and the pins at the other end of the cable;
responding to the fact that the cable to be tested is in a reference line sequence and meets the one-to-one relation between the pin at one end of the cable and the pin at the other end of the cable, and sending a first confirmation signal from the sideband channel to the second component by the first component;
responding to the second component to receive the first confirmation signal, and sequentially detecting whether each differential channel of the cable to be detected is conducted; and
and responding to the conduction of all the differential channels, and confirming the conduction of the cable to be tested.
2. The method of claim 1, wherein the sequentially detecting whether each differential channel of the cable under test is conductive comprises:
and the first component sends a second confirmation signal to the second component from the first differential channel and judges whether the second component receives the second confirmation signal.
3. The method of claim 2, wherein the sequentially detecting whether each differential channel of the cable under test is conductive comprises:
in response to the second component receiving the second acknowledgement signal, the second component sends a third acknowledgement signal to the first component and determines whether the first component received the third acknowledgement signal.
4. The method of claim 3, wherein the sequentially detecting whether each differential channel of the cable under test is conductive comprises:
continuing to detect a next differential lane in response to the first component receiving the third acknowledgement signal.
5. The method of claim 1, further comprising:
responding to the fact that the cable to be tested is not in a reference line sequence but meets the one-to-one relation between the pin at one end of the cable and the pin at the other end of the cable, and sending confirmation data with pin codes to the second component by the first component; and
and analyzing the confirmation data in response to the second component receiving the confirmation data, and judging whether the cable is conducted or not based on the analyzed data.
6. The method of claim 5, wherein determining whether the cable is conductive based on the parsed data comprises:
and matching the analyzed pin codes with the pin codes of the first part, and judging whether the pin codes which are not successfully matched exist.
7. The method of claim 1, further comprising:
and responding to the condition that the cable to be tested is not in the reference line sequence and does not meet the one-to-one relationship between the pin at one end of the cable and the pin at the other end of the cable, sequentially sending confirmation data of each pin by the first component, and receiving and analyzing each confirmation data by the second component.
8. A system for detecting a server cable, comprising:
the reference module is configured to determine whether the cable to be tested placed between the first component and the second component is in a reference line sequence and meets the one-to-one relationship between the pins at one end of the cable and the pins at the other end of the cable;
the first detection module is configured to respond to the fact that the cable to be detected is in a reference line sequence and meets the one-to-one relation between the pin at one end of the cable and the pin at the other end of the cable, and the first component sends a first confirmation signal to the second component from the sideband channel;
the second detection module is configured to respond to the second component receiving the first confirmation signal and sequentially detect whether each differential channel of the cable to be detected is conducted or not; and
and the display module is configured to respond to the conduction of all the differential channels and confirm the conduction of the cable to be tested.
9. A computer device, comprising:
at least one processor; and
a memory storing computer instructions executable on the processor, the instructions when executed by the processor implementing the steps of the method of any one of claims 1 to 7.
10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 7.
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| CN113671419A (en) * | 2021-08-17 | 2021-11-19 | 杭州佳量医疗科技有限公司 | Line sequence testing method, device and system |
| CN113740637A (en) * | 2021-07-28 | 2021-12-03 | 苏州浪潮智能科技有限公司 | Cable test fixture |
| CN113810071A (en) * | 2021-09-13 | 2021-12-17 | 上海星秒光电科技有限公司 | Self-adaptive line sequence adjusting method, device, equipment, system and storage medium |
| CN114006631A (en) * | 2021-09-17 | 2022-02-01 | 苏州浪潮智能科技有限公司 | Cable testing device and method based on code pattern signal verification |
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| CN108614178A (en) * | 2016-12-09 | 2018-10-02 | 英业达科技有限公司 | Conduction detecting system suitable for RJ45 connectors |
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| CN108614178A (en) * | 2016-12-09 | 2018-10-02 | 英业达科技有限公司 | Conduction detecting system suitable for RJ45 connectors |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113740637A (en) * | 2021-07-28 | 2021-12-03 | 苏州浪潮智能科技有限公司 | Cable test fixture |
| CN113740637B (en) * | 2021-07-28 | 2023-11-03 | 苏州浪潮智能科技有限公司 | Cable test fixture |
| CN113671419A (en) * | 2021-08-17 | 2021-11-19 | 杭州佳量医疗科技有限公司 | Line sequence testing method, device and system |
| CN113671419B (en) * | 2021-08-17 | 2024-05-24 | 杭州佳量医疗科技有限公司 | Line sequence testing method, device and system |
| CN113810071A (en) * | 2021-09-13 | 2021-12-17 | 上海星秒光电科技有限公司 | Self-adaptive line sequence adjusting method, device, equipment, system and storage medium |
| CN113810071B (en) * | 2021-09-13 | 2022-07-22 | 上海星秒光电科技有限公司 | Self-adaptive line sequence adjusting method, device, equipment, system and storage medium |
| CN114006631A (en) * | 2021-09-17 | 2022-02-01 | 苏州浪潮智能科技有限公司 | Cable testing device and method based on code pattern signal verification |
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| CN112286747B (en) | 2023-05-26 |
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