CN112272024A - Method and circuit for refreshing configuration data of FPGA device and storage medium - Google Patents

Method and circuit for refreshing configuration data of FPGA device and storage medium Download PDF

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CN112272024A
CN112272024A CN202011181814.1A CN202011181814A CN112272024A CN 112272024 A CN112272024 A CN 112272024A CN 202011181814 A CN202011181814 A CN 202011181814A CN 112272024 A CN112272024 A CN 112272024A
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configuration data
fpga
fpga device
refreshing
controlled
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CN112272024B (en
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朱志新
王佳承
何允灵
朱亚军
李铁明
刘鑫
李�昊
朱一骄
丁雪玲
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State Nuclear Power Automation System Engineering Co Ltd
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State Nuclear Power Automation System Engineering Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/1776—Structural details of configuration resources for memories
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G06F11/1402—Saving, restoring, recovering or retrying
    • G06F11/1446—Point-in-time backing up or restoration of persistent data
    • G06F11/1458—Management of the backup or restore process
    • G06F11/1469—Backup restoration techniques
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/17764—Structural details of configuration resources for reliability
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/17768—Structural details of configuration resources for security
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Security & Cryptography (AREA)
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Abstract

The invention discloses a method for refreshing configuration data of an FPGA device, which comprises the following steps: s11, storing a configuration data backup of the FPGA device; s12, detecting whether the configuration data of the FPGA device is wrong, if so, executing a step S13; and S13, refreshing the configuration data of the FPGA device by using the configuration data backup. According to the invention, by detecting the configuration data of the FPGA device, when the configuration data of the FPGA device is wrong, the configuration data of the FPGA device is acquired from the configuration data storage chip for backup and the configuration data of the FPGA device is refreshed, so that the configuration data error of the FPGA device can be found and corrected in a short time, the efficiency of detecting the configuration data and correcting the error is improved, the working reliability of the FPGA device is improved, and the safety is improved.

Description

Method and circuit for refreshing configuration data of FPGA device and storage medium
Technical Field
The invention relates to the technical field of industrial control, in particular to a method and a circuit for refreshing configuration data of an FPGA device and a storage medium.
Background
A Field Programmable Gate Array (FPGA) device with a Static Random-Access Memory (SRAM) structure is configured to read configuration data into an on-chip SRAM when the FPGA device is powered on, and enter a working state after the configuration data is read. After the FPGA device is powered off, configuration data in the SRAM in the chip is lost, and the internal logic relation of the FPGA device disappears. When the FPGA device works in a radiation environment (such as nuclear power), the on-chip SRAM is easily influenced by single event upset (namely bit upset), so that bits in a storage unit are overturned, and stored data is wrong and functions are lost.
Configuration data in an on-chip SRAM of the FPGA device is easy to generate errors (including loss), once the errors occur, the configuration data can be found only after a long time, the configuration data loaded in the FPGA device needs to be refreshed manually, the efficiency of detecting the configuration data and correcting the configuration data is low, the working reliability of the FPGA device is reduced, and the safety is reduced.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a method, a circuit and a storage medium for refreshing configuration data of an FPGA device, aiming at overcoming the defects that configuration data in an on-chip SRAM of the FPGA device in the prior art is easy to generate errors (including loss), and once the configuration data is generated, the configuration data can be found in a long time, the configuration data loaded in the FPGA device needs to be refreshed manually, the working reliability of the FPGA device is reduced, the efficiency of detecting the configuration data and correcting errors is low, and the safety is reduced.
The invention solves the technical problems through the following technical scheme:
the invention provides a method for refreshing configuration data of an FPGA device, which comprises the following steps:
s11, storing a configuration data backup of the FPGA device;
s12, detecting whether the configuration data of the FPGA device is wrong, if so, executing a step S13;
and S13, refreshing the configuration data of the FPGA device by using the configuration data backup.
Preferably, step S12 includes the following steps:
and comparing whether the configuration data of the FPGA device is the same as the configuration data backup of the corresponding FPGA device.
Preferably, the FPGA device includes a master FPGA and a controlled FPGA;
step S11 specifically includes:
storing the configuration data backup of the main control FPGA in a first storage chip, and storing the configuration data backup of the controlled FPGA in a second storage chip;
step S12 specifically includes:
detecting whether the configuration data of the main control FPGA is wrong, if so, executing a step S13;
and the master control FPGA detects whether the configuration data of the controlled FPGA is wrong, and if so, the step S13 is executed.
Preferably, a plurality of controlled FPGAs are connected in sequence to form a cascade controlled FPGA;
step S12 further includes:
and the master control FPGA detects whether configuration data of any controlled FPGA in the cascade controlled FPGAs are wrong, and if so, the step S13 is executed.
Preferably, after step S13, the method for refreshing configuration data further includes the following steps:
and S14, after finishing refreshing the configuration data of the corresponding FPGA device, the FPGA device generates a refreshing operation finishing indication signal.
The invention also provides a system for refreshing the configuration data of the FPGA device, which comprises at least one FPGA device, a refreshing module and a first memory chip;
the refreshing module is electrically connected with the FPGA device and the first storage chip respectively;
the first storage chip is used for storing the configuration data backup of the FPGA device;
the refreshing module is used for detecting whether configuration data of the FPGA device is wrong or not, and if yes, the configuration data of the FPGA device is refreshed by using the configuration data backup.
Preferably, the refresh module is configured to compare whether the configuration data of the FPGA device is the same as the configuration data backup of the corresponding FPGA device, and if not, use the configuration data backup to refresh the configuration data of the FPGA device.
Preferably, the FPGA device includes a master FPGA and a controlled FPGA;
the refresh system further comprises a second memory chip;
the main control FPGA is electrically connected with the refreshing module, the second storage chip and the controlled FPGA respectively;
the first storage chip is used for storing the configuration data backup of the master control FPGA, and the second storage chip is used for storing the configuration data backup of the controlled FPGA;
the refreshing module comprises a first detection unit and a first refreshing unit, wherein the first detection unit is used for detecting whether the configuration data of the main control FPGA is wrong, if yes, the first refreshing unit is called to use the configuration data backup to refresh the configuration data of the main control FPGA;
the main control FPGA comprises a second detection unit and a second refreshing unit, wherein the second detection unit is used for detecting whether the configuration data of the controlled FPGA is wrong or not, and if yes, the second refreshing unit is called to use the configuration data to backup and refresh the configuration data of the controlled FPGA.
Preferably, a plurality of controlled FPGAs are connected in sequence to form a cascade controlled FPGA;
the second detection unit is further configured to detect whether configuration data of any controlled FPGA in the cascaded controlled FPGAs is in error, and if yes, invoke the second refresh unit to refresh the configuration data of the controlled FPGA by using the configuration data backup.
Preferably, the FPGA device further includes a signal generating unit;
and after the configuration data of the corresponding FPGA device is refreshed, the signal generating unit generates a refresh operation completion indicating signal.
The present invention also provides a computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the method for refreshing configuration data of an FPGA device as described above.
The positive progress effects of the invention are as follows: by detecting the configuration data of the FPGA device, when the configuration data of the FPGA device is wrong, the configuration data backup of the FPGA device is obtained from the configuration data storage chip and the configuration data of the FPGA device is refreshed, so that the configuration data error of the FPGA device can be found and corrected in a short time, the efficiency of detecting the configuration data and correcting the error is improved, the working reliability of the FPGA device is improved, and the safety is improved.
Drawings
Fig. 1 is a schematic flowchart of a method for refreshing configuration data of an FPGA device in embodiment 1.
Fig. 2 is a schematic flowchart of another implementation manner of the method for refreshing configuration data of an FPGA device in embodiment 1.
Fig. 3 is a schematic flowchart of a method for refreshing configuration data of an FPGA device in embodiment 2.
Fig. 4 is a schematic flowchart of a method for refreshing configuration data of an FPGA device according to embodiment 3.
Fig. 5 is a block diagram of a system for refreshing configuration data of an FPGA device of embodiment 4.
Fig. 6 is a block diagram showing a system for refreshing configuration data of an FPGA device according to embodiment 5.
Fig. 7 is a block diagram showing a system for refreshing configuration data of an FPGA device of embodiment 6.
Detailed Description
The invention is further illustrated by the following examples, which are not intended to limit the scope of the invention.
Example 1
The embodiment provides a method for refreshing configuration data of an FPGA device. Referring to fig. 1, the refresh method includes the steps of:
and S11, storing the configuration data backup of the FPGA device.
S12, detecting whether the configuration data of the FPGA device is wrong, if so, executing a step S13.
And S13, refreshing the configuration data of the FPGA device by using the configuration data backup.
And S14, after finishing refreshing the configuration data of the corresponding FPGA device, the FPGA device generates a refreshing operation finishing indication signal.
In step S14, the FPGA device may complete the refresh operation by a refresh operation completion indication signal indicating that the refresh of the configuration data is completed.
According to the method for refreshing the configuration data of the FPGA device, the configuration data of the FPGA device is acquired from the configuration data storage chip and backed up and refreshed when the configuration data of the FPGA device is wrong by detecting the configuration data of the FPGA device, so that the configuration data error of the FPGA device can be found and corrected in a short time, the efficiency of detecting the configuration data and correcting the error is improved, the working reliability of the FPGA device is improved, and the safety is improved.
Referring to fig. 2, step S12 specifically includes the following steps:
and S121, comparing whether the configuration data of the FPGA device is the same as the configuration data backup of the corresponding FPGA device.
If not, it indicates that the configuration data of the FPGA device is in error, and step S13 is executed.
According to the method for refreshing the configuration data of the FPGA device, by detecting the configuration data of the FPGA device, when the configuration data of the FPGA device is different from the configuration data backup, the configuration data backup of the FPGA device is obtained from the configuration data storage chip and the configuration data of the FPGA device is refreshed, so that the configuration data error of the FPGA device can be found and corrected in a short time, the efficiency of detecting the configuration data and correcting the error is improved, the working reliability of the FPGA device is improved, and the safety is improved.
Example 2
The method for refreshing configuration data of an FPGA device of this embodiment is a further improvement of embodiment 1, and specifically includes:
the FPGA device comprises a main control FPGA and a controlled FPGA.
Referring to fig. 3, step S11 specifically includes:
and S111, storing the configuration data backup of the main control FPGA in the first storage chip, and storing the configuration data backup of the controlled FPGA in the second storage chip.
Step S12 specifically includes:
and S122, detecting whether the configuration data of the main control FPGA is wrong, and if so, executing the step S13.
And S123, the main control FPGA detects whether the configuration data of the controlled FPGA is wrong, and if so, the step S13 is executed.
If the configuration data of the main control FPGA is wrong, the configuration data of the main control FPGA is refreshed in step S13; if the configuration data of the controlled FPGA is incorrect, the configuration data of the controlled FPGA is refreshed in step S13.
According to the method for refreshing the configuration data of the FPGA device, under the condition that the configuration data error of the main control FPGA is monitored and corrected, the configuration data error of the controlled FPGA is monitored and corrected by the main control FPGA, so that the configuration data error of the main control FPGA and the controlled FPGA can be found and corrected in a short time, the efficiency of detecting the configuration data and correcting the configuration data is further improved, the working reliability of the FPGA device is improved, and the safety is improved.
Example 3
The method for refreshing configuration data of an FPGA device of this embodiment is a further improvement of embodiment 2, and specifically includes:
and the plurality of controlled FPGAs are sequentially connected to form a cascade controlled FPGA.
Referring to fig. 4, step S12 further includes:
and S124, the master control FPGA detects whether configuration data of any controlled FPGA in the cascade controlled FPGAs are wrong, and if yes, the step S13 is executed.
The method for refreshing the configuration data of the FPGA device further enriches the connection mode of the controlled FPGA, and can monitor and correct configuration data errors of any controlled FPGA in the cascaded controlled FPGA.
Example 4
The embodiment provides a system for refreshing configuration data of an FPGA device. Referring to fig. 5, the refresh system includes at least one FPGA device 1, a refresh module 2, and a first memory chip 3.
The refreshing module 2 is electrically connected with the FPGA device 1 and the first memory chip 3 respectively.
The first memory chip 3 is used for storing configuration data backup of the FPGA device 1.
The refreshing module 2 is used for detecting whether the configuration data of the FPGA device 1 is wrong, and if so, the configuration data of the FPGA device 1 is refreshed by using the configuration data backup.
In specific implementation, the refreshing module 2 is configured to compare whether the configuration data of the FPGA device 1 is the same as the configuration data backup of the corresponding FPGA device 1, and if not, use the configuration data backup to refresh the configuration data of the FPGA device 1. If the configuration data of the FPGA device 1 is different from the configuration data backup of the corresponding FPGA device 1, it indicates that the configuration data of the FPGA device 1 is wrong.
According to the system for refreshing the configuration data of the FPGA device, the configuration data of the FPGA device is acquired from the configuration data storage chip and backed up and the configuration data of the FPGA device is refreshed when the configuration data of the FPGA device is wrong by detecting the configuration data of the FPGA device, so that the configuration data error of the FPGA device can be found and corrected in a short time, the efficiency of detecting the configuration data and correcting the error is improved, the working reliability of the FPGA device is improved, and the safety is improved.
Example 5
The system for refreshing configuration data of an FPGA device of this embodiment is a further improvement of embodiment 4, specifically:
referring to fig. 6, the FPGA device 1 includes a main control FPGA11 and a controlled FPGA12, the refresh system further includes a second memory chip 4, the refresh module 2 includes a first detection unit 21 and a first refresh unit 22, and the main control FPGA11 includes a second detection unit 23 and a second refresh unit 24.
The main control FPGA11 is electrically connected with the refresh module 2, the second memory chip 4 and the controlled FPGA12 respectively.
The first storage chip 3 is used for storing the configuration data backup of the master control FPGA11, and the second storage chip 4 is used for storing the configuration data backup of the controlled FPGA 12.
The first detecting unit 21 is configured to detect whether the configuration data of the main control FPGA11 is in error, and if yes, invoke the first refreshing unit 22 to refresh the configuration data of the main control FPGA11 by using the configuration data backup.
The second detecting unit 23 is configured to detect whether the configuration data of the controlled FPGA12 is in error, and if yes, invoke the second refreshing unit 24 to use the configuration data to backup and refresh the configuration data of the controlled FPGA 12.
According to the system for refreshing the configuration data of the FPGA device, under the condition that the configuration data error of the main control FPGA is monitored and corrected, the configuration data error of the controlled FPGA is monitored and corrected by the main control FPGA, so that the configuration data error of the main control FPGA and the controlled FPGA can be found and corrected in a short time, the efficiency of detecting the configuration data and correcting the configuration data is further improved, the working reliability of the FPGA device is improved, and the safety is improved.
Example 6
The system for refreshing configuration data of an FPGA device of this embodiment is a further improvement of embodiment 5, specifically:
referring to fig. 7, a plurality of controlled FPGAs 12 are connected in sequence to form a cascaded controlled FPGA 13.
The second detecting unit 23 is further configured to detect whether an error occurs in the configuration data of any controlled FPGA12 in the cascaded controlled FPGAs 13, and if so, invoke the second refreshing unit 24 to use the configuration data to backup and refresh the configuration data of the controlled FPGA 12.
The system for refreshing the configuration data of the FPGA device further enriches the connection mode of the controlled FPGA, and can monitor and correct configuration data errors of any controlled FPGA in the cascaded controlled FPGA.
In an embodiment, the FPGA device 1 further includes a signal generating unit, and after the configuration data of the corresponding FPGA device 1 is refreshed, the signal generating unit generates a refresh operation completion indication signal.
In specific implementation, when the refresh module 2 detects that the configuration data of the FPGA device 1 is incorrect, the FPGA device 1 sends a refresh operation completion indication signal to the refresh module 2 after finishing refreshing the configuration data. When the master FPGA11 detects an error in the configuration data of the controlled FPGA12, the controlled FPGA12 sends a refresh operation completion indication signal to the master FPGA11 after the configuration data is refreshed.
In the system for refreshing configuration data of an FPGA device of this embodiment, the FPGA device may complete the refresh of the configuration data by a refresh operation completion indication signal.
Example 7
The present embodiment provides a computer-readable storage medium on which a computer program is stored, the computer program, when executed by a processor, implementing the steps of the method for refreshing configuration data of an FPGA device in any one of embodiment 1, embodiment 2, or embodiment 3.
More specific examples, among others, that the readable storage medium may employ may include, but are not limited to: a portable disk, a hard disk, random access memory, read only memory, erasable programmable read only memory, optical storage device, magnetic storage device, or any suitable combination of the foregoing.
In a possible implementation manner, the present invention can also be implemented in the form of a program product, which includes program code for causing a terminal device to execute steps of implementing a method for refreshing configuration data of an FPGA device in any one of embodiment 1, embodiment 2, or embodiment 3, when the program product is run on the terminal device.
Where program code for carrying out the invention is written in any combination of one or more programming languages, the program code may be executed entirely on the user device, partly on the user device, as a stand-alone software package, partly on the user device and partly on a remote device or entirely on the remote device.
While specific embodiments of the invention have been described above, it will be appreciated by those skilled in the art that this is by way of example only, and that the scope of the invention is defined by the appended claims. Various changes and modifications to these embodiments may be made by those skilled in the art without departing from the spirit and scope of the invention, and these changes and modifications are within the scope of the invention.

Claims (11)

1. A method for refreshing configuration data of an FPGA device is characterized by comprising the following steps:
s11, storing a configuration data backup of the FPGA device;
s12, detecting whether the configuration data of the FPGA device is wrong, if so, executing a step S13;
and S13, refreshing the configuration data of the FPGA device by using the configuration data backup.
2. The method for refreshing configuration data of an FPGA device as claimed in claim 1, wherein the step S12 includes the steps of:
and comparing whether the configuration data of the FPGA device is the same as the configuration data backup of the corresponding FPGA device.
3. The method of refreshing configuration data of an FPGA device of claim 1, wherein the FPGA device comprises a master FPGA and a controlled FPGA;
step S11 specifically includes:
storing the configuration data backup of the main control FPGA in a first storage chip, and storing the configuration data backup of the controlled FPGA in a second storage chip;
step S12 specifically includes:
detecting whether the configuration data of the main control FPGA is wrong, if so, executing a step S13;
and the master control FPGA detects whether the configuration data of the controlled FPGA is wrong, and if so, the step S13 is executed.
4. The method for refreshing configuration data of an FPGA device as recited in claim 3, wherein a plurality of said controlled FPGAs are connected in sequence to form a cascade controlled FPGA;
step S12 further includes:
and the master control FPGA detects whether configuration data of any controlled FPGA in the cascade controlled FPGAs are wrong, and if so, the step S13 is executed.
5. The method for refreshing configuration data of an FPGA device as recited in claim 1, wherein after step S13, the method for refreshing configuration data further comprises the steps of:
and S14, after finishing refreshing the configuration data of the corresponding FPGA device, the FPGA device generates a refreshing operation finishing indication signal.
6. A refreshing system of configuration data of an FPGA device is characterized by comprising at least one FPGA device, a refreshing module and a first storage chip;
the refreshing module is electrically connected with the FPGA device and the first storage chip respectively;
the first storage chip is used for storing the configuration data backup of the FPGA device;
the refreshing module is used for detecting whether configuration data of the FPGA device is wrong or not, and if yes, the configuration data of the FPGA device is refreshed by using the configuration data backup.
7. The system of claim 6, wherein the refresh module is configured to compare whether the configuration data of the FPGA device is the same as the corresponding configuration data backup of the FPGA device, and if not, to refresh the configuration data of the FPGA device using the configuration data backup.
8. The system for refreshing configuration data of an FPGA device of claim 6, wherein said FPGA device comprises a master FPGA and a controlled FPGA;
the refresh system further comprises a second memory chip;
the main control FPGA is electrically connected with the refreshing module, the second storage chip and the controlled FPGA respectively;
the first storage chip is used for storing the configuration data backup of the master control FPGA, and the second storage chip is used for storing the configuration data backup of the controlled FPGA;
the refreshing module comprises a first detection unit and a first refreshing unit, wherein the first detection unit is used for detecting whether the configuration data of the main control FPGA is wrong, if yes, the first refreshing unit is called to use the configuration data backup to refresh the configuration data of the main control FPGA;
the main control FPGA comprises a second detection unit and a second refreshing unit, wherein the second detection unit is used for detecting whether the configuration data of the controlled FPGA is wrong or not, and if yes, the second refreshing unit is called to use the configuration data to backup and refresh the configuration data of the controlled FPGA.
9. The system for refreshing configuration data of an FPGA device of claim 8, wherein a plurality of said controlled FPGAs are connected in sequence to form a cascaded controlled FPGA;
the second detection unit is further configured to detect whether configuration data of any controlled FPGA in the cascaded controlled FPGAs is in error, and if yes, invoke the second refresh unit to refresh the configuration data of the controlled FPGA by using the configuration data backup.
10. The system for refreshing configuration data of an FPGA device of claim 6, wherein said FPGA device further comprises a signal generating unit;
and after the configuration data of the corresponding FPGA device is refreshed, the signal generating unit generates a refresh operation completion indicating signal.
11. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the method for refreshing configuration data of an FPGA device of any one of claims 1 to 5.
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