WO2023273146A1

WO2023273146A1 - Data processing apparatus, system, method, and board card

Info

Publication number: WO2023273146A1
Application number: PCT/CN2021/134517
Authority: WO
Inventors: 黄炎坡
Original assignee: 深圳市商汤科技有限公司
Priority date: 2021-06-29
Filing date: 2021-11-30
Publication date: 2023-01-05
Also published as: CN113344767A

Abstract

A data processing apparatus, system, method, and board card. The data processing apparatus (100) comprises: a multiplexer (20) which, in response to receiving a port gating signal, is used to gate a first transmission path or a second transmission path of a data processing chip (10) which are used to acquire configuration information; and the data processing chip, which is used to acquire first configuration information in response to the first transmission path being gated, and determine its own mode to be a master control mode on the basis of the first configuration information, and to acquire second configuration information in response to the second transmission path being gated, and determine its own mode to be a controlled mode on the basis of the second configuration information. In this way, a functional limitation on a data processing chip can be eliminated, so that the data processing chip can switch its own mode according to actual need, improving stability of a data processing apparatus.

Description

Data processing device, system, method and board

Cross References to Related Applications

This patent application claims the priority of the Chinese patent application with the application number 202110727748.1 and the invention title "data processing device, system, board, method, electronic equipment and storage medium" filed on June 29, 2021. The application Incorporated into the text by reference.

technical field

The present disclosure relates to the field of computer technology, in particular, to a data processing device, system, method and board.

Background technique

When processing data such as images, a central processing unit (CPU) is usually used as the main control chip, supplemented by an artificial intelligence (AI) accelerator card chip as an accelerator card, and a "CPU+AI acceleration chip" is constructed. Card" hardware architecture to achieve data processing, thereby effectively improving the speed of data processing. However, once the CPU as the main control chip breaks down, data processing cannot be performed normally, resulting in poor stability of the hardware architecture.

Contents of the invention

Embodiments of the present disclosure at least provide a data processing device, system, method and board.

In a first aspect, an embodiment of the present disclosure provides a data processing device, including: a data processing chip and a multiplexer; wherein the multiplexer is configured to select a The data processing chip is used to obtain the first transmission path or the second transmission path of the configuration information; the data processing chip is used to respond to the first transmission path being gated, and obtain the first configuration information, based on the The first configuration information is used to determine its own mode as the master mode; in response to the second transmission path being selected, the second configuration information is obtained, and based on the second configuration information, its own mode is determined as the controlled mode .

In this way, by switching the data processing chip in the data processing device to the main control mode or the controlled mode under different circumstances, it is possible to get rid of the functional restrictions on the data processing chip in the traditional data processing device, and the data processing chip can be used according to the actual situation. It needs to switch its own mode to improve the stability of the data processing device.

In an optional implementation manner, the data processing chip is further configured to decompose the data processing task into multiple subtasks in response to receiving the data processing task when its own mode is in the master control mode, and send Other data processing devices in the controlled mode issue the subtasks; or the data processing chip is further configured to respond to receiving the subtask from other data processing devices in the master mode when its own mode is in the controlled mode. The delivered subtasks execute the subtasks delivered by the other data processing devices.

In this way, the data processing chip whose own mode is in the master control mode can play a controlling role, and deliver subtasks corresponding to data processing tasks to other data processing devices in the controlled mode. For a data processing chip whose self-mode is in the controlled mode, it can perform specific tasks of data processing. When there are multiple data processing chips in the controlled mode, the data processing chips in the controlled mode can be parallel Data processing is performed on corresponding subtasks, so the efficiency of data processing is high.

In an optional implementation manner, the data processing device further includes: a first memory and a second memory; wherein, the first memory and the second memory are respectively connected to the multiplexer; The multiplexer is configured to gate the first transmission path between the data processing chip and the first memory, or gate the data processing chip and the A second transmission path between the second memories.

In this way, by setting the first memory and the second memory, when the data processing chip in the data processing device switches its own mode, it only needs to gate the transmission path corresponding to the memory in the corresponding mode, which is more convenient and can also effectively improve the data quality. The efficiency with which a data processing chip in a processing device switches its mode.

In an optional implementation manner, the data processing device further includes: the signal converter is connected to the multiplexer; and is connected to the controller; the signal converter is used to The communication protocol receives the control command sent by the controller, converts the control command into a port gating signal, and sends the port gating signal to the multiplexer.

In this way, by setting the signal converter, the control command sent by the controller can be received, and the control command can be effectively converted into a port strobe signal, and sent to the multiplexer.

In an optional implementation manner, the data processing device further includes: a monitoring chip; the monitoring chip is respectively connected to the data processing chip and the signal converter; the monitoring chip is used to monitor the data Processing the working state of the chip, and sending a monitoring signal corresponding to the working state to the signal converter; the signal converter is also used to receive the monitoring signal sent by the monitoring chip, and based on a preset A second communication protocol sends the monitoring signal to the controller.

In this way, by setting the monitoring chip, convenient and accurate monitoring of the data processing chip can be realized, so as to determine the working state of the data processing chip.

In an optional implementation manner, the data processing device further includes: a register; the register is used to store type information of the data processing chip.

In this way, by setting the register, the type information of the data processing chip can be stored in the register in advance, so that the controller can directly know the type of the corresponding data processing chip through the register, without having to repeat it every time the type is checked The detection is more efficient.

In the second aspect, the embodiment of the present disclosure also provides a data processing system, including: the data processing device provided in the embodiment of the present disclosure, and a controller; wherein, there are multiple data processing devices; multiple data processing devices It includes: a first data processing device in a master mode, and a second data processing device in a controlled mode; the controller is configured to monitor the state of the first data processing device; responding to the state Instructing to switch the first data processing device to a controlled mode, sending a first control instruction to the first data processing device, and sending a second control instruction to a target second data processing device; the first data processing device , configured to switch its own mode to a controlled mode in response to receiving a first control instruction; the target second data processing device is configured to switch its own mode to a master mode in response to receiving a second control instruction.

In this way, in the case of failure of the data processing device in the master mode in the data processing system, other data processing devices in the controlled mode can switch to the master mode, and continue to assume the responsibility of the data processing device in the master mode. function, so as to ensure the normal and stable operation of the data processing system.

In an optional implementation manner, the state of the data processing device includes at least one of the following: working state; data path state.

In an optional implementation manner, the controller, when monitoring the state of the first data processing device, is configured to: receive a monitoring signal sent by the first data processing device; , determining the working state of the first data processing device; determining whether to switch the first data processing device to a controlled mode based on the working state of the first data processing device.

In this way, by monitoring the working state of the first data processing device, it can be quickly determined whether the data processing system can currently work normally; A data processing device is switched to the controlled mode, which can respond to the failure of the data processing system in an emergency, and the stability is stronger.

In an optional implementation manner, the data processing system further includes: a communication switch; multiple data processing devices are respectively connected to the controller through the communication switch; When monitoring the state of a data processing device, it is used to: monitor the state of the data path between the first data processing device and the communication switch; based on the data between the first data processing device and the communication switch A channel state, determining whether to switch the first data processing device to a controlled mode.

In this way, by setting the communication switch, the state of the data path between the first data processing device and the communication switch can be monitored, and when the state of the data path is abnormal, it is determined to switch the first data processing device to the controlled mode. In this way, when the data path is not normal, the self mode of the first data processing device can be switched to ensure that the data path of the first data processing device is normal, thereby ensuring that the data processing device in the master mode can pass the subtask normally. The data path is delivered to other data processing devices.

In an optional implementation manner, the controller, when monitoring the state of the first data processing device, is configured to: in response to the state of the first data processing device being an abnormal state, determine that the The first data processing device switches to a controlled mode.

In an optional implementation manner, the controller, before sending the second control instruction to the target second data processing device, is further configured to: based on the state of the second data processing device, from the second data processing device In the processing device, a target second data processing device to switch to the master mode is determined.

In an optional implementation manner, the controller, based on the state of the second data processing device, determines from among the second data processing devices the target second data processing device to be switched to the master mode when the state of the first data processing device is abnormal, determine the candidate data processing device from the second data processing device, and detect the state of the candidate data processing device; in response The state of the candidate data processing device is a normal state, and the candidate data processing device is determined as the target second data processing device; the controller is further configured to: respond to the candidate data processing device If the state of the data processing device is abnormal, determine a new candidate data processing device from the second data processing device, and return to the step of detecting whether the state of the candidate data processing device is normal.

In this way, by first determining whether the state of the candidate data processing device is normal, and then determining whether it can be used as the target second data processing device, it is possible to avoid directly switching the candidate data processing device to the target second data processing device. If the selected data processing device still cannot normally complete the decomposition and distribution of data processing tasks, it can accurately determine the data processing device that can switch to the master mode and execute the data processing tasks in this mode, so it can avoid It is more efficient to switch multiple data processing devices repeatedly.

In an optional implementation manner, the controller, when determining from the second data processing device a target second data processing device to be switched to the master mode, is further configured to, from the alternative Reading type information from the data processing device; in response to the read type information being preset type information, determining the candidate data processing device as the target second data processing device.

In this way, the controller can also determine the type information of the candidate data processing device, so as to prevent the data processing device that cannot perform the data processing task in the master control mode from switching its own mode to the master control mode, causing the data processing system to fail to continue to work normally. Or multiple times of frequent switching of the candidate data processing device as the data processing device in the master control mode.

In an optional implementation manner, when the controller sends the first control instruction to the first data processing device and sends the second control instruction to the target second data processing device, it is configured to: A data processing device and the target second data processing device send a reset signal; after the reset signal is sent successfully, send a first control instruction to the first data processing device, and send a second control instruction to the target second data processing device control instruction; the first data processing device, when switching its own mode to the controlled mode in response to receiving the first control instruction, is used to: execute reset in response to receiving the reset signal; and complete the reset Afterwards, in response to receiving the first control instruction, switch its own mode to the controlled mode; when the target second data processing device switches its own mode to the master mode in response to receiving the second control instruction , configured to perform a reset in response to receiving the reset signal; and switch its own mode to a master mode in response to receiving the second control instruction after the reset is completed.

In this way, through the controller sending a reset signal to the first data processing device and the target second data processing device, the first data processing device and the target second data processing device can release the current self-mode, so that the first data processing device and the target When the second data processing device switches its own mode, it can be realized directly by gating the transmission path between its corresponding data processing chip and the first memory or the second memory, so that the first data processing device can be relatively simply The device and the target data processing device complete the switching of their own modes, and effectively reduce the occurrence of switching failures during switching.

In an optional implementation manner, the controller is further configured to: in response to receiving a successful handover signal sent by the first data processing device and the target second data processing device, send a message to the first data processing device The data processing device and the target second data processing device send a reset release signal; the first data processing device releases the reset in response to receiving the reset release signal; the target second data processing device responds to The reset is released upon receiving the reset release signal.

In this way, after the first data processing device and the target second data processing device are released from reset, the target second data processing device can continue to receive data processing tasks based on its own mode as the master mode, and decompose it into subtasks; similarly , the first data processing device may process the received subtasks based on its own mode as the controlled mode, so that the data processing system can continue to complete the corresponding data processing tasks, so as to restore the normal data processing state of the data processing system.

In an optional implementation manner, the controller is also connected to the data processing device through a bus; the controller sends a reset signal to the first data processing device and the target second data processing device , configured to: send a reset signal to the first data processing device and the target second data processing device through the bus.

In the third aspect, the embodiments of the present disclosure further provide a board, the board includes the first aspect of the present disclosure and any implementation thereof to provide a data processing device, or the second aspect of the disclosure and any implementation thereof A data processing system is provided.

In a fourth aspect, the embodiments of the present disclosure further provide a data processing method applied to a data processing device; the data processing method includes:

In response to receiving the port gating signal, the multiplexer gating the first transmission path or the second transmission path used by the data processing chip to obtain the configuration information;

The data processing chip acquires first configuration information in response to the first transmission path being selected, and determines its own mode as the master mode based on the first configuration information; in response to the selection of the second transmission path In general, the second configuration information is acquired, and based on the second configuration information, the self mode is determined as the controlled mode.

In the fifth aspect, the embodiments of the present disclosure also provide another data processing method, which is applied to a data processing system; the data processing method includes:

The controller monitors the status of the first data processing device; in response to the status indication, switches the first data processing device to a controlled mode, sends a first control command to the first data processing device, and sends a target the second data processing device sends a second control instruction;

The first data processing device switches its own mode to the controlled mode in response to receiving the first control instruction;

The target second data processing device switches its own mode to the master mode in response to receiving the second control instruction.

For the effect description of the above-mentioned board and data processing method, refer to the description of the above-mentioned data processing device and data processing system, which will not be repeated here.

In order to make the above-mentioned objects, features and advantages of the present disclosure more comprehensible, preferred embodiments will be described in detail below together with the accompanying drawings.

Description of drawings

In order to illustrate the technical solutions of the embodiments of the present disclosure more clearly, the following will briefly introduce the accompanying drawings used in the embodiments. The accompanying drawings here are incorporated into the specification and constitute a part of the specification. The drawings show the embodiments consistent with the present disclosure, and are used together with the description to explain the technical solutions of the present disclosure. It should be understood that the following drawings only show some embodiments of the present disclosure, and therefore should not be regarded as limiting the scope. For those skilled in the art, they can also make From these figures are obtained other related figures.

FIG. 1 shows a schematic diagram of a data processing device provided by an embodiment of the present disclosure;

FIG. 2 shows a schematic structural diagram of a data processing device provided by an embodiment of the present disclosure;

Fig. 3 shows a schematic diagram of a data processing system provided by an embodiment of the present disclosure;

FIG. 4 shows a schematic structural diagram of a data processing system provided by an embodiment of the present disclosure;

Fig. 5 shows a schematic diagram of a second data processing device for determining a target provided by an embodiment of the present disclosure;

Fig. 6 shows a schematic diagram when a controller according to an embodiment of the present disclosure sends a data reset signal to a data processing device;

FIG. 7A and FIG. 7B show a flow chart of a data processing system provided by an embodiment of the present disclosure when performing a data processing task;

FIG. 8 shows a schematic diagram of a board provided by an embodiment of the present disclosure;

FIG. 9 shows a flow chart of a data processing method provided by an embodiment of the present disclosure;

FIG. 10 shows a flowchart of another data processing method provided by an embodiment of the present disclosure.

detailed description

In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only It is a part of the embodiments of the present disclosure, but not all of them. The components of the disclosed embodiments generally described and illustrated herein may be arranged and designed in a variety of different configurations. Accordingly, the following detailed description of the embodiments of the present disclosure is not intended to limit the scope of the claimed disclosure, but merely represents selected embodiments of the present disclosure. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative effort shall fall within the protection scope of the present disclosure.

After research, it is found that when using CPU to process data such as images, in order to speed up data processing and improve efficiency, it is usually supplemented by multiple AI accelerator cards to process data in parallel. For example, when performing data processing on multiple images, the CPU can be used as the main control chip to receive data processing tasks sent by the outside world, decompose the data processing tasks into multiple sub-tasks, and assign different sub-tasks to multiple AI accelerator cards. Tasks, sub-tasks are processed in parallel by multiple AI accelerator cards to improve the efficiency of data processing. However, under this "CPU+AI accelerator card" hardware architecture, once the CPU as the main control chip fails, the entire data processing process will be affected, resulting in poor stability of the hardware architecture.

Based on the above research, the present disclosure provides a data processing device, by switching the data processing chip in the data processing device to the master mode or the controlled mode under different circumstances, so as to get rid of the data processing in the traditional data processing device. Functional limitations of the chip. The data processing chip can switch its own mode according to actual needs, improving the stability of the data processing device.

The defects in the above solutions are all the results obtained by the inventor after practice and careful research. Therefore, the discovery process of the above problems and the solutions proposed by the present disclosure below for the above problems should be the result of the inventor Contributions made to this disclosure during the course of this disclosure.

It should be noted that like numerals and letters denote similar items in the following figures, therefore, once an item is defined in one figure, it does not require further definition and explanation in subsequent figures.

To facilitate understanding of this embodiment, a data processing device disclosed in this embodiment of the disclosure is first introduced in detail.

Referring to FIG. 1 , it is a schematic diagram of a data processing device provided by an embodiment of the present disclosure; the data processing device 100 includes: a data processing chip 10 and a multiplexer 20; wherein,

The multiplexer 20 is configured to, in response to receiving a port gating signal, gating the first transmission path or the second transmission path used by the data processing chip 10 for obtaining configuration information;

The data processing chip 10 is configured to obtain first configuration information in response to the first transmission path being gated, and determine its own mode as the master mode based on the first configuration information; in response to the second The transmission channel is selected, the second configuration information is obtained, and the own mode is determined as the controlled mode based on the second configuration information.

In the data processing device provided by the embodiments of the present disclosure, the multiplexer may gate the first transmission path between the data processing chip and the first memory in response to receiving the port gating signal, so that the data processing chip The mode is switched to the master mode; or, the second transmission path between the data processing chip and the second memory is selected, so that the data processing chip switches its own mode to the controlled mode. In this way, by switching the data processing chip in the data processing device to the master mode or the controlled mode under different circumstances, it can get rid of the functional limitation of the data processing chip in the traditional data processing device. The data processing chip can switch its own mode according to actual needs, improving the stability of the data processing device.

In a specific implementation, the data processing chip 10 in the data processing device 100 may include but not limited to at least one of the following: AI chip, graphics processing unit (graphics processing unit, GPU), field programmable logic gate array (Field Programmable Gate Array, FPGA), and Application Specific Integrated Circuit (ASIC). Specifically, in the case that the data processing chip 10 includes an AI chip, the data processing apparatus 100 correspondingly including the data processing chip 10 may include hardware devices for accelerating data processing, for example. Here, in the data processing chip 10, for example, a network adapter (network adapter) for interfacing with an external network may also be included, for example, the network adapter may receive data sent by an external network, such as a related data.

In the embodiments of the present disclosure, the data processing chip 10 has different functions in different modes. Among them, in the master control mode, the data processing chip 10 can receive the data processing tasks sent by the outside world, decompose the data processing tasks into multiple subtasks, and send subtasks to other data processing chips 10 in the controlled mode, so as to play the role of The control function of other data processing devices 100; in the controlled mode, the data processing chip 10 can receive the subtasks sent by other data processing chips 10 in the master control mode, and process the subtasks to actually execute the data processing tasks role.

Exemplarily, the data processing task may include classifying and recognizing multiple images, where after decomposing the data processing task into multiple subtasks, each subtask includes: classifying and recognizing one of the multiple images. Alternatively, the data processing task may also include performing multiple data enhancement processing on an image, wherein after decomposing the data processing task into multiple subtasks, each subtask includes: using one of the multiple data enhancement processing methods The data enhancement processing method is to perform data enhancement processing on the image; various data enhancement processing includes, for example, smoothing the image, Gaussian blur processing, random erasing processing, and boundary detection processing. In addition, the above data processing tasks only show two examples, and the data processing apparatus 100 provided in the embodiments of the present disclosure may also be used to perform other data processing tasks, which are not limited in the embodiments of the present disclosure.

In a specific implementation, the data processing chip 10 has different functions when its own mode is in the master mode and its own mode is in the controlled mode.

Specifically, for the data processing chip 10 in the master control mode in its own mode, the data processing chip 10 may decompose the data processing task into multiple subtasks in response to receiving the data processing task, Other data processing apparatuses 100 in the control mode deliver the subtasks.

For the data processing chip 10 whose own mode is in the controlled mode, the data processing chip 10 may execute the subtasks issued by other data processing devices 100 in the master mode in response to receiving the subtasks issued by the other data processing devices 100. sent subtasks.

Exemplarily, the data processing chip 10 in the data processing device 100 may be represented by an IC (integrated circuit), for example. Wherein, corresponding to a plurality of data processing devices 100 (for example, including three data processing devices), the corresponding data processing chips 10 may be denoted as IC_1, IC_2, and IC_3 respectively. Currently, the self-mode of IC_1 is in the master mode, and the self-modes of IC_2 and IC_3 are in the controlled mode. After IC_1 receives the data processing task sent by the host (host) side or other upper computer devices, it decomposes the received data processing task into multiple subtasks. Wherein, the plurality of subtasks may include, for example, a subtask M_1 for classifying and identifying the first image, and a subtask M_2 for classifying and identifying the second image. After determining the subtasks M_1 and M_2, IC_1 may, for example, send subtask M_1 to IC_2 in the controlled mode, and send subtask M_2 to IC_3 also in the controlled mode.

After receiving the subtask M_1, IC_2 executes the subtask M_1 to classify and recognize the first image; similarly, after receiving the subtask M_2, IC_3 executes the subtask M_2 to classify and recognize the second image . In a possible implementation manner, the data processing chip 10 in the controlled mode may also send the processing result to the data processing chip 10 in the master mode after executing the subtask. For example, when IC_2 determines that the classification recognition result is C1, and IC_3 determines that the classification recognition result is C2, the recognition result C1 and the recognition result C2 may also be sent to IC_1 respectively.

In the data processing device 100, if the data processing chip 10 is in the master control mode; when the data processing chip 10 fails, the current mode of the data processing chip 10 can be switched from the master control mode to the controlled mode; meanwhile, another The data processing chip 10 in the controlled mode in a data processing device 100 is switched from the controlled mode to the master mode. In this way, the simultaneous occurrence of multiple data processing chips 10 in the master mode can be avoided. At the same time, due to the mode switching of the data processing chip 10, it is guaranteed that once the data processing chip 10 in the main control mode breaks down, the data processing chip 10 in other data processing devices will replace its main control function, ensuring the stability of the system .

In another possible implementation, in order to prevent the data processing chip 10 in the fault state from affecting the normal execution of the data processing task, the data processing chip 10 in the fault state may not be switched from the master control mode to the controlled mode, but In response to a failure of the data processing chip 10 in the current master control mode, the data transmission path between the data processing chip 10 and other data processing chips 10 is disconnected. In this case, it is necessary to switch the data processing chip 10 in another data processing device 100 from the controlled mode to the master mode.

In addition, since the data processing device 100 including the data processing chip 10 can be integrated into an integrated circuit, a circuit board or a chip, that is, the data processing device 100 is hot-swappable, so when the data processing chip 10 fails, it can be The data processing device 100 including the data processing chip 10 is removed, and a new data processing device 100 is replaced. And in this process, there is no need to suspend the normal use of other data processing devices 100, which can reduce the impact of the fault repair process on other data processing devices 100, and maintain the stability of the hardware architecture.

In another embodiment of the present disclosure, the switching of the data processing chip 10 may be implemented by utilizing the first memory and the second memory further included in the data processing device 100 , for example. Referring to FIG. 2 , it shows a specific structural diagram of a data processing device, which includes a first memory 30 and a second memory 40; the first memory 30 and the second memory 40 are respectively connected to the multiple Port A and port B in the multiplexer 20 are connected.

Specifically, the first memory 30 and the second memory 40, for example, may be flash memory (flash). The multiplexer 20 may gate the first transmission path between the data processing chip 10 and the first memory 30, or gate the data processing chip 10 and the first memory 30 in response to receiving the port gate signal. The second transmission path between the second memory 40 is selected, so that the data processing chip 10 determines its own mode as the master mode in response to the first transmission path being selected; or the data processing chip 10 responds to the second transmission path is strobed to determine its own mode as the controlled mode.

Wherein, the first configuration information is stored in the first memory 30 . After the data processing chip 10 obtains the first configuration information, for example, it can receive a data processing task sent by a host computer or other upper computer equipment, or it can also perform other data configurations on the data processing chip 10 in other data processing devices 100 . Correspondingly, the data processing chip 10 receiving the first configuration information can determine its own mode as the master mode.

Exemplarily, a first transmission path is included between the data processing chip 10 and the first memory 30, and the first transmission path may include, for example, a serial peripheral interface (Serial Peripheral Interface, SPI) bus. Since the multiplexer 20 is connected to the first memory 30, when the self mode of the data processing chip 10 is determined to be the master mode, the first memory between the multiplexer 20 and the first memory 30 can be selected. Data path implementation. Wherein, the communication protocol between the multiplexer 20 and the first memory 30 may also include an SPI bus, or a different protocol may be selected according to actual conditions, and details will not be repeated here.

In the second memory 40, second configuration information is stored. After acquiring the second configuration information, the data processing chip 10 may, for example, receive subtasks sent by the data processing chips 10 in other data processing devices 100 , such as the aforementioned subtask M_1 and subtask M_2 . Specifically, in the embodiment of the present disclosure, the data processing chip 10 that receives the second configuration information is unaware of the data processing chip 10 that sends the subtask to it, and executes the corresponding data processing task after receiving the subtask, namely Can. That is to say, the data processing chip 10 corresponding to receiving the second configuration information can switch its own mode to the controlled mode, and continue to execute the subtasks sent by the data processing chip 10 whose own mode is currently in the master control mode, which can reduce the execution data. Interruption while processing tasks, with better processing coherence.

Exemplarily, a second transmission path may be included between the data processing chip 10 and the second memory 40 , for example. Wherein, the second transmission path, for example, can also be set as the same as the first transmission path as the SPI bus, so that the data processing chip 10 does not need to switch the communication protocol when switching its own mode, and the switching is relatively simple, and the efficiency can also be improved to a certain extent . When the data processing chip 10 whose current own mode is in the master control mode breaks down, for other data processing chips 10 that can be switched to the master control mode at this time, the multiple channels in the data processing chip 10 whose current self mode is in the master control mode The multiplexer 20 is connected with the second memory 40, so when the data processing chip 10 whose current self mode is in the master control mode determines to switch its own mode to the controlled mode, the multiplexer 20 can be connected to the second memory 40 through the gate. A data path between memories 40 is implemented.

In another embodiment, since the multiplexer 20 mainly acts as a switch, it cannot undertake the task of judging whether the data processing chip 10 in the data processing device 100 needs to switch its own mode, so in the data processing device 100 also includes a signal converter and a monitoring chip. Referring to FIG. 2 , it shows the circuit connection relationship of the signal converter 50 and the monitoring chip 60 in the data processing device 100 . Please refer to the description of the signal converter 50 and the monitoring chip 60 below for details.

Wherein, the monitoring chip 60 can be used to monitor the state of the data processing chip 10 to determine whether the data processing chip 10 can work normally, so as to determine whether the current mode of the data processing chip 10 needs to be switched. In addition, the signal converter 50 is also connected to the controller outside the data processing device, because the controller cannot directly use the bus (here, the bus includes a System Management Bus (SMBUS)) to directly read the information determined by the monitoring chip 60. Monitoring results, so the controller can read the monitoring results sent by the monitoring chip 60 from the signal converter 50 and stored in the signal converter 50, and further send control instructions to the signal converter 50 to control multiplexing The device 20 gates the first transmission path or gates the second transmission path, so as to realize the mode switching of the data processing chip 10 itself.

Specifically, for the monitoring chip 60 , the monitoring chip 60 is respectively connected to the data processing chip 10 and the signal converter 50 , and for the specific connection relationship, please refer to the following description of the signal converter 50 . The monitoring chip 60 is configured to monitor the working state of the data processing chip 10 and send a monitoring signal corresponding to the working state to the signal converter 50 .

Exemplarily, the monitoring chip 60 can be, for example, an SP706 chip, or a MAX706 chip. The monitoring chip 60 includes multiple pins, which can receive or send different signals. Specifically, the monitoring chip 60 may include, for example, a watchdog signal input (Watch Dog Input, WDI) pin, and the WDI pin is connected to the data processing chip 10 for monitoring the working state of the data processing chip 10.

Exemplary, if the input/output (Input/Output, I/O) port of the WDI pin of the monitoring chip 60 has a level change within 1.6 seconds, the watchdog signal output (Watch Dog) included in the monitoring chip 60 The output signal of the Output (WDO) pin is high level, indicating that the working state of the data processing chip 10 is normal. If the I/O port of the WDI pin of the monitoring chip 60 has no level change within 1.6 seconds, the output signal of the WDO pin included in the monitoring chip 60 is low level, indicating that the working state of the data processing chip 10 is abnormal.

After the monitoring chip 60 monitors the working state of the data processing chip 10, a monitoring signal corresponding to the working state can be determined. Exemplarily, the output signal of the WDO pin represented by high and low levels can be directly used as the monitoring signal; or, the level logic can also be set to determine the monitoring signal, for example, when the working state of the data processing chip 10 is determined to be normal , determining that the corresponding monitoring signal is at a low level, and determining that the corresponding monitoring signal is at a high level when it is determined that the working state of the data processing chip 10 is abnormal. Specifically, it may be determined according to actual conditions, and no limitation is made here.

After the monitoring chip 60 determines the monitoring signal, it can send the monitoring signal to the signal converter 50 . Here, in order to reduce the weight of the data processing device 100 and manage a plurality of data processing devices 100 with one controller, a controller can be provided outside the data processing device 100 to judge whether data processing is required according to the monitoring signal. The own mode of the chip 10 is switched. That is, the controller may include, for example, an electronic device that plays a decision-making role outside the data processing device.

Here, when the controller reads the monitoring signal determined by the monitoring chip 60 , it can use SMBUS to read the monitoring signal. But when selecting the SP706 chip as the monitoring chip 60, because the controller cannot directly read the monitoring signal determined by the SP706 chip through the SMBUS, it can effectively control the output of any input pin of the signal converter 50 through the SMBUS to correspond to the monitoring signal. , and can be read by the controller, so the monitoring chip 60 can send the monitoring signal to the signal converter 50, and then the controller reads the monitoring signal stored in the signal converter 50 through SMBUS.

Wherein, when the number of data processing devices 100 is large, the controller can only read monitoring signals corresponding to a limited number of data processing devices 100 through SMBUS because the number of SMBUS that the controller can support to read is limited. In this case, an expansion chip, such as PCA9548, can also be provided for the controller, so that the controller can read the monitoring signal of the data processing device 100 currently to be monitored. Similarly, for the situation that the controller sends other signals to the data processing device 100 , it is also possible to implement sending signals to a larger number of data processing devices 100 by expanding the chip for it. For example, in the following embodiments, when the controller sends the reset signal to the data processing device 100 and releases the reset signal, the controller can also be provided with an expansion chip to realize the failure to receive the signal when a single controller is set. Other data processing devices 100 transmit signals. It will not be repeated in the following.

In another embodiment of the present disclosure, the signal converter 50 is further configured to receive the monitoring signal sent by the monitoring chip 60, and send the monitoring signal to the controller based on a preset second communication protocol .

Wherein, the signal converter 50 can be, for example, a PCA9555 chip.

Exemplarily, as shown in FIG. 2, the signal converter 50 may include, for example, two input/output pins, respectively denoted as I/O_1 and I/O_2; and include a synchronous serial bus (Inter-Integrated Circuit, I2C )interface. Wherein, the I/O_1 in the signal converter 50 is connected to the WDO in the monitoring chip. The monitoring chip 60 can, for example, utilize the WDO to transmit the monitoring signal to the signal converter 50; wherein, I/O_1 is used to receive the monitoring signal sent by the WDO in the monitoring chip 60, and then the register in the signal converter 50 rewrites the monitoring signal, and the controller The rewritten monitoring signal can be read from the I2C, so as to determine whether the data processing chip 10 can work normally. In this case, the data path between the I2C and the controller in the signal converter 50 indicated in FIG. 2 refers to the data path through which the controller reads signals from the I2C.

Wherein, the signal converter 50 may send a monitoring signal to the controller based on a preset second communication protocol. The second communication protocol may include, for example, a communication protocol used by SMBUS.

In another embodiment of the present disclosure, when the mode of the data processing chip 10 is switched, the data processing chip 10 needs to be able to adapt to the mode after switching. For example, the types of the data processing chip 10 include computing chips that can only provide computing power, and other chips that can provide computing power and also perform subtask distribution. Then for the computing chip, when switching its own mode from the controlled mode to the master mode, since the computing chip cannot undertake the function of distributing subtasks, the computing chip is switching its own mode to the master mode. After that, the data processing task cannot be executed normally, that is, the self-mode of the computing chip should not be switched to the main control mode.

Therefore, registers may also be included in the data processing device 100 . Refer to FIG. 2 , which shows a schematic circuit connection diagram of the register. Wherein, the register 90 can be, for example, an electrically erasable programmable read only memory (Electrically Erasable Programmable read only memory, E2PROM), specifically a field-replaceable unit (Field-Replaceable Unit E2PROM, FRU E2PROM). Since the tasks that the data processing chip 10 can undertake are fixed, that is, its type is fixed, so the type information of the data processing chip 10 can be predetermined. Specifically, the corresponding register 90 can be determined for the data processing chip 10, and the register 90 is used to store the type information of the data processing chip 10; and, since the type information corresponding to the data processing chip 10 is fixed, the When using the data processing device 100, the type information can be directly programmed into the register 90, and the type information stored in the register 90 remains unchanged. Here, the register 90, for example, can be connected to the corresponding data processing chip 10; or exist as a separate register in the data processing device 100, and has no connection relationship with other modules in the data processing chip 10, as shown in FIG. 2 The register 90 is not connected to other modules in the data processing chip 10 . In addition, a controller outside the data processing device 100 is connected to the register 90; specifically, the controller can also use SMBUS to read the type information stored in the register 90, and judge whether the data processing chip 10 can switch its own mode.

Exemplarily, the controller can determine the data processing chip 10 whose own mode is currently in the controlled mode, and then monitor the data processing chip 10, specifically after receiving the monitoring signal stored in the signal converter 50, through the monitoring The signal judges whether the corresponding data processing chip 10 can work normally. In a possible situation, if the monitoring signal indicates that the data processing chip 10 can work normally, keep the current mode of the data processing chip 10 unchanged and continue to execute the data processing task.

In another possible situation, if the monitoring signal indicates that the data processing chip 10 cannot work normally, the controller may, for example, control the signal gate in the data processing device 100 where the data processing chip 10 is located, so that the signal gate The port gate signal is sent to the port gate interface in the multiplexer 20 . Referring to FIG. 2 , it shows a circuit connection diagram of a multiplexer.

Specifically, the signal converter 50 is used to receive the control command sent by the controller based on the preset first communication protocol, convert the control command into a port gating signal, and send it to the multiplexer 20 The port strobe signal. Wherein, the first communication protocol can be, for example, the same communication protocol as the second communication protocol, such as SMBUS, or other communication protocols different from the first communication protocol can also be selected according to actual conditions.

Wherein, I/O_2 in the signal converter 50 can be used to send a port gating signal to the port gating port in the multiplexer 20 connected to it, and the port gating signal is used to indicate the multiplexer 20 gates the first transmission path or the second transmission path between the multiplexer 20 and the first memory 30 or the second memory 40 .

Corresponding to the data processing chip 10 that cannot work normally at present, the controller can, for example, send a control instruction to the synchronous serial bus (Inter-Integrated Circuit, I2C) interface in the signal converter 50 in the corresponding data processing device 100, to After receiving the control instruction, the signal converter 50 sends the port gate signal PO_1 to the port gate port of the multiplexer 20 to instruct the multiplexer 20 to select the second transmission path. In this case, the data path between the I2C and the controller in the signal converter 50 indicated in FIG. 2 refers to the data path through which the controller sends a control instruction to the I2C. At this time, for the data processing chip 10 , its own mode will be switched from the current master control mode to the controlled mode.

And corresponding to the data processing chip 10 that can work normally at present, if the controller reads the type information of the data processing chip 10 stored in the register 90 in the data processing device 100 where the data processing chip 10 is located, determine its type information When indicating that the data processing chip 10 can be used as the data processing chip 10 in the master control mode, a control instruction can be sent to the I2C interface in its corresponding signal converter 50, so that after receiving the control instruction, the multi-channel The port gate port of the multiplexer 20 sends a port gate signal PO_2 instructing the multiplexer 20 to gate the first transmission path. Then, for the data processing chip 10, its own mode will be switched from the current controlled mode to the master mode.

The embodiment of the present disclosure also provides a data processing system. Referring to FIG. 3 , it is a schematic diagram of a data processing system 200 provided by an embodiment of the present disclosure; the data processing system 200 includes a data processing device 100 provided by an embodiment of the present disclosure, and a controller 70; wherein, the data There are multiple processing devices 100; the multiple data processing devices 100 include: a first data processing device 101 in a master mode, and a second data processing device 102 in a controlled mode; wherein,

The controller 70 is configured to monitor the status of the first data processing device; switch the first data processing device to a controlled mode in response to the status indication, and send a message to the first data processing device a first control instruction, and sending a second control instruction to a target second data processing device;

The first data processing device 101 is configured to switch its own mode to a controlled mode in response to receiving a first control instruction;

The target second data processing device 103 is configured to switch its own mode to the master mode in response to receiving the second control instruction.

The data processing system 200 provided by the embodiment of the present disclosure may use the controller to determine the state of the first data processing device, and determine whether to switch its mode. When the controller determines to switch its own mode of the first data processing device, it can send a first control command to the first data processing device to switch its own mode to the controlled mode; The second data processing device sends a second control instruction, so that the target second data processing device switches its own mode to the master mode. In this way, when the data processing device in the master mode in the data processing system 200 fails, other data processing devices in the controlled mode can switch to the master mode, and continue to assume the responsibility of the data processing device in the master mode. function, so as to ensure the normal and stable operation of the data processing system 200.

In a specific implementation, the first data processing device 101 includes one, its own mode is the main control mode, and correspondingly the data processing chip in the first data processing device 101, its own mode is the main control mode. Corresponding to the second data processing device 102 , there may be one or more devices according to actual data processing task requirements or requirements on the working stability of the data processing system 200 . When the working state of the first data processing device 101 is abnormal, an appropriate target second data processing device 103 can be selected in the second data processing device 102 to switch to the master mode to replace the abnormal first data processing device 101, In this way, the normal and stable operation of the data processing system 200 is guaranteed.

Specifically, when the controller 70 monitors the state of the first data processing device 101, for example, it may receive a monitoring signal sent by the first data processing device 101; based on the monitoring signal, determine the first data The working status of the processing device 101: based on the working status of the first data processing device 101, determine whether to switch the first data processing device 101 to a controlled mode.

Wherein, the specific process of the first data processing device 101 sending the monitoring signal to the controller 70 may refer to the above-mentioned description of the data processing device 100 , which will not be repeated here.

In a specific implementation, when the controller 70 determines the state of the first data processing device 101 based on the monitoring signal, for example, it may determine that the state of the first data processing device 101 is the working state and/or the data path state according to the monitoring signal .

Wherein, when the first data processing device 101 works normally in the master control mode, for example, the first data processing device 101 processes the data processing task into multiple subtasks after receiving it, and distributes the subtasks to the second data processing device 102. When performing a task, the state of the first data processing device 101 can be considered as a working state, that is, the first data processing device 101 is correspondingly executing a data processing task.

Alternatively, the state of the first data processing device 101 may also include a data path state. For example, for the first data processing device 101 that cannot work normally at present, it cannot normally distribute subtasks to the second data processing device 102, so there is only a connection relationship on the data path. In this case, the state of the first data processing means is determined as the data path state.

In this way, the status of the first data processing device 101 can be intuitively used to determine whether it needs to be switched to the controlled mode. The following takes the first data processing device 101 including the working status as an example for illustration.

The controller 70 can simply determine the state of the first data processing device 101 according to the correspondence between preset monitoring signals and optional state judgment results. For example, when the working state of the data processing chip in the first data processing device 101 is abnormal, a high-level monitoring signal can be sent to the controller 70, and after the controller 70 receives the high-level monitoring signal, It may be determined that the state of the first data processing device 101 is an abnormal working state. Or, when the working state of the data processing chip in the first data processing device 101 is normal, a low-level monitoring signal can be sent to the controller 70, and after the controller 70 receives the low-level monitoring signal, It may be determined that the state of the first data processing device 101 is a normal working state.

After determining the working state of the first data processing device 101, the controller 70 may also determine whether to switch the first data processing device 101 to the controlled mode based on the determined working state of the first data processing device 101. Specifically, when the controller 70 determines that the working state of the first data processing device 101 is abnormal, it determines that the state of the first data processing device 101 is an abnormal state, and determines to switch the first data processing device 101 to the controlled mode; Alternatively, when the controller 70 determines that the working state of the first data processing device 101 is normal, it keeps the self-mode of the first data processing device 101 as the master mode.

The following takes the first data processing device 101 including the data path state as an example to illustrate whether it is necessary to switch the mode of the first data processing device 101 to the controlled mode.

Specifically, the controller 70 may monitor the state of the data path between the first data processing device 101 and the communication switch; based on the state of the data path between the first data processing device 101 and the communication switch, determine whether to Switch the first data processing device 101 to a controlled mode.

Wherein, the communication switch may include, for example, a high-speed serial computer expansion bus standard switch (Peripheral Component Interconnect Express Switch, PCIE Switch). Referring to FIG. 4 , it is a schematic structural diagram of a data processing system provided by an embodiment of the present disclosure; wherein, multiple data processing devices are respectively connected to the controller 70 through the communication switch 80 . In addition, when multiple data processing devices are connected with communication switch 80 respectively, can utilize high-speed serial computer expansion bus standard exchange card slot (PCIE Slot) to connect; Shown in Fig. 4 a plurality of data processing devices (data processing The device is represented by "DP". The multiple data processing devices shown in the figure include PCIE Slots corresponding to DP_1, DP_2, ..., DP_n), including PCIE Slot#1, PCIE Slot#2, PCIE Slot#3,... ..., PCIE Slot#n. In this way, when the data processing device communicates with the communication switch 80, it can select the PCIE protocol for communication.

Specifically, the controller 70 may determine that the current data transmission path of the first data processing device 101 is in a normal state through a data path normal signal actively sent by the communication switch 80, such as a PORT_GOOD# signal.

Exemplarily, as shown in FIG. 4 , the communication switch 80 may, for example, send PORT_GOOD# signals respectively corresponding to a plurality of data processing devices DP_1 to DP_n to the controller, for example, may include PORT_GOOD#1 to PORT_GOOD# shown in FIG. 4 n.

Here, if the controller 70 fails to receive the data path normal signal corresponding to any data processing device from the communication switch 80 , it can determine that the state of the data path between the data processing device and the communication switch 80 is abnormal. For example, if the controller 70 fails to receive PORT_GOOD#1, it can determine that the state of the data transmission path between the data processing device DP_1 and the communication switch 80 is abnormal, that is, the state of the data path corresponding to PCIE Slot#1 is abnormal.

In addition, when the controller 70 determines the state of the data path between the corresponding data processing device and the communication switch 80 based on the PORT_GOOD# signal sent by the communication switch 80, the direction of data transmission is the direction in which the data processing device transmits data to the controller. . However, in a possible situation, if the first data processing device 101 in the master mode is determined among multiple data processing devices, the first data processing device 101 may also send data to other first data processing devices 101 in the controlled mode. Two data processing devices 102 send subtasks (for example, when DP_1 serves as the first data processing device 101 , the remaining DP_2 to DP_n can all serve as the second data processing device 102 ). Therefore, there may also be data sent to the second data processing device 102 (ie, DP_2 to DP_n) in the data transmission path shown in FIG. 4 , which is opposite to the above data transmission direction when determining the state of the data path. Therefore, the specific direction during data transmission is not shown in FIG. 4 , but in a specific data processing situation, it can represent the data transmission direction corresponding to the data processing task.

Here, the data transmission path of the first data processing device 101 can include, for example, a data transmission path corresponding to the PCIE communication protocol, or other data transmission paths that can be used for subtask transmission can also be selected, and the used one can be replaced accordingly. communication switch 80 .

After determining the state of the data path between the first data processing device 101 and the communication switch 80, the controller 70 may also determine whether to switch the first data processing device 101 to the controlled mode based on the state of the data path. Specifically, when the controller 70 determines that the state of the data path between the first data processing device 101 and the communication switch 80 is abnormal, it determines that the state of the first data processing device 101 is an abnormal state, and determines that the first data processing device 101 switch to the controlled mode; or, when the controller 70 determines that the state of the data path between the first data processing device 101 and the communication switch 80 is normal, keep the first data processing device 101 in its own mode as the master mode.

The following takes the first data processing device 101 including the working state and the data path state as an example to explain whether it is necessary to switch the mode of the first data processing device 101 to the controlled mode.

Specifically, after the controller 70 determines the state of the data path between the first data processing device 101 and the communication switch 80, based on the state of the data path and the working state of the first data processing device 101, determine whether to The data processing device 101 switches to the controlled mode. Specifically, when the controller 70 determines that the working state of the first data processing device 101 is normal but the state of the data path is abnormal, the controller 70 determines that the state of the first data processing device 101 is an abnormal state, and determines to switch the first data processing device 101 to is the controlled mode; or, when the controller 70 determines that the working state of the first data processing device 101 is abnormal and the state of the data path is abnormal, it determines that the state of the first data processing device 101 is an abnormal state, and determines that the first data processing device 101 is abnormal. The processing device 101 switches to the controlled mode; or, when the controller 70 determines that the working state of the first data processing device 101 is abnormal but the data path state is normal, determine that the state of the first data processing device 101 is an abnormal state, and determine Switch the first data processing device 101 to the controlled mode; or, when the controller 70 determines that the working state of the first data processing device 101 is normal but the data path state is abnormal, determine that the state of the first data processing device 101 is abnormal state, and determine to switch the first data processing device 101 to the controlled mode; or, the controller 70 keeps the first data processing device 101 in Its own mode is master mode.

Specifically, the controller 70 may also monitor the state of the data path between the first data processing device 101 and the communication switch 80 after determining the working state of the first data processing device 101; The state and the state of the data path between the first data processing device 101 and the communication switch 80 determine whether to switch the first data processing device 101 to the controlled mode. The specific switching method is similar to the previous description, and will not be repeated here.

It should be noted that the present disclosure does not limit the order in which the controller 70 determines the working status of the first data processing device 101 and determines the data path status of the first data processing device 101 . That is, the controller 70 may first determine the data path status of the first data processing device 101, and then determine the working status of the first data processing device 101; it may also perform in reverse order; or both may be performed at the same time.

For the situation where the controller 70 determines to switch the first data processing device 101 to the controlled mode, because the working state of the first data processing device 101 currently in use is abnormal and cannot work normally, in order to ensure that the data processing system 200 can continue to complete the In the work of decomposing the data processing task and delivering the subtasks obtained after decomposing, the target second data processing device 103 can also be determined in the second data processing device 102, so that the target second data processing device 103 can be used as The new first data processing device 101 completes corresponding data processing tasks. Therefore, the controller 70 may also determine, from among the second data processing devices 102 , the target second data processing device 103 to switch to the master mode based on the state of the second data processing device 102 .

In a specific implementation, the controller 70 may determine an alternative data processing apparatus from the second data processing apparatus 102 in response to the state of the first data processing apparatus 101 being an abnormal state, and detect the alternative data processing apparatus Device status: determining the candidate data processing device as the target second data processing device 103 in response to the candidate data processing device being in a normal state. The normal status of the candidate data processing device includes that the working status and the data path status of the candidate data processing device are both normal.

Specifically, refer to FIG. 5 , which is a schematic diagram of a second data processing device for determining a target provided by an embodiment of the present disclosure. In FIG. 5 , data processing devices DP_1 , DP_2 , . . . , DP_n usable in the data processing system 200 are included. Wherein, DP_1 is the current first data processing device 101 . After determining that the state of DP_1 is an abnormal state, when determining a candidate data processing device from the second data processing device 102, for example, the second data processing device 102 sequentially adjacent to DP_1 may be determined as a candidate data processing device.

Wherein, when determining the second data processing device 102 sequentially adjacent to the first data processing device 101, for example, it may be determined according to the sequence numbers of multiple data processing devices. Exemplarily, when determining a plurality of data processing devices in the data processing system 200, if n data processing devices are sequentially determined, including DP_1, DP_2, ..., DP_n, it is considered that they are in the same order as the first data processing device DP_1. The adjacent second data processing device, that is, DP_2, serves as an alternative data processing device.

Alternatively, for example, the second data processing device 102 sequentially adjacent to the first data processing device 101 may also be determined according to the current states of multiple data processing devices other than the first data processing device 101 . For example, when determining a candidate data processing device, the operating temperature of multiple data processing devices can be monitored first, and the operating temperature can be changed from a lower operating temperature to a higher operating temperature according to the respective operating temperatures of the multiple data processing devices. The direction of temperature determines the ordering of the multiple data processing means. Exemplarily, in the case where the multiple data processing apparatuses include DP_2, DP_3, and DP_4, the corresponding ordering is, for example, DP_3, DP_4, and DP_2. Then, when determining the second data processing device 102 sequentially adjacent to the first data processing device 101, determine the second data processing device 102 with the lowest operating temperature, that is, DP_3, as a candidate data processing device.

Here, different methods are selected when determining the sequence of multiple data processing devices, and the determined candidate data processing devices may also be different. Specifically, the corresponding candidate data processing device may be determined according to actual conditions, which is not limited here.

After the candidate data processing device is determined, in order to avoid the problem that the data processing system 200 still cannot work normally after switching its own mode to the master control mode due to the failure of the candidate data processing device, it is also guaranteed that the first data processing device For the efficiency when the processing device 101 and the second data processing device 102 switch, the controller 70 can also monitor the status of the alternative data processing device.

In a possible implementation manner, the controller 70 may also determine a new candidate data processing device from the second data processing device 102 in response to the state of the candidate data processing device being an abnormal state, and return Go to the step of detecting whether the state of the alternative data processing device is normal.

Wherein, the manner of determining a new candidate data processing device is similar to the above-mentioned manner of determining a candidate data processing device from the second data processing device 102 , and will not be repeated here.

In addition, when the controller 70 determines from the second data processing device 102 the target second data processing device 103 to switch to the master mode, it is also used to read the type information from the candidate data processing device ; Determining the candidate data processing device as the target second data processing device 103 in response to the read type information being preset type information.

Here, similar to the description in the data processing device corresponding to FIG. 2 above, if the type information of the candidate data processing device indicates that the data processing device cannot be used as the data processing device in the master mode, The status of the data processing device is normal, and the self-mode of the candidate data processing device cannot be switched to the master mode, and it can be used as the target second data processing device 103 . Therefore, the controller 70 can also read the type information of the candidate data processing device to determine whether it can be selected as the target second data processing device 103 and work as the data processing device in the master mode. For a specific manner in which the controller 70 reads the type information of the candidate data processing device, reference may be made to relevant descriptions in the above-mentioned embodiment corresponding to FIG. 2 , which will not be repeated here.

In this way, it is possible to determine the candidate data processing device when the data processing system 200 can be used normally after its own mode is switched to the master mode, and the efficiency is high. After it is determined that the state of the candidate data processing device is normal, the screening of the second data processing device 102 is stopped, and the determined candidate data processing device is used as the target second data processing device 103 .

After the controller 70 determines the target second data processing device 103, it can determine a new data processing system 200 by switching its own mode corresponding to the first data processing device 101 and the target second data processing device 103 respectively. The first data processing device 101.

In a specific implementation, the controller 70 may send a reset signal to the first data processing device 101 and the target second data processing device 103; after the reset signal is sent successfully, send a reset signal to the first data processing device 101 The first control instruction, and sending the second control instruction to the target second data processing device 103 .

Referring to FIG. 6 , it is a schematic diagram of a controller sending a data reset signal to a data processing device according to an embodiment of the present disclosure. Wherein, as the reset signal, for example, a device reset signal (PCIE Reset, PERST) can be used. In addition, the controller 70 may also send a device reset signal to the communication switch 80 . After the communication switch 80 receives the reset signal, it performs a reset operation.

In another embodiment, there is a situation where the controller 70 cannot send a reset signal to the communication switch 80, and then the communication switch 80 sends a reset signal to the data processing device. In this case, the communication is not shown in FIG. 6 The connection relationship between the switch 80 and the data processing device directly expresses the data transmission path through which the controller 70 sends a reset signal to the communication switch 80 and the data processing device.

In a specific implementation, the controller 70 is also connected to the data processing device through a bus; when the controller 70 sends a reset signal to the first data processing device 101 and the target second data processing device 103, It is configured to: send a reset signal to the first data processing device 101 and the target second data processing device 103 through the bus.

Exemplarily, the bus may include SMBUS, for example.

In a possible situation, corresponding to the circuit structure shown in FIG. 4 , if the communication switch 80 can use SMBUS to send reset signals to the data processing devices DP_1 to DP_n, then the controller 70 can send the reset signal to the communication switch 80, Then, the communication switch 80 sends reset signals to the data processing devices DP_1 to DP_n connected thereto. In another possible situation, if the communication switch cannot use SMBUS to send reset signals to the data processing devices DP_1 to DP_n, then the controller 70 can use the structure shown in FIG. The I2C in the converter sends a reset signal, thereby resetting the corresponding data processing device.

After the controller 70 sends a reset signal to the first data processing device 101 and the target second data processing device 103, the first data processing device 101 and the target second data processing device 103 can cancel the current self-mode, so that when the two are respectively When the corresponding self-mode is switched, it can be realized directly by gating the transmission paths between the corresponding data processing chips and the first memory or the second memory, so that the first data processing device 101 and the target The data processing device completes the switching of its own mode, and effectively reduces the occurrence of switching failures during switching.

Specifically, after the communication switch 80 receives the reset signal, it can also stop sending the PORT_GOOD# signal to the controller 70, that is, stop monitoring the data path corresponding to the data processing device, so as to reduce the communication switch 80 and the controller 70 during switching. power consumption. After the first data processing device 101 and the target second data processing device 103 receive the reset signal and complete the reset, the controller 70 can send the first control instruction to the first data processing device 101 and send the target second data processing device 103 Send the second control instruction. Wherein, the first control instruction is used to instruct the first data processing device 101 to switch its own mode to the controlled mode; the second control instruction is used to instruct the target data processing device to switch its own mode to the master mode.

Correspondingly, for the first data processing device 101, when switching its own mode to the controlled mode in response to receiving the first control instruction, it is used to perform a reset in response to receiving the reset signal; and after completing the reset , switching the own mode to the controlled mode in response to receiving the first control instruction. For the target data processing device, when switching its own mode to the master mode in response to receiving the second control instruction, it is used to perform a reset in response to receiving the reset signal; and after the reset is completed, in response to receiving the The second control instruction switches its own mode to the main control mode.

Taking the first data processing device 101 as an example, after the first data processing device 101 receives the first control instruction, referring to the description of the data processing device provided in the embodiment of the present disclosure, the first control instruction can be sent to the first data processing device The signal converter in 101, and the data processing chip in the first data processing device 101 can obtain the second configuration information in the second memory by sending a port gating signal from the signal converter to the multiplexer , so as to switch the first data processing device 101 from its own mode to the controlled mode. Similarly, the target second data processing device 103 may switch its own mode to the master mode in a similar manner, which will not be repeated here.

After the self-mode switching of the first data processing device 101 and the target second data processing device 103 is completed, for example, a successful switching signal may be sent to the controller 70 respectively. In a possible situation, if the controller 70 does not receive the successful switching signals sent by the two respectively, for example, it can directly report an error, wait for the staff to check, and keep the first data processing device 101 and the target second data processing device 103 reset status, or the solution can be determined according to the actual situation, which is not limited here.

In another possible situation, if the controller 70 receives the successful switching signal from the first data processing device 101 and the target second data processing device 103, it may send a message to the first data processing device 101 and the target second data processing device The device 103 sends a de-reset signal, and may also send a de-reset signal to the communication switch 80 . Correspondingly, the first data processing device 101 may release the reset in response to the received reset release signal; similarly, the target second data processing device 103 may also release the reset in response to receiving the reset release signal. Wherein, the manner in which the controller 70 sends the release reset signal to the first data processing device 101 and the target second data processing device 103 is similar to the manner in which the reset signal is sent to them, and will not be repeated here. After the communication switch 80 receives the release reset signal, it can re-monitor the corresponding data paths of the multiple data processing devices in the new data processing system 200 . In this way, the target second data processing device 103 can continue to receive data processing tasks and decompose them into subtasks based on its own mode as the master mode; similarly, the first data processing device 101 can be controlled based on its own mode, Task processing is performed on the received subtasks, so that the data processing system 200 can continue to complete corresponding data processing tasks.

In another embodiment of the present disclosure, a specific embodiment of data processing system 200 processing data processing tasks is also provided. Referring to FIG. 7A and FIG. 7B , it is a flowchart of a data processing system performing a data processing task provided by an embodiment of the present disclosure; wherein,

S701: The controller determines that the current own mode is the first data processing device in the main control mode;

S702: The data processing system executes a data processing task;

S703: The controller monitors whether the status of the first data processing device is normal; wherein, S703 includes the following S7031 to S7034;

S7031: The controller monitors the state of the data path between the first data processing device and the communication switch, and determines whether the state of the first data processing device is normal; if yes, execute S7032; if not, execute S7033;

S7032: The controller monitors whether the data processing chip in the first data processing device can work normally; wherein, S7032 includes the following S70321 and S70322;

S70321: The monitoring chip monitors the working state of the data processing chip in the first data processing device, and sends a monitoring signal corresponding to the working state to the signal converter;

S70322: The controller reads the monitoring signal stored in the signal converter, and determines whether the state of the first data processing device is normal; if yes, execute S7034; if not, execute S7033;

Here, S7031 and S7032 can be executed in reverse order, for example, S7032 is executed first, and then S7031 is executed; or, S7031 and S7032 can be executed synchronously.

S7033: Determine that the state of the first data processing device is an abnormal state;

S7034: Determine that the state of the first data processing device is normal; return to execute S702:

S704: The controller determines a candidate data processing device from the second data processing device;

S705: The controller monitors whether the state of the alternative data processing device is normal; if yes, execute S706; if not, execute S707;

S706: The controller determines that the candidate data processing device is the target second data processing device;

S707: The controller determines a new candidate data processing device from the second data processing device; return to execute S705;

S708: The controller sends a reset signal to the first data processing device and the target second data processing device to reset the first data processing device and the target second data processing device;

S709: The controller sends the first control instruction to the first data processing device, and sends the second control instruction to the target second data processing device;

S710: The first data processing device and the target second data processing device switch their own modes; wherein, S710 includes S7101 and S71012;

S7101: The first data processing device switches its own mode to a controlled mode in response to receiving a first control instruction;

S7102: The target second data processing device switches its own mode to the master mode in response to receiving the second control instruction;

S711: The controller sends a reset release signal to the first data processing device and the target second data processing device; the first data processing device and the target second data processing device release reset.

Based on the same inventive concept, an embodiment of the present disclosure also provides a board. The board provided by the embodiments of the present disclosure may include any data processing device or any data processing system disclosed in the embodiments of the present disclosure. Refer to FIG. 1 and FIG. 2 for the board including the data processing device, and refer to FIG. 8 for the board including the data processing system.

FIG. 8 is a schematic diagram of a board provided by an embodiment of the present disclosure; the board 300 includes a plurality of data processing devices 100 provided by an embodiment of the present disclosure (n data processing devices 100 are shown in FIG. 8, including DP_1 to DP_n), and a controller 70; wherein, a plurality of said data processing devices 100 are respectively connected to said controller 70 through a communication switch 80;

The controller 70 is configured to monitor the status of each of the data processing devices 100; switch one of the data processing devices 100 to the master mode according to the status of each of the data processing devices 100, and process other data The device 100 switches to the controlled mode.

Wherein, there is no separate CPU in this board. For the board shown in FIG. 8 , the data processing device 100 in the master control mode can undertake tasks such as receiving, splitting, and distributing data processing tasks. The master control mode is also called the root processing mode (Root Complex, RC). The data processing apparatus 100 in the controlled mode can undertake tasks such as processing subtasks, and the controlled mode is also called a node processing mode (End Point, EP).

In the related art, for using different CPUs, for example, CPU#1 and CPU#2 respectively connect the data processing device 100 in RC mode and the data processing device 100 in EP mode, such "CPU+data processing device" hardware architecture Among them, data processing devices in different modes correspond to different CPUs to complete related data processing tasks. However, when any one of the CPU or the data processing device is damaged, the whole cannot be used normally, and thus the data processing task cannot be performed normally. In addition, when replacing the hardware architecture in the new RC mode, it is also necessary to perform single-board verification on the CPU connected to the new data processing device and the new data processing device as a whole, for example, for "CPU#3+newly selected The function of "data processing device" is verified to determine whether it can be used as a hardware construction in the new RC mode, and this method is also relatively cumbersome.

For the board provided by the embodiment of the present disclosure, since the mode of the data processing device 100 can be switched in the board, that is, the mode of the data processing device 100 can be switched to the RC mode or the EP mode accordingly, so in the RC When the data processing device 100 in the EP mode fails, it can quickly switch to the RC mode from the data processing device 100 in other EP modes to continue to complete the data processing task. Therefore, when the board is performing the data processing task More flexible and more stable.

Based on the same inventive concept, the embodiment of the present disclosure also provides a data processing method corresponding to the data processing device. Since the problem-solving principle of the method in the embodiment of the present disclosure is similar to that of the above-mentioned data processing device in the embodiment of the present disclosure, the implementation of the method Reference can be made to the implementation of the device, and repeated descriptions will not be repeated.

Referring to FIG. 9 , it is a flowchart of a data processing method provided by an embodiment of the present disclosure, the data processing method is applied to the data processing device provided by the embodiment of the present disclosure; the data processing method includes:

S901: The multiplexer selects the first transmission path or the second transmission path used by the data processing chip to obtain the configuration information in response to receiving the port strobe signal;

S902: The data processing chip acquires first configuration information in response to the first transmission path being gated, and determines its own mode as the master mode based on the first configuration information; in response to the second transmission path is gated, acquires second configuration information, and determines its own mode as the controlled mode based on the second configuration information.

In an optional implementation manner, the data processing method further includes: when the data processing chip is in the master control mode in its own mode, in response to receiving a data processing task, decomposing the data processing task into multiple Subtasks, sending the subtasks to other data processing devices in the controlled mode; or the data processing chip is in the controlled mode in its own mode, in response to receiving other data processing devices in the master mode The delivered subtasks execute the subtasks delivered by the other data processing devices.

In an optional implementation manner, the data processing device further includes: a first memory and a second memory; wherein, the first memory and the second memory are respectively connected to the multiplexer; The data processing method further includes: the multiplexer gates the first transmission path between the data processing chip and the first memory in response to receiving the port gate signal, or gates the data A second transmission path between the processing chip and the second memory.

In an optional implementation manner, the data processing device further includes: a signal converter; the signal converter is connected to the multiplexer; and connected to a controller; the data processing method further includes: The signal converter receives the control instruction sent by the controller based on the preset first communication protocol, converts the control instruction into a port selection signal, and sends the port selection communication to the multiplexer No.

In an optional implementation manner, the data processing device further includes: a monitoring chip; the monitoring chip is respectively connected to the data processing chip and the signal converter; the data processing method further includes the monitoring chip monitoring the The working state of the data processing chip, and send a monitoring signal corresponding to the working state to the signal converter; the signal converter receives the monitoring signal sent by the monitoring chip, and based on the preset second A communication protocol sends the monitoring signal to the controller.

In addition, based on the same inventive concept, the embodiment of the present disclosure also provides a data processing method corresponding to the data processing system. Since the problem-solving principle of the method in the embodiment of the present disclosure is similar to that of the above-mentioned data processing system in the embodiment of the present disclosure, the method For the implementation of , please refer to the implementation of the system, and the repetition will not be repeated.

Referring to FIG. 10 , it is a flow chart of another data processing method provided by an embodiment of the present disclosure. The data processing method is applied to the data processing system provided by the embodiment of the present disclosure; the data processing method includes:

S1001: The controller monitors the status of the first data processing device; in response to the status indication, switches the first data processing device to a controlled mode, and sends a first control instruction to the first data processing device , and sending a second control instruction to the target second data processing device;

S1002: The first data processing device switches its own mode to a controlled mode in response to receiving the first control instruction;

S1003: The target second data processing device switches its own mode to the master mode in response to receiving the second control instruction.

In an optional implementation manner, the controller monitoring the state of the first data processing device includes: receiving a monitoring signal sent by the first data processing device; based on the monitoring signal, determining the The working status of the first data processing device: determining whether to switch the first data processing device to a controlled mode based on the working status of the first data processing device.

In an optional implementation manner, the data processing system further includes: a communication switch; multiple data processing devices are respectively connected to the controller through the communication switch; The state of the processing device is monitored, including: monitoring the state of the data path between the first data processing device and the communication switch; based on the state of the data path between the first data processing device and the communication switch, determining Whether to switch the first data processing device to a controlled mode.

In an optional implementation manner, the monitoring of the state of the first data processing device by the controller includes: in response to the state of the first data processing device being an abnormal state, determining that the first data processing device The processing device switches to controlled mode.

In an optional implementation manner, before the controller sends the second control instruction to the target second data processing device, the controller includes: based on the state of the second data processing device, from the second data processing device, A target second data processing device to be switched to the master mode is determined.

In an optional implementation manner, the controller determines, from among the second data processing devices, a target second data processing device to be switched to the master mode based on the state of the second data processing device, including : in response to the state of the first data processing device being an abnormal state, determine a candidate data processing device from the second data processing device, and detect the state of the candidate data processing device; in response to the candidate The state of the data processing device is a normal state, and the candidate data processing device is determined as the target second data processing device; the controller responds to the state of the candidate data processing device as an abnormal state, from the The second data processing device determines a new candidate data processing device, and returns to the step of detecting whether the state of the candidate data processing device is normal.

In an optional implementation manner, the controller determines from the second data processing device the target second data processing device to switch to the master mode, including: reading from the candidate data processing device Obtaining type information; in response to the read type information being preset type information, determining the candidate data processing device as the target second data processing device.

In an optional implementation manner, the controller sending the first control instruction to the first data processing device, and sending the second control instruction to the target second data processing device include: sending the first data processing device The device, and the target second data processing device send a reset signal; after the reset signal is sent successfully, send a first control instruction to the first data processing device, and send a second control instruction to the target second data processing device; The first data processing device switches its own mode to the controlled mode in response to receiving the first control instruction, including performing a reset in response to receiving the reset signal; and after completing the reset, in response to receiving the The first control instruction is to switch its own mode to the controlled mode; the target second data processing device switches its own mode to the master mode in response to receiving the second control instruction, including in response to receiving the reset signal, Executing reset; and after the reset is completed, in response to receiving the second control instruction, switch its own mode to the master mode.

In an optional implementation manner, the data processing method further includes: the controller responds to receiving a successful switching signal sent by the first data processing device and the target second data processing device, sending A data processing device and the target second data processing device send a reset release signal; the first data processing device releases reset in response to receiving the reset release signal; the target second data processing device responds Upon receiving the de-reset signal, de-reset.

In an optional implementation manner, the controller is further connected to the data processing device through a bus; the controller sends a reset signal to the first data processing device and the target second data processing device, including : sending a reset signal to the first data processing device and the target second data processing device through the bus.

Those skilled in the art can understand that in the above method of specific implementation, the writing order of each step does not mean a strict execution order and constitutes any limitation on the implementation process. The specific execution order of each step should be based on its function and possible The inner logic is OK.

The embodiment of the present disclosure also provides an electronic device, including: an instruction memory and the data processing device provided in the embodiment of the present disclosure, or including the data processing system provided in the embodiment of the present disclosure, or including the board provided in the embodiment of the present disclosure.

The data processing device, data processing system, or board provided by the embodiments of the present disclosure may include a chip, an AI chip, and the like. The electronic device provided by the embodiment of the present disclosure may include a smart terminal such as a mobile phone, or may also be another device capable of data processing, a server, etc., which is not limited here.

Boards include, for example, printed circuit boards.

The embodiment of the present disclosure also provides a computer-readable storage medium, on which a computer program is stored, and the program is used by a multiplexer or a data processing chip to execute the method provided in any data processing method embodiment of the present disclosure; or, The method provided by any data processing method embodiment of the present disclosure is executed by the controller, the first data processing device, and the target second data processing device.

The embodiment of the present disclosure also provides a computer program product, the computer program product carries a program code, and the instructions included in the program code can be used to execute the steps of the data processing method described in the above method embodiment, for details, please refer to the above method The embodiment will not be repeated here.

Wherein, the above-mentioned computer program product may be specifically implemented by means of hardware, software or a combination thereof. In an optional embodiment, the computer program product is embodied as a computer storage medium, and in another optional embodiment, the computer program product is embodied as a software product, such as a software development kit (Software Development Kit, SDK) etc. Wait.

Those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working process of the above-described system and device can refer to the corresponding process in the foregoing method embodiments, which will not be repeated here. In the several embodiments provided in the present disclosure, it should be understood that the disclosed systems, devices and methods may be implemented in other ways. The device embodiments described above are only illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or May be integrated into another system, or some features may be ignored, or not implemented. In another point, the mutual coupling or direct coupling or communication connection shown or discussed may be through some communication interfaces, and the indirect coupling or communication connection of devices or units may be in electrical, mechanical or other forms.

The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present disclosure may be integrated into one processing unit, each unit may exist separately physically, or two or more units may be integrated into one unit.

If the functions are realized in the form of software function units and sold or used as independent products, they can be stored in a non-volatile computer-readable storage medium executable by a processor. Based on this understanding, the technical solution of the present disclosure is essentially or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including Several instructions are used to make an electronic device (which may be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the methods described in various embodiments of the present disclosure. The aforementioned storage media include: U disk, mobile hard disk, read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), magnetic disk or optical disc and other media that can store program codes. .

Finally, it should be noted that: the above-mentioned embodiments are only specific implementations of the present disclosure, and are used to illustrate the technical solutions of the present disclosure, rather than limit them, and the protection scope of the present disclosure is not limited thereto, although referring to the aforementioned The embodiments have described the present disclosure in detail, and those skilled in the art should understand that any person familiar with the technical field can still modify the technical solutions described in the foregoing embodiments within the technical scope disclosed in the present disclosure Changes can be easily imagined, or equivalent replacements can be made to some of the technical features; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present disclosure, and should be included in this disclosure. within the scope of protection. Therefore, the protection scope of the present disclosure should be defined by the protection scope of the claims.

Claims

A data processing device, comprising: a data processing chip and a multiplexer; wherein,

The multiplexer is configured to select the first transmission path or the second transmission path used by the data processing chip for obtaining configuration information in response to receiving a port selection signal;

The data processing chip is configured to obtain first configuration information in response to the first transmission channel being gated, and determine its own mode as the master mode based on the first configuration information; in response to the second transmission The path is selected, the second configuration information is obtained, and the own mode is determined as the controlled mode based on the second configuration information.
The data processing device according to claim 1, wherein the data processing chip is further configured to decompose the data processing task in response to receiving a data processing task when its own mode is in the master control mode For multiple subtasks, sending the subtasks to other data processing devices in the controlled mode; or

The data processing chip is further configured to execute subtasks issued by other data processing devices in response to receiving subtasks issued by other data processing devices in master mode when its own mode is in the controlled mode. Task.
The data processing device according to claim 1 or 2, further comprising:

a first memory and a second memory;

Wherein, the first memory and the second memory are respectively connected to the multiplexer;

The multiplexer is configured to gate the first transmission path between the data processing chip and the first memory, or gate the data processing chip in response to receiving the port gate signal and the second transmission path between the second memory.
The data processing device according to any one of claims 1-3, further comprising: a signal converter;

the signal converter is connected to the multiplexer; and is connected to a controller;

The signal converter is used to receive the control command sent by the controller based on the preset first communication protocol, convert the control command into the port gating signal, and send the control command to the multiplexer. port strobe signal.
The data processing device according to any one of claims 1-4, further comprising: a monitoring chip;

The monitoring chip is respectively connected with the data processing chip and the signal converter;

The monitoring chip is used to monitor the working state of the data processing chip, and send a monitoring signal corresponding to the working state to the signal converter;

The signal converter is further configured to receive the monitoring signal sent by the monitoring chip, and send the monitoring signal to the controller based on a preset second communication protocol.
The data processing device according to any one of claims 1-5, further comprising: a register; the register is used to store type information of the data processing chip.
A data processing system, comprising: the data processing device according to any one of claims 1-6, and a controller;

Wherein, there are multiple data processing devices; the multiple data processing devices include: a first data processing device in a master mode, and a second data processing device in a controlled mode;

The controller is configured to monitor the status of the first data processing device; switch the first data processing device to a controlled mode in response to the status indication, and send the first data processing device to the first data processing device a control command, and sending the second control command to the target second data processing device;

The first data processing device is configured to switch its own mode to a controlled mode in response to receiving the first control instruction;

The target second data processing device is configured to switch its own mode to a master mode in response to receiving the second control instruction.
The data processing system according to claim 7, wherein the state of the data processing device includes at least one of the following:

Working status; data path status.
The data processing system according to claim 7 or 8, wherein the controller, when monitoring the state of the first data processing device, is configured to:

receiving a monitoring signal sent by the first data processing device;

determining the working state of the first data processing device based on the monitoring signal;

Based on the working state of the first data processing device, it is determined whether to switch the first data processing device to a controlled mode.
The data processing system according to any one of claims 7-9, further comprising: a communication switch;

A plurality of the data processing devices are respectively connected to the controller through the communication switch;

The controller, when monitoring the state of the first data processing device, is configured to: monitor the state of a data path between the first data processing device and the communication switch;

Based on the state of the data path between the first data processing device and the communication switch, it is determined whether to switch the first data processing device to a controlled mode.
The data processing system according to any one of claims 7-10, wherein the controller, when monitoring the state of the first data processing device, is configured to:

In response to the state of the first data processing device being an abnormal state, it is determined to switch the first data processing device to a controlled mode.
The data processing system according to any one of claims 7-11, wherein the controller, before sending the second control instruction to the target second data processing device, is further configured to:

Based on the state of the second data processing device, a target second data processing device to be switched to the master mode is determined from among the second data processing devices.
The data processing system according to claim 12, wherein the controller, based on the state of the second data processing device, determines from the second data processing device to switch to the master mode When targeting a second data processing device, for:

In response to the state of the first data processing device being an abnormal state, determining a candidate data processing device from the second data processing device, and detecting the state of the candidate data processing device; in response to the candidate data The status of the processing device is normal, and the candidate data processing device is determined as the target second data processing device;

The controller is further configured to: in response to the state of the candidate data processing device being an abnormal state, determine a new candidate data processing device from the second data processing device, and return to detecting the candidate data processing device The step of whether the state of the data processing device is normal.
A data processing system according to claim 12 or 13, characterized in that,

The controller, when determining from the second data processing device a target second data processing device to be switched to master mode, is further configured to read type information from an alternative data processing device; in response The read type information is preset type information, and the candidate data processing device is determined as the target second data processing device.
The data processing system according to any one of claims 7-14, wherein the controller sends a first control instruction to the first data processing device, and sends a second control command to the target second data processing device. When controlling instructions, it is used to:

Send a reset signal to the first data processing device and the target second data processing device; after the reset signal is sent successfully, send a first control instruction to the first data processing device, and send a first control instruction to the target second data processing device The device sends a second control instruction;

The first data processing device, when switching its own mode to the controlled mode in response to receiving the first control instruction, is configured to: perform a reset in response to receiving the reset signal; and after completing the reset, respond upon receiving the first control instruction, switch the own mode to the controlled mode;

The target second data processing device, when switching its own mode to the master mode in response to receiving the second control instruction, is configured to: perform a reset in response to receiving the reset signal; and after completing the reset, In response to receiving the second control instruction, switch its own mode to the master mode.
The data processing system according to claim 15, wherein the controller is further configured to: respond to receiving a successful switching signal sent by the first data processing device and the target second data processing device , sending a release reset signal to the first data processing device and the target second data processing device;

The first data processing device, in response to receiving the reset release signal, releases the reset;

The target second data processing device releases the reset in response to receiving the reset release signal.
The data processing system according to claim 15 or 16, wherein the controller is further connected to the data processing device through a bus;

The controller, when sending a reset signal to the first data processing device and the target second data processing device, is configured to: send data to the first data processing device and the target second data processing device through the bus The processing means sends a reset signal.
A board, comprising: the data processing device according to any one of claims 1-6, or the data processing system according to any one of claims 7-17.
A data processing method, applied to the data processing device according to any one of claims 1-6; the data processing method comprises:

In response to receiving the port gating signal, the multiplexer gating the first transmission path or the second transmission path used by the data processing chip to obtain the configuration information;

The data processing chip acquires first configuration information in response to the first transmission path being selected, and determines its own mode as the master mode based on the first configuration information; in response to the selection of the second transmission path In general, the second configuration information is acquired, and based on the second configuration information, the self mode is determined as the controlled mode.
A data processing method, applied to the data processing system according to any one of claims 7-17; the data processing method comprises:

The controller monitors the status of the first data processing device; in response to the status indication, switches the first data processing device to a controlled mode, sends a first control command to the first data processing device, and sends a target the second data processing device sends a second control instruction;

The first data processing device switches its own mode to the controlled mode in response to receiving the first control instruction;

The target second data processing device switches its own mode to the master mode in response to receiving the second control instruction.