CN112256512B - GLINK bus-based verification and test universal system - Google Patents
GLINK bus-based verification and test universal system Download PDFInfo
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- CN112256512B CN112256512B CN202011161261.3A CN202011161261A CN112256512B CN 112256512 B CN112256512 B CN 112256512B CN 202011161261 A CN202011161261 A CN 202011161261A CN 112256512 B CN112256512 B CN 112256512B
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- 238000012360 testing method Methods 0.000 title claims abstract description 167
- 238000012795 verification Methods 0.000 title claims abstract description 15
- 230000005540 biological transmission Effects 0.000 claims abstract description 42
- 230000002457 bidirectional effect Effects 0.000 claims abstract description 6
- 238000012545 processing Methods 0.000 claims abstract description 4
- 239000013307 optical fiber Substances 0.000 claims description 10
- 230000003993 interaction Effects 0.000 claims description 3
- 230000000694 effects Effects 0.000 claims 1
- 238000004891 communication Methods 0.000 description 3
- 230000000052 comparative effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
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- 230000003287 optical effect Effects 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test buses, lines or interfaces, e.g. stuck-at or open line faults
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/273—Tester hardware, i.e. output processing circuits
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The invention discloses a verification and test universal system based on a GLINK bus, which comprises a first chip and a second chip, wherein the first chip and the second chip are connected in a bidirectional manner; the first chip is used for constructing N test channels to obtain corresponding test data and sending the corresponding test data to the second chip, the second chip is used for processing and displaying the test data in real time, and N is a positive integer. The invention can verify and test the influence of different transmission media, different transmission distances and equalizer on GLINK bus transmission at the same time; the compatibility of different transceivers on GLINK bus transmission under the same condition and the feasibility of the external SerDes chip in speed reduction transmission can be verified; the device can be used as a general GLINK bus test device for detecting and testing other GLINK bus devices.
Description
Technical Field
The invention relates to the technical field of communication control, in particular to a verification and test universal system based on a GLINK bus.
Background
The carrier rocket control system is used for controlling the state of the rocket in flight, and in the actual flight process, the carrier rocket can be subjected to various interferences from the carrier rocket and the outside, and a great amount of information exchange is needed between the units of the system. The traditional bus transmission has low data communication rate, poor anti-interference capability and poor network interconnection capability, and can not meet the requirements of a control bus of a future carrier rocket control system.
The GLINK bus technology has the characteristics of high transmission rate, strong anti-interference capability and the like, can greatly improve control performance, is widely applied to future integrated electronic systems, realizes the conversion from a traditional aerospace electrical system to a new-generation integrated electronic system, and promotes the development of equipment to integration, integration and miniaturization. However, different transmission mediums, different transmission distances, different transceivers and the presence or absence of an equalizer have certain influence on the transmission reliability of the GLINK bus, and research and test of influence caused by different conditions can provide references and solutions for future carrier rocket control systems when the GLINK bus is realized and applied.
Disclosure of Invention
Aiming at the problem of verifying the transmission reliability of a GLINK bus in the prior art, the invention provides a GLINK bus-based verification and test universal system, which constructs 10 GLINK bus test channels by adopting a classical architecture of FPGA+DSP, is used for testing and verifying the influence of different transmission media, different transmission distances, different transceivers, equalizer and the like on the transmission reliability of the GLINK bus, and can also be used for testing the communication capability of other GLINK bus devices.
In order to achieve the above object, the present invention provides the following technical solutions:
The verification and test universal system based on the GLINK bus comprises a first chip and a second chip, wherein the first chip and the second chip are connected in a bidirectional manner;
The first chip is used for constructing N test channels to obtain corresponding test data and sending the corresponding test data to the second chip, the second chip is used for processing and displaying the test data in real time, and N is a positive integer.
Preferably, the first chip is an FPGA chip, and the second chip is a DSP chip; the first chip performs data interaction with the second chip through an EMIF interface.
Preferably, the first chip is further provided with a video output/input interface and an RS232 serial port; the second chip is provided with a power interface and a reset interface.
Preferably, a first test channel is connected to the 1 port of the first chip, and the first test channel comprises a first transceiver and a first connector; the 2 port of the first chip is connected with a second test channel, and the second test channel comprises an equalizer, a first transceiver and a first connector; the first test channel and the second test channel are used for comparing and testing the transmission influence of the equalizer on the GLINK bus when the first connector is externally connected.
Preferably, a third test channel is connected to the 3 port of the first chip, and the third test channel includes a second transceiver and a first connector; the first test channel and the third test channel are used for comparing and testing the compatibility of different transceivers to the GLINK bus.
Preferably, a fourth test channel is connected to the 4 port of the first chip, and the fourth test channel comprises a first transceiver and a second connector; the first test channel and the fourth test channel are used for connecting transmission lines of different mediums to the GLINK bus in comparison with the test connector.
Preferably, a fifth test channel is connected to the 5-port of the first chip, and the fifth test channel includes an equalizer, a second transceiver and a second connector; a 6 port of the first chip is connected with a sixth test channel, and the sixth test channel comprises an equalizer, a transformer and a second connector; the fifth test channel and the sixth test channel are used for comparing and testing the transmission influence of different mediums on the GLINK bus.
Preferably, the 7-port of the first chip is connected with a seventh test channel, and the seventh test channel comprises a third chip, a second transceiver and a second connector; the 8 port of the first chip is connected with an eighth test channel, and the eighth test channel comprises a third chip, an equalizer, a second transceiver and a second connector; the seventh test channel and the eighth test channel are used for comparing and testing whether the transmission speed of the GLINK bus is influenced by the onboard equalizer when the third chip is arranged.
Preferably, the 9 ports of the first chip are connected with a passive optical fiber interface, and the 10 ports of the first chip are connected with an active optical fiber interface, so as to verify the transmission influence of different types of optical fiber interfaces on the GLINK bus.
Preferably, each test channel is provided as a main channel and a standby channel.
In summary, due to the adoption of the technical scheme, compared with the prior art, the invention has at least the following beneficial effects:
The invention can verify and test the influence of different transmission media, different transmission distances and equalizer on GLINK bus transmission at the same time; the compatibility of different transceivers on GLINK bus transmission under the same condition and the feasibility of the external SerDes chip in speed reduction transmission can be verified; the device can be used as a general GLINK bus test device for detecting and testing other GLINK bus devices.
Description of the drawings:
Fig. 1 is a schematic diagram of a generic system for authentication and testing based on a GLINK bus according to an exemplary embodiment of the present invention.
Fig. 2 is a schematic diagram of a standby test channel and a primary test channel according to an exemplary embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to examples and embodiments. It should not be construed that the scope of the above subject matter of the present invention is limited to the following embodiments, and all techniques realized based on the present invention are within the scope of the present invention.
In the description of the present invention, it should be understood that the terms "longitudinal," "transverse," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like indicate orientations or positional relationships based on the orientation or positional relationships shown in the drawings, merely to facilitate describing the present invention and simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present invention.
As shown in FIG. 1, the invention provides a GLINK bus-based universal verification and test system, which comprises a first chip and a second chip, wherein the first chip and the second chip are connected in a bidirectional manner, namely, data interaction is carried out through an EMIF interface; the first chip is used for constructing a test channel to obtain test data and sending the test data to the second chip, and the second chip is used for processing the test data.
In this embodiment, the first chip may be an FPGA chip, and the second chip may be a DSP chip.
In this embodiment, N (e.g., 10) test channels are constructed on the first chip to respectively verify the influence of different transmission media, different transmission distances, whether an equalizer and different transceivers affect the transmission of the GLINK bus, and each test channel is independent of the other test channel. Meanwhile, a video output/input interface and an RS232 serial port are arranged on the first chip; the second chip is provided with a power interface and a reset interface.
The 1 port of the first chip is connected with a first test channel, the first test channel comprises a first transceiver and a first connector, namely, the 1 port of the first chip is connected with the first transceiver in a bidirectional way, and the first transceiver is connected with the first connector in a bidirectional way. The first transceiver is a domestic transceiver and can adopt a TP-link series; the first connector is a super five/six type connector.
The 2 port of the first chip is connected with a second test channel, and the second test channel comprises an equalizer, a first transceiver and a first connector which are sequentially connected.
The 3 port of the first chip is connected with a third test channel, and the third test channel comprises a second transceiver and a first connector which are sequentially connected. The second transceiver is an inlet transceiver and may be of the optoCAN-HS series.
The 4 port of the first chip is connected with a fourth test channel, and the fourth test channel comprises a first transceiver and a second connector which are connected in sequence. The second connector may be a 1394 connector.
The 5 ports of the first chip are connected with a fifth test channel, and the fifth test channel comprises an equalizer, a second transceiver and a second connector which are sequentially connected.
The 6 ports of the first chip are connected with a sixth test channel, and the sixth test channel comprises an equalizer, a transformer and a second connector which are sequentially connected.
And a seventh test channel is connected to the 7 port of the first chip and comprises a third chip, a second transceiver and a second connector which are sequentially connected. The third chip is a Serdes chip.
An 8 port of the first chip is connected with an eighth test channel, and the eighth test channel comprises a third chip, an equalizer, a second transceiver and a second connector which are sequentially connected. The third chip is a Serdes chip.
The 9 port of the first chip is connected with a traditional optical interface (passive optical fiber module); the 10-port of the first chip is connected to an active optical interface (active fiber optic module).
In this embodiment, each test channel adopts a redundant design, and a completely identical standby channel is designed to prevent the main channel from influencing the test result due to the bad state. And meanwhile, whether the test channel is normal can be verified through the comparison analysis of the test data of the standby channel and the main channel. If the test data of the two channels are close, the test channels are normal; if the error of the test data of the two channels is larger (the error can be preset), the abnormal condition of the test channels is indicated, and the problem should be solved immediately.
Fig. 2 illustrates a first test channel, with the remaining test channels being similar in structure. The Rx (including Rx+ and Rx-) ports and the Tx (including Tx+ and Tx-) ports of the 1 port of the first chip are respectively connected through a first transceiver and a first connector, the power supply of the first transceiver is connected with Vcc, and the ground is connected with GND. The Rx port may be set as a standby channel and the Tx port as a main channel; or the Tx port is set as the standby channel and the Rx port is set as the main channel.
In this embodiment, the first test channel and the third test channel are used for comparing and testing the first connector externally connected, and respectively carrying data when the first transceiver and the second transceiver are carried out, so as to verify the transmission influence of different transceivers on the GLINK bus, i.e. verify whether the first transceiver and the second transceiver have compatibility.
The first test channel and the second test channel are used for comparing and testing the data of the external first connector and the data of the onboard equalizer, so as to verify whether the onboard equalizer has transmission influence on the GLINK bus when the external first connector (super five/six connectors) is externally connected.
The first test channel and the fourth test channel are used for comparing and testing data when the first transceiver is carried, the first connector (super five/six type connector) and the second connector (1394 connector) are respectively connected in an external mode, and therefore the transmission influence of transmission lines (super five/six type line/1394 line) of different mediums, which are connected with the comparison test connector in an external mode, on the GLINK bus is verified.
The fourth test channel and the fifth test channel are used for comparing and testing whether the second connector is loaded with the equalizer or not, so as to verify whether the equalizer is loaded or not when the second connector is externally connected or not to influence transmission of the GLINK bus.
The second test channel and the sixth test channel are used for comparing and testing data of the carrying equalizer and the first transceiver and the transformer respectively so as to verify the transmission influence of the comparing transceiver and the transformer on the GLINK bus.
The fifth test channel and the sixth test channel are used for carrying the equalizer and the second connector in a comparative test to verify the transmission influence of different mediums (transceiver and transformer) in the comparative test on the GLINK bus.
The seventh test channel and the eighth test channel are used for comparing and testing whether the equalizer is carried when the external third chip, the second transceiver and the second connector are carried, so as to verify whether the equalizer is carried when the third chip is arranged, namely the feasibility of the transmission influence, namely the speed reduction transmission, of the GLINK bus is verified. The seventh test channel and the eighth test channel are connected with the first chip through I/O pins, each 1 channel is provided with 20I/O receiving pins and 20I/O transmitting pins, 2 transmitting signals of 8 cores are formed at the second connector end, and the second connector is externally connected with the signals.
The ninth test channel and the tenth test channel are used for comparing and testing data externally connected with the active optical fiber module and the passive optical fiber module respectively so as to verify the transmission influence of different types of optical fiber modules on the GLINK bus.
In this embodiment, the GLINK bus, the RS232 serial port, and the video input/output interface are initially configured on the first chip, and then any one of the test channels is selected for verification test, and after the verification test data is processed by the second chip, the test data or the test result is displayed in real time.
It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples of carrying out the invention and that various changes in form and details may be made therein without departing from the spirit and scope of the invention.
Claims (9)
1. The verification and test universal system based on the GLINK bus is characterized by comprising a first chip and a second chip, wherein the first chip and the second chip are connected in a bidirectional manner;
The first chip is used for constructing N test channels to obtain corresponding test data and sending the corresponding test data to the second chip, the second chip is used for processing and displaying the test data in real time, and N is a positive integer;
The 1 port of the first chip is connected with a first test channel, and the first test channel comprises a first transceiver and a first connector; the 2 port of the first chip is connected with a second test channel, and the second test channel comprises an equalizer, a first transceiver and a first connector; the first test channel and the second test channel are used for comparing and testing the transmission influence of the equalizer on the GLINK bus when the first connector is externally connected.
2. The universal system for verifying and testing based on a GLINK bus as defined in claim 1, wherein the first chip is an FPGA chip and the second chip is a DSP chip; the first chip performs data interaction with the second chip through an EMIF interface.
3. The universal system for verifying and testing based on a GLINK bus as defined in claim 1, wherein the first chip is further provided with a video input/output interface and an RS232 serial port; the second chip is provided with a power interface and a reset interface.
4. A universal GLINK bus based verification and test system as defined in claim 3, wherein the 3 port of the first chip is connected with a third test channel comprising a second transceiver and a first connector; the first test channel and the third test channel are used for comparing and testing the compatibility of different transceivers to the GLINK bus.
5. A universal GLINK bus based verification and test system as defined in claim 3, wherein the 4 port of the first chip is connected with a fourth test channel, the fourth test channel comprising a first transceiver and a second connector; the first test channel and the fourth test channel are used for connecting transmission lines of different mediums to the GLINK bus in comparison with the test connector.
6. The universal GLINK bus based verification and test system of claim 1, wherein the 5 port of the first chip is connected with a fifth test channel comprising an equalizer, a second transceiver and a second connector; a 6 port of the first chip is connected with a sixth test channel, and the sixth test channel comprises an equalizer, a transformer and a second connector; the fifth test channel and the sixth test channel are used for comparing and testing the transmission influence of different mediums on the GLINK bus.
7. The universal GLINK bus based verification and test system of claim 1, wherein the 7 port of the first chip is connected to a seventh test channel comprising a third chip, a second transceiver and a second connector; the 8 port of the first chip is connected with an eighth test channel, and the eighth test channel comprises a third chip, an equalizer, a second transceiver and a second connector; the seventh test channel and the eighth test channel are used for comparing and testing whether the transmission speed of the GLINK bus is influenced by the onboard equalizer when the third chip is arranged.
8. The universal system for verifying and testing a GLINK bus as defined in claim 1, wherein the 9 ports of the first chip are connected to a passive optical fiber interface and the 10 ports of the first chip are connected to an active optical fiber interface to verify the transmission effect of different types of optical fiber interfaces on the GLINK bus.
9. A universal GLINK bus based verification and test system as defined in claim 1, wherein each test channel is configured as a primary channel and a backup channel.
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| CN202011161261.3A CN112256512B (en) | 2020-10-27 | 2020-10-27 | GLINK bus-based verification and test universal system |
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