CN112256512A - General verification and test system based on GLINK bus - Google Patents
General verification and test system based on GLINK bus Download PDFInfo
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- CN112256512A CN112256512A CN202011161261.3A CN202011161261A CN112256512A CN 112256512 A CN112256512 A CN 112256512A CN 202011161261 A CN202011161261 A CN 202011161261A CN 112256512 A CN112256512 A CN 112256512A
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- 238000012360 testing method Methods 0.000 title claims abstract description 167
- 238000012795 verification Methods 0.000 title claims abstract description 19
- 230000005540 biological transmission Effects 0.000 claims abstract description 44
- 238000012545 processing Methods 0.000 claims abstract description 4
- 239000013307 optical fiber Substances 0.000 claims description 10
- 230000002457 bidirectional effect Effects 0.000 claims description 3
- 230000003993 interaction Effects 0.000 claims description 3
- 238000010200 validation analysis Methods 0.000 claims 1
- 238000012812 general test Methods 0.000 abstract description 2
- 238000004891 communication Methods 0.000 description 3
- 230000002159 abnormal effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000010835 comparative analysis Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
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- 238000005516 engineering process Methods 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test buses, lines or interfaces, e.g. stuck-at or open line faults
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/273—Tester hardware, i.e. output processing circuits
Abstract
The invention discloses a general verification and test system based on a GLINK bus, which comprises a first chip and a second chip, wherein the first chip is connected with the second chip in a two-way manner; the first chip is used for constructing N testing channels to obtain corresponding testing data and sending the testing data to the second chip, the second chip is used for processing and displaying the testing data in real time, and N is a positive integer. By the invention, the influence of different transmission media, different transmission distances and the existence of an equalizer on the GLINK bus transmission can be verified and tested at the same time; the compatibility of different transceivers to GLINK bus transmission under the same condition and the feasibility of speed reduction transmission of the external SerDes chip can be verified; the test device can be used as a general test device of the GLINK bus and used for detecting and testing other GLINK bus devices.
Description
Technical Field
The invention relates to the technical field of communication control, in particular to a general verification and test system based on a GLINK bus.
Background
The carrier rocket control system is used for controlling the state of the carrier rocket in flight, and in the actual flight process, the carrier rocket can be interfered by self and outside, and a large amount of information needs to be exchanged among all units of the system. The traditional bus transmission has low data communication rate, poor anti-interference capability and poor network interconnection capability, and cannot meet the requirement of a control bus of a future carrier rocket control system.
The GLINK bus technology has the characteristics of high transmission rate, strong anti-interference capability and the like, can greatly improve the control performance, is widely applied to future integrated electronic systems, realizes the conversion of the traditional aerospace electrical system to a new generation integrated electronic system, and promotes the development of equipment to integration, integration and miniaturization. However, different transmission media, different transmission distances, different transceivers, and the presence or absence of equalizers have certain influence on the transmission reliability of the GLINK bus, and the influence brought by different conditions can be researched and tested, so that a reference and solution scheme can be provided for realizing and applying the GLINK bus by a carrier rocket control system in the future.
Disclosure of Invention
Aiming at the problem of verifying the transmission reliability of the GLINK bus in the prior art, the invention provides a verification and test universal system based on the GLINK bus, which is used for testing and verifying the influence of different transmission media, different transmission distances, different transceivers, whether equalizers exist or not, and the like on the transmission reliability of the GLINK bus by adopting a classical architecture of FPGA and DSP and can also be used for testing the communication capacity of other GLINK bus equipment.
In order to achieve the purpose, the invention provides the following technical scheme:
a general verification and test system based on a GLINK bus comprises a first chip and a second chip, wherein the first chip and the second chip are connected in a bidirectional mode;
the first chip is used for constructing N testing channels to obtain corresponding testing data and sending the testing data to the second chip, the second chip is used for processing and displaying the testing data in real time, and N is a positive integer.
Preferably, the first chip is an FPGA chip, and the second chip is a DSP chip; and the first chip performs data interaction with the second chip through an EMIF interface.
Preferably, the first chip is further provided with a video output and input interface and an RS232 serial port; the second chip is provided with a power interface and a reset interface.
Preferably, a port 1 of the first chip is connected with a first test channel, and the first test channel includes a first transceiver and a first connector; the 2 port of the first chip is connected with a second test channel, and the second test channel comprises an equalizer, a first transceiver and a first connector; the first test channel and the second test channel are used for comparing and testing the transmission influence of the carried equalizer on the GLINK bus when the external first connector is connected.
Preferably, the 3-port of the first chip is connected with a third test channel, and the third test channel includes a second transceiver and a first connector; the first test channel and the third test channel are used for comparing and testing the compatibility of different transceivers to the GLINK bus.
Preferably, a fourth test channel is connected to the 4-port of the first chip, and the fourth test channel includes a first transceiver and a second connector; the first test channel and the fourth test channel are used for testing the transmission influence of transmission lines of different media externally connected with the connector on the GLINK bus.
Preferably, a fifth test channel is connected to the 5-port of the first chip, and the fifth test channel includes an equalizer, a second transceiver, and a second connector; a port 6 of the first chip is connected with a sixth test channel, and the sixth test channel comprises an equalizer, a transformer and a second connector; and the fifth test channel and the sixth test channel are used for comparing and testing the transmission influence of different media on the GLINK bus.
Preferably, the 7 ports of the first chip are connected with a seventh test channel, and the seventh test channel includes a third chip, a second transceiver and a second connector; the 8 port of the first chip is connected with an eighth test channel, and the eighth test channel comprises a third chip, an equalizer, a second transceiver and a second connector; and the seventh test channel and the eighth test channel are used for comparing and testing the influence of whether an equalizer is carried on the transmission speed of the GLINK bus when the third chip is arranged.
Preferably, the 9 ports of the first chip are connected with passive optical fiber interfaces, and the 10 ports of the first chip are connected with active optical fiber interfaces, so as to verify the transmission influence of different kinds of optical fiber interfaces on the GLINK bus.
Preferably, each test channel is provided as a main channel and a spare channel.
In summary, due to the adoption of the technical scheme, compared with the prior art, the invention at least has the following beneficial effects:
by the invention, the influence of different transmission media, different transmission distances and the existence of an equalizer on the GLINK bus transmission can be verified and tested at the same time; the compatibility of different transceivers to GLINK bus transmission under the same condition and the feasibility of speed reduction transmission of the external SerDes chip can be verified; the test device can be used as a general test device of the GLINK bus and used for detecting and testing other GLINK bus devices.
Description of the drawings:
fig. 1 is a schematic diagram of a general verification and test system based on a GLINK bus according to an exemplary embodiment of the present invention.
FIG. 2 is a schematic diagram of a standby test channel and a main test channel according to an exemplary embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to examples and embodiments. It should be understood that the scope of the above-described subject matter is not limited to the following examples, and any techniques implemented based on the disclosure of the present invention are within the scope of the present invention.
In the description of the present invention, it is to be understood that the terms "longitudinal", "lateral", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, indicate orientations or positional relationships based on those shown in the drawings, and are used merely for convenience of description and for simplicity of description, and do not indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated, and thus, are not to be construed as limiting the present invention.
As shown in fig. 1, the present invention provides a general verification and test system based on a GLINK bus, which includes a first chip and a second chip, wherein the first chip and the second chip are connected in a bidirectional manner, that is, data interaction is performed through an EMIF interface; the first chip is used for constructing a test channel to obtain test data and sending the test data to the second chip, and the second chip is used for processing the test data.
In this embodiment, the first chip may be an FPGA chip, and the second chip may be a DSP chip.
In this embodiment, N (e.g., 10) test channels are constructed on the first chip to respectively verify the influence of different transmission media, different transmission distances, the presence or absence of an equalizer, and different transceivers on the transmission of the GLINK bus, and each test channel is independent from each other. Meanwhile, a video output and input interface and an RS232 serial port are arranged on the first chip; the second chip is provided with a power interface and a reset interface.
The port 1 of the first chip is connected with a first test channel, and the first test channel comprises a first transceiver and a first connector, namely, the port 1 of the first chip is bidirectionally connected with the first transceiver, and the first transceiver is bidirectionally connected with the first connector. The first transceiver is a domestic transceiver and can adopt TP-link series; the first connector is a super five/six type connector.
The 2 ports of the first chip are connected with a second test channel, and the second test channel comprises an equalizer, a first transceiver and a first connector which are connected in sequence.
The 3 ports of the first chip are connected with a third test channel, and the third test channel comprises a second transceiver and a first connector which are sequentially connected. The second transceiver is an ingress transceiver, which may be of the optoCAN-HS series.
The 4 ports of the first chip are connected with a fourth test channel, and the fourth test channel comprises a first transceiver and a second connector which are connected in sequence. The second connector may employ a 1394 connector.
And the 5 port of the first chip is connected with a fifth test channel, and the fifth test channel comprises an equalizer, a second transceiver and a second connector which are connected in sequence.
And the 6 port of the first chip is connected with a sixth test channel, and the sixth test channel comprises an equalizer, a transformer and a second connector which are sequentially connected.
And the 7 port of the first chip is connected with a seventh test channel, and the seventh test channel comprises a third chip, a second transceiver and a second connector which are connected in sequence. The third chip is a Serdes chip.
And the 8 port of the first chip is connected with an eighth test channel, and the eighth test channel comprises a third chip, an equalizer, a second transceiver and a second connector which are connected in sequence. The third chip is a Serdes chip.
The 9 ports of the first chip are connected with a traditional optical interface (a passive optical fiber module); the 10 ports of the first chip are connected with source optical interfaces (active fiber optic modules).
In this embodiment, each test channel adopts a redundancy design, and a completely identical standby channel is designed to prevent the main channel from generating a bad state to affect the test result. Meanwhile, whether the test channel is normal or not can be verified through comparative analysis of the test data of the standby channel and the main channel. If the test data of the two channels are close to each other, the test channels are normal; if the error of the test data of the two channels is large (the error can be preset), the abnormal condition of the test channel is indicated, and the abnormal condition is solved immediately.
FIG. 2 shows a first test channel, which is similar in structure to the rest of the test channels. The Rx (including Rx + and Rx-) port and the Tx (including Tx + and Tx-) port of the 1 port of the first chip are respectively connected through a first transceiver and a first connector, the power supply end of the first transceiver is Vcc, and the ground end of the first transceiver is GND. The Rx port may be set as a standby channel and the Tx port may be set as a main channel; or the Tx port is set as a standby channel and the Rx port is set as a main channel.
In this embodiment, the first test channel and the third test channel are used for a comparison test, and are both externally connected with the first connector, and respectively carry data of the first transceiver and the second transceiver, so as to verify whether the transmission influence of different transceivers on the GLINK bus, i.e., whether the compatibility exists.
The first test channel and the second test channel are used for comparing and testing data of the external first connector and carrying the equalizer, so that the transmission influence of the external first connector (super five/six type connector) on the GLINK bus can be verified.
The first test channel and the fourth test channel are used for carrying a first transceiver in a comparison test and respectively externally connecting a first connector (ultra-five/six type connector) and a second connector (1394 connector) to verify the transmission influence of a transmission line (ultra-five/six type line/1394 line) externally connecting different media on the GLINK bus by the comparison test connector.
The fourth test channel and the fifth test channel are used for carrying the second connector in a contrast test mode, and whether data carrying the equalizer exist or not is verified so that whether the transmission influence of the equalizer on the GLINK bus exists or not when the second connector is externally connected is verified.
The second test channel and the sixth test channel are used for carrying the equalizer in a comparison test, and carrying data of the first transceiver and data of the transformer respectively so as to verify the transmission influence of the comparison transceiver and the data of the transformer on the GLINK bus.
The fifth test channel and the sixth test channel are used for carrying out comparison test on the equalizer and the second connector so as to verify the transmission influence of different media (transceivers and transformers) in comparison test on the GLINK bus.
The seventh test channel and the eighth test channel are used for comparing and testing whether data carrying the equalizer exists or not when the external third chip, the second transceiver and the second connector are carried, so that the feasibility of speed reduction transmission, namely the transmission influence of the equalizer carried on the GLINK bus, when the third chip is arranged, is verified. The seventh test channel and the eighth test channel are connected with the first chip through I/O pins, each 1 channel has 20I/O receiving pins and 20I/O sending pins, 2 sending and 2 receiving signals of 8 cores are formed at the second connector end, and then the second connector is externally connected.
And the ninth test channel and the tenth test channel are used for comparing and testing data respectively externally connected with the active optical fiber module and the passive optical fiber module so as to verify the transmission influence of different types of optical fiber modules on the GLINK bus.
In this embodiment, a GLINK bus, an RS232 serial port, and a video output/input interface are initially configured on a first chip, any test channel is selected for verification test, and after verification test data is processed by a second chip, the test data or test results are displayed in real time.
It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples for carrying out the invention, and that various changes in form and details may be made therein without departing from the spirit and scope of the invention in practice.
Claims (10)
1. A general verification and test system based on a GLINK bus is characterized by comprising a first chip and a second chip, wherein the first chip and the second chip are connected in a bidirectional mode;
the first chip is used for constructing N testing channels to obtain corresponding testing data and sending the testing data to the second chip, the second chip is used for processing and displaying the testing data in real time, and N is a positive integer.
2. The GLINK bus based verification and test universal system of claim 1, wherein said first chip is an FPGA chip and said second chip is a DSP chip; and the first chip performs data interaction with the second chip through an EMIF interface.
3. The GLINK bus-based verification and test universal system as claimed in claim 1, wherein said first chip is further provided with a video output and input interface and an RS232 serial port; the second chip is provided with a power interface and a reset interface.
4. The GLINK bus based verification and test universal system of claim 1, wherein a first test channel is connected to a port 1 of the first chip, the first test channel comprising a first transceiver and a first connector; the 2 port of the first chip is connected with a second test channel, and the second test channel comprises an equalizer, a first transceiver and a first connector; the first test channel and the second test channel are used for comparing and testing the transmission influence of the carried equalizer on the GLINK bus when the external first connector is connected.
5. The GLINK bus based verification and test universal system of claim 4, wherein a third test channel is connected to the 3 port of the first chip, the third test channel comprising a second transceiver and a first connector; the first test channel and the third test channel are used for comparing and testing the compatibility of different transceivers to the GLINK bus.
6. The GLINK bus based verification and test universal system of claim 4, wherein a fourth test channel is connected to the 4 port of the first chip, the fourth test channel comprising a first transceiver and a second connector; the first test channel and the fourth test channel are used for testing the transmission influence of transmission lines of different media externally connected with the connector on the GLINK bus.
7. The GLINK bus based verification and test universal system of claim 1, wherein a fifth test channel is connected to 5 ports of the first chip, the fifth test channel comprising an equalizer, a second transceiver and a second connector; a port 6 of the first chip is connected with a sixth test channel, and the sixth test channel comprises an equalizer, a transformer and a second connector; and the fifth test channel and the sixth test channel are used for comparing and testing the transmission influence of different media on the GLINK bus.
8. The GLINK bus based verification and test universal system of claim 1, wherein the 7 ports of the first chip are connected with a seventh test channel, the seventh test channel comprises a third chip, a second transceiver and a second connector; the 8 port of the first chip is connected with an eighth test channel, and the eighth test channel comprises a third chip, an equalizer, a second transceiver and a second connector; and the seventh test channel and the eighth test channel are used for comparing and testing the influence of whether an equalizer is carried on the transmission speed of the GLINK bus when the third chip is arranged.
9. The GLINK bus based verification and test universal system as claimed in claim 1, wherein 9 ports of the first chip are connected with passive optical fiber interfaces, and 10 ports of the first chip are connected with active optical fiber interfaces, so as to verify the transmission influence of different kinds of optical fiber interfaces on the GLINK bus.
10. The GLINK bus based validation and test universal system of claim 1, wherein each test channel is configured as a primary channel and a backup channel.
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| CN202011161261.3A CN112256512A (en) | 2020-10-27 | 2020-10-27 | General verification and test system based on GLINK bus |
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| CN202011161261.3A CN112256512A (en) | 2020-10-27 | 2020-10-27 | General verification and test system based on GLINK bus |
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