CN110646723A

CN110646723A - Bus interface test circuit and method

Info

Publication number: CN110646723A
Application number: CN201810677371.1A
Authority: CN
Inventors: 姜文奇; 苏孟豪; 刘苏
Original assignee: Loongson Technology Corp Ltd
Current assignee: Loongson Technology Corp Ltd
Priority date: 2018-06-27
Filing date: 2018-06-27
Publication date: 2020-01-03
Anticipated expiration: 2038-06-27
Also published as: CN110646723B

Abstract

The invention provides a bus interface test circuit and a method. The circuit includes: the data processing unit, the first selection circuit and the second selection circuit; the data processing unit is respectively connected with the input end of the coding circuit, the input end of the first selection circuit, the output end of the first differential circuit, the output end of the decoding circuit and the output end of the second selection circuit; the input end of the first selection circuit is connected with the output end of the coding circuit, and the output end of the first selection circuit is respectively connected with the input end of the first differential circuit and the input end of the second selection circuit; the input end of the second selection circuit is connected with the output end of the second differential circuit, and the output end of the second selection circuit is connected with the input end of the decoding circuit. According to the invention, the data processing unit respectively processes and transmits the test data through the N test channels corresponding to the N test modes, and the test result is obtained according to the output data and the test data of the N test channels, so that the troubleshooting of the SpaceWire bus interface circuit is realized.

Description

Bus interface test circuit and method

Technical Field

The invention relates to the technical field of aerospace and aviation tests, in particular to a bus interface test circuit and a bus interface test method.

Background

With the continuous development of the aerospace industry, the continuous expansion of the aerospace technology and the application field, the scale and the information amount of data processing performed by an aerospace equipment system are increasingly huge, the requirement on large-scale and complex data processing technology is more urgent, and the high-speed transmission of the aerospace satellite-borne information interaction network is increasingly important. The SpaceWire bus (space high-speed data transmission bus) is a serial, high-speed, point-to-point and full-duplex serial bus network proposed by the European Space Agency (ESA) in 2003, the transmission code rate is 2-400Mbps, and encoding and decoding and reliable transmission of data are realized by two pairs of differential signals in the transmitting and receiving directions.

Based on the advantages of the SpaceWire bus, the SpaceWire bus is widely applied to the field of the current aerospace and aviation communication systems. In the existing application engineering communication network, when any one of the SpaceWire bus interface circuits fails, the whole communication network is generally required to be combined, and the correctness of each circuit in the SpaceWire bus interface circuit is verified by a test instrument, so that the operation is inconvenient, the efficiency is low, and the cost is high.

Therefore, a bus interface test circuit capable of determining a fault of each of the SpaceWire bus interface circuits is needed.

Disclosure of Invention

The invention provides a bus interface test circuit and a bus interface test method, which aim to solve the problems of inconvenient operation, low efficiency and higher cost caused by the fact that the SpaceWire bus interface can be tested only by a whole communication network and a test instrument in the prior art.

In a first aspect, the present invention provides a bus interface test circuit, which is applied to test a SpaceWire bus interface circuit, where the SpaceWire bus interface circuit includes: coding circuit, first difference circuit, second difference circuit and the decoding circuit that connects gradually, bus interface test circuit includes: the data processing unit, the first selection circuit and the second selection circuit; wherein the content of the first and second substances,

the data processing unit is respectively connected with the input end of the coding circuit, the input end of the first selection circuit, the output end of the first differential circuit, the output end of the decoding circuit and the output end of the second selection circuit;

the input end of the first selection circuit is also connected with the output end of the coding circuit, and the output end of the first selection circuit is respectively connected with the input end of the first differential circuit and the input end of the second selection circuit;

the input end of the second selection circuit is also connected with the output end of the second differential circuit, and the output end of the second selection circuit is also connected with the input end of the decoding circuit;

the data processing unit is used for setting N test modes, wherein N is a positive integer;

the data processing unit is also used for acquiring test data; processing and transmitting the test data through N test channels corresponding to the N test modes respectively, wherein the test modes correspond to the test channels one by one, and each test channel comprises at least one circuit in the SpaceWire bus interface circuit;

the data processing unit is further configured to obtain a test result according to the output data of the N test channels and the test data, where the test result is used to indicate whether each circuit in the SpaceWire bus interface circuit has a fault.

Optionally, the data processing unit includes: the system comprises a mode configuration module, a data generation module and a data verification module; wherein the content of the first and second substances,

the output end of the mode configuration module is connected with the input end of the data generation module, and the output end of the data generation module is respectively connected with the input end of the coding circuit, the input end of the first selection circuit and the input end of the data verification module;

the input end of the data checking module is also respectively connected with the output end of the decoding circuit, the output end of the second selection circuit and the output end of the first differential circuit,

the mode configuration module is used for setting the N test modes;

the data generating module is used for acquiring test data, sending the test data to the data checking module, and processing and transmitting the test data through N test channels corresponding to the N test modes respectively;

and the data checking module is used for obtaining the test result according to the output data of the N test channels and the test data.

Optionally, the data processing unit is a processor.

Optionally, the N test patterns include: the system comprises a full-channel test mode, a differential channel test mode, a coding and decoding channel test mode and a single-channel test mode; wherein the content of the first and second substances,

the data checking module is configured to obtain a first determination result according to the output data of the test channel in the full-path test mode and the test data, where the first determination result is used to determine whether each circuit in the test channel in the full-path test mode has a fault; obtaining a second judgment result according to the output data of the test channel in the differential path test mode and the test data, wherein the second judgment result is used for determining whether each circuit in the test channel in the differential path test mode has a fault; obtaining a third judgment result according to the output data of the test channel in the coding and decoding channel test mode and the test data, wherein the third judgment result is used for determining whether each circuit in the test channel in the coding and decoding channel test mode has a fault; obtaining a fourth judgment result according to the output data of the test channel in the single-path test mode and the test data, wherein the fourth judgment result is used for determining whether each circuit in the test channel has a fault in the single-path test mode; and obtaining the test result according to the first judgment result, the second judgment result, the third judgment result and the fourth judgment result.

Optionally, when the test mode corresponding to the test channel is the full channel test mode, the mode configuration module is configured to determine that the test channel is a channel formed by the encoding circuit, the first differential circuit, the second differential circuit, and the decoding circuit; sending a full-channel test instruction to the data generation module;

the data generation module is used for processing and transmitting the test data through each circuit in the test channel when the full-channel test instruction is received;

the data checking module is configured to receive output data of the test channel, and determine whether the output data is the same as the test data, so as to obtain the first determination result.

Optionally, when the test mode corresponding to the test channel is a differential path test mode, the mode configuration module is configured to determine that the test channel is a channel formed by the first selection circuit, the first differential circuit, the second differential circuit, and the second selection circuit; sending a differential channel test instruction to the data generation module;

the data generation module is used for processing and transmitting the test data through each circuit in the test channel when the differential channel test instruction is received;

and the data checking module is used for receiving the output data of the test channel, judging whether the output data is the same as the test data or not and obtaining the second judgment result.

Optionally, when the test mode corresponding to the test channel is a codec channel test mode, the mode configuration module is configured to determine that the test channel is a channel formed by the encoding circuit, the first selection circuit, the second selection circuit, and the decoding circuit; sending a coding and decoding path test instruction to the data generation module;

the data generation module is used for processing and transmitting the test data through each circuit in the test channel when the coding and decoding channel test instruction is received;

and the data checking module is used for receiving the output data of the test channel, judging whether the output data is the same as the test data or not and obtaining a third judgment result.

Optionally, when the test mode corresponding to the test channel is a single-channel test mode, the mode configuration module is configured to determine that the test channel is a channel formed by the encoding circuit and the first differential circuit; and sending a single-channel test instruction to the data generation module;

the data generation module is used for processing and transmitting the test data through each circuit in the test channel when the single-channel test instruction is received;

the data checking module is configured to predict the test data in the same processing procedure as that of each circuit in the test channel to obtain predicted data, receive output data of the test channel, determine whether the output data is the same as the predicted data, and obtain the fourth determination result.

Optionally, the first differential circuit is connected to the second differential circuit by a cable or an external device.

In a second aspect, the present invention provides a bus interface testing method, including:

acquiring test data and N test patterns, wherein N is a positive integer;

processing and transmitting the test data through N test channels corresponding to the N test patterns respectively to obtain output data of the N test channels, wherein the test patterns correspond to the test channels one to one, each test channel comprises at least one circuit in a SpaceWire bus interface circuit, and the SpaceWire bus interface circuit comprises: the encoding circuit, the first differential circuit, the second differential circuit and the decoding circuit are connected in sequence;

and obtaining a test result according to the output data of the N test channels and the test data, wherein the test result is used for indicating whether each circuit in the SpaceWire bus interface circuit has a fault.

Optionally, the N test patterns include: the test device comprises a full-channel test mode, a differential channel test mode, a coding and decoding channel test mode and a single-channel test mode.

Optionally, the obtaining a test result according to the output data of the N test channels and the test data includes:

obtaining a first judgment result according to the output data of the test channel in the full-channel test mode and the test data, wherein the first judgment result is used for determining whether each circuit in the test channel has a fault in the full-channel test mode;

obtaining a second judgment result according to the output data of the test channel in the differential path test mode and the test data, wherein the second judgment result is used for determining whether each circuit in the test channel in the differential path test mode has a fault;

obtaining a third judgment result according to the output data of the test channel in the coding and decoding channel test mode and the test data, wherein the third judgment result is used for determining whether each circuit in the test channel has a fault in the coding and decoding channel test mode;

obtaining a fourth judgment result according to the output data of the test channel in the single-path test mode and the test data, wherein the fourth judgment result is used for determining whether each circuit in the test channel has a fault in the single-path test mode;

and obtaining the test result according to the first judgment result, the second judgment result, the third judgment result and the fourth judgment result.

Optionally, the obtaining a first determination result according to the output data of the test channel in the full-channel test mode and the test data includes:

determining the test channel as a channel formed by the encoding circuit, the first differential circuit, the second differential circuit and the decoding circuit and a full-channel test instruction according to the fact that the test mode corresponding to the test channel is a full-channel test mode;

processing and transmitting the test data through each circuit in the test channel according to the full-channel test instruction to obtain output data of the test channel;

and judging whether the output data is the same as the test data or not to obtain the first judgment result.

Optionally, the obtaining a second determination result according to the output data from the test channel in the differential path test mode and the test data includes:

determining that the test channel is a channel formed by a first selection circuit, the first differential circuit, the second differential circuit and a second selection circuit and a differential channel test instruction according to the fact that the test mode corresponding to the test channel is a differential channel test mode;

processing and transmitting the test data through each circuit in the test channel according to the differential channel test instruction to obtain output data of the test channel;

and judging whether the output data is the same as the test data or not to obtain a second judgment result.

Optionally, the obtaining a third determination result according to the output data of the test channel in the codec path test mode and the test data includes:

determining the test channel as a channel formed by the coding circuit, the first selection circuit, the second selection circuit and the decoding circuit and a coding and decoding channel test instruction according to the fact that the test mode corresponding to the test channel is a coding and decoding channel test mode;

processing and transmitting the test data through each circuit in the test channel according to the coding and decoding channel test instruction to obtain output data of the test channel;

and judging whether the output data is the same as the test data or not to obtain a third judgment result.

Optionally, the obtaining a fourth determination result according to the output data from the test channel in the single-channel test mode and the test data includes:

determining the test channel as a channel formed by the coding circuit and the first differential circuit and a single-channel test instruction according to the fact that the test mode corresponding to the test channel is a single-channel test mode;

processing and transmitting the test data through each circuit in the test channel according to the single-channel test instruction to obtain output data of the test channel;

predicting the test data in the same processing process with each circuit in the test channel to obtain predicted data;

and judging whether the output data is the same as the prediction data or not to obtain a fourth judgment result.

In a third aspect, the present invention provides a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements the bus interface testing method of the second aspect.

In a fourth aspect, the present invention provides an electronic device comprising:

a processor; and

a memory for storing executable instructions of the processor;

wherein the processor is configured to perform the bus interface test method of the second aspect via execution of the executable instructions.

The bus interface test circuit and the method provided by the invention configure N test modes through the data processing unit, the test modes correspond to the test channels one by one, and each test channel covers at least one circuit in the SpaceWire bus interface circuit. The data processing unit obtains output data of the N test channels through each circuit in the N test channels by setting the first selection circuit and the second selection circuit, and obtains a test result according to the received output data of the N test channels and the corresponding test data, so that a tester can judge whether each circuit in the SpaceWire bus interface circuit has a fault according to the test result. The invention solves the problems of inconvenient operation, low efficiency and higher cost caused by the fact that the SpaceWire bus interface can be tested only through the whole communication network and a testing instrument in the prior art, realizes the testing requirement of verifying the SpaceWire bus interface circuit through the bus interface testing circuit, and can flexibly and comprehensively carry out function testing and fault judgment on the SpaceWire bus interface circuit, thereby greatly reducing the risk occurrence probability of the SpaceWire bus interface circuit and improving the reliability and the work efficiency of the SpaceWire bus interface circuit.

Drawings

In order to clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a schematic structural diagram of a bus interface test circuit according to the present invention;

FIG. 2 is a schematic structural diagram of a bus interface test circuit according to the present invention;

FIG. 3 is a flow chart of a bus interface testing method provided by the present invention;

FIG. 4 is a flow chart of a bus interface testing method provided by the present invention;

FIG. 5 is a flow chart of a bus interface testing method provided by the present invention;

FIG. 6 is a flow chart of a bus interface testing method provided by the present invention;

FIG. 7 is a flowchart of a bus interface testing method provided by the present invention;

FIG. 8 is a flowchart of a bus interface testing method provided by the present invention;

fig. 9 is a schematic diagram of a hardware structure of the electronic device provided in the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments obtained by persons of ordinary skill in the art based on the embodiments of the present invention without any creative efforts shall fall within the protection scope of the embodiments of the present invention.

Fig. 1 is a schematic structural diagram of a bus interface test circuit provided in the present invention, and as shown in fig. 1, a bus interface test circuit 20 in this embodiment may perform function test and fault judgment on each circuit in a SpaceWire bus interface circuit 10, where the SpaceWire bus interface circuit 10 may include: the encoding circuit 11, the first differential circuit 12, the second differential circuit 13 and the decoding circuit 14 are connected in sequence, namely, the basic components of the SpaceWire bus interface circuit 10. In this embodiment, specific forms of the encoding circuit 11, the decoding circuit 14, the first differential circuit 12, and the second differential circuit 13 are not limited, and it is only necessary that signals transmitted by the encoding circuit 11, the decoding circuit 14, the first differential circuit 12, and the second differential circuit 13 satisfy the internal communication protocol standard IEEE 1355/1995. For example, the encoding circuit 11 may employ a Data/Strobe (D/S) encoding circuit, the decoding circuit 14 employs a D/S decoding circuit, and both the first Differential circuit 12 and the second Differential circuit 13 may employ a Low-Voltage Differential Signaling (LVDS) circuit.

Further, in order to implement the function test and fault judgment of the SpaceWire bus interface circuit 10, the bus interface test circuit 20 of the present embodiment can set N test modes and N test channels, the test modes correspond to the test channels one by one, the generated test data is processed and transmitted through the N test channels corresponding to the N test modes to obtain the output data of the N test channels, and the test result is obtained according to the test data and the output data of the N test channels, thereby indicating whether each circuit in the SpaceWire bus interface circuit 10 has a fault according to the test result, meeting the test requirement of verifying the SpaceWire bus interface circuit 10, flexibly and comprehensively judging the faults of the SpaceWire bus interface circuit 10, thereby greatly reducing the risk occurrence probability of the SpaceWire bus interface circuit 10 and improving the reliability and the work efficiency of the SpaceWire bus interface circuit 10. Next, a specific configuration of the bus interface test circuit 20 will be described in detail by a specific embodiment.

For convenience of description, IN this embodiment, taking IN as an example that IN represents an input terminal and OUT represents an output terminal, with continuing to refer to fig. 1, the bus interface test circuit 20 of this embodiment may include: a data processing unit 21, a first selection circuit 22, and a second selection circuit 23; wherein the content of the first and second substances,

the data processing unit 21 is respectively connected with the input end of the encoding circuit 11, the input end of the first selection circuit 22, the output end of the first differential circuit 12, the output end of the decoding circuit 14 and the output end of the second selection circuit 23;

the input end of the first selection circuit 22 is further connected with the output end of the encoding circuit 11, and the output end of the first selection circuit 22 is respectively connected with the input end of the first differential circuit 12 and the input end of the second selection circuit 23;

the input end of the second selection circuit 23 is further connected with the output end of the second differential circuit 13, and the output end of the second selection circuit 23 is further connected with the input end of the decoding circuit 14;

a data processing unit 21 configured to set N test patterns, where N is a positive integer;

the data processing unit 21 is further configured to obtain test data; the test data are processed and transmitted through N test channels corresponding to N test modes respectively, the test modes correspond to the test channels one by one, and each test channel comprises at least one circuit in the SpaceWire bus interface circuit 10;

the data processing unit 21 is further configured to obtain a test result according to the output data and the test data of the N test channels, where the test result is used to indicate whether each circuit in the SpaceWire bus interface circuit 10 has a fault.

Specifically, when each circuit in the SpaceWire bus interface circuit 10 works normally, the output data obtained by the initial data passing through the encoding circuit 11, the first differential circuit 12, the second differential circuit 13 and the decoding circuit 14 is the same as the initial data. For example, the initial data transmitted to the encoding circuit 11 is an initial sequence, and the encoding circuit 11 performs D/S encoding on the initial sequence to generate a single-ended D/S data signal, which can be converted into LVDS differential signal pairs, respectively Dout +/Dout-, Sout +/Sout-via the first differential circuit 12. The first differential circuit 12 may be connected to the second differential circuit 13 through a cable or an external device, the second differential circuit 13 may convert the LVDS differential signal pair (Dout +/Dout-, Sout +/Sout-) into a single-ended D/S data signal, and the signal is D/S decoded by the decoding circuit 14, and the obtained sequence is still the initial sequence.

When the encoding circuit 11 and the decoding circuit 14 in the SpaceWire bus interface circuit 10 work normally, the output data obtained by the initial data passing through the encoding circuit 11 and the decoding circuit 14 is the same as the initial data. For example, the initial data transmitted to the encoding circuit 11 is an initial sequence, the encoding circuit 11 performs D/S encoding on the initial sequence to generate a single-ended D/S data signal, and the signal is D/S decoded by the decoding circuit 14, so that the obtained sequence is still the initial sequence.

When the first differential circuit 12 and the second differential circuit 13 in the SpaceWire bus interface circuit 10 work normally, the initial data passes through the first differential circuit 12 and the second differential circuit 13, and the obtained output data is the same as the initial data. For example, the initial signal may be converted into an LVDS differential signal pair, respectively Dout +/Dout-, Sout +/Sout-, by the first differential circuit 12, and then converted into the initial signal by the second differential circuit 13.

When the encoding circuit 11 and the first differential circuit 12 in the SpaceWire bus interface circuit 10 normally operate, since the initial data is known, and the operation principle of the encoding circuit 11 and the first differential circuit 12 is also known, the data obtained by the initial data passing through the encoding circuit 11 and the first differential circuit 12 can be predicted to obtain predicted data, and then the output data obtained by the initial data passing through the encoding circuit 11 and the first differential circuit 12 can be obtained to obtain output data, wherein the output data and the predicted data should be the same. For example, the initial signal may be converted into an LVDS differential signal pair (Dout +/Dout-, Sout +/Sout-, respectively) via the encoding circuit 11 and the first differential circuit 12, and the LVDS differential signal pair (i.e., Dout +/Dout-, Sout +/Sout-, respectively) may also be directly obtained from the initial signal in view of the operation principle of the encoding circuit 11 and the first differential circuit 12.

Further, based on the above principle, whether each circuit in the SpaceWire bus interface circuit 10 has a fault can be detected by testing the SpaceWire bus interface circuit 10 by the bus interface test circuit 20. The data processing unit 21 in the bus interface test circuit 20 is configured to obtain test data, where the data processing unit 21 may generate the test data by itself, and may also receive the test data input by a tester, where the test data may be a data packet with a fixed number of bits, a random data packet, or a data packet including a packet header and a check bit, and the specific form of the test data is not limited in this embodiment, and only needs to satisfy that the SpaceWire bus interface circuit 10 can recognize and process the test data (that is, satisfy the external bus communication protocol standard IEEE 1596.3).

Further, since the data processing unit 21 is connected to the input terminal of the encoding circuit 11 and the input terminal of the first selection circuit 22, and the output terminal of the first selection circuit 22 is connected to the input terminal of the first differential circuit 12 and the input terminal of the second selection circuit 23, the input terminal of the test data acquired by the data processing unit 21 may have multiple selections, specifically, may be the encoding circuit 11, and may also be transmitted to the first differential circuit 12 or the second selection circuit 23 through the first selection circuit 22.

Furthermore, since the data processing unit 21 is further connected to the output terminal of the first differential circuit 12, the output terminal of the decoding circuit 14, and the output terminal of the second selection circuit 23, the data processing unit 21 can change the output terminal of the test data after being processed by the test channel, specifically, the output terminal can be the first differential circuit 12, the output terminal can also be the decoding circuit 14, and the output terminal can also be the second selection circuit 23.

Further, different input ends and different output ends of the test data enable the bus interface test circuit 20 to include a plurality of test channels, and all the test channels can include all the circuits in the SpaceWire bus interface circuit 10, so that the test data can pass through each circuit in the SpaceWire bus interface circuit 10, and further the fault judgment of the SpaceWire bus interface circuit 10 is realized.

Specifically, the data processing unit 21 in the bus interface test circuit 20 may also be configured to set N test modes, and the test modes correspond to the test channels one to one, where the test modes may be set according to actual requirements, and the specific forms of the test modes and the test channels are not limited in this embodiment.

Further, the data processing unit 21 may send the test data to the test channel corresponding to the test mode for processing and transmission by selecting the test mode of the current test. The data processing unit 21 may transmit the test data in a circulating manner, or may transmit the test data at a fixed time and length, and the specific manner of transmitting the test data by the data processing unit 21 is not limited in this embodiment. Therefore, each circuit in the test channel corresponding to the test mode can process and transmit the test data, and the output data can be obtained from the output end of the test channel.

Further, since the output of each test channel (i.e. the output of the last circuit of each test channel) is connected to the data processing unit 21, therefore, for each of the N test patterns, the data processing unit 21 can not only obtain the test data used in the test enable pattern, but also receive the output data output by the test channel corresponding to the test pattern, and can compare whether the test data and the output data are the same, or comparing whether the predicted data and the output data corresponding to the test data are the same or not to verify whether each circuit in the test channel has a fault or not, in this way, the data processing unit 21 can obtain a test result based on each output data and the corresponding test data, whether each circuit in the SpaceWire bus interface circuit 10 has a fault is judged through the test result.

Here, it should be noted that: in this embodiment, the data processing unit 21, the first selection circuit 22, and the second selection circuit 23 may be integrated circuits built with components, or may be integrated chips, and the specific forms of the data processing unit 21, the first selection circuit 22, and the second selection circuit 23 are not limited in this embodiment. In addition, the number and types of ports corresponding to the input end and the output end of each of the data processing unit 21, the first selection circuit 22 and the second selection circuit 23 are not limited in this embodiment.

The bus interface test circuit provided in this embodiment configures N test modes through the data processing unit, where the test modes correspond to the test channels one to one, and each test channel covers at least one circuit in the SpaceWire bus interface circuit. The data processing unit obtains output data of the N test channels through each circuit in the N test channels by setting the first selection circuit and the second selection circuit, and obtains a test result according to the received output data of the N test channels and the corresponding test data, so that a tester can judge whether each circuit in the SpaceWire bus interface circuit has a fault according to the test result. The embodiment solves the problems that the operation is inconvenient because the SpaceWire bus interface can be tested only through the whole communication network and the testing instrument in the prior art, the efficiency is low, and the cost is high, the testing requirement for verifying the SpaceWire bus interface circuit is realized through the bus interface testing circuit, the function test and the fault judgment can be flexibly and comprehensively carried out on the SpaceWire bus interface circuit, the risk occurrence probability of the SpaceWire bus interface circuit is greatly reduced, and the reliability and the work efficiency of the SpaceWire bus interface circuit are improved.

First, on the basis of the above-described embodiment, a detailed description is given of a specific structure of the data processing unit 21 in fig. 1 with reference to fig. 2.

Fig. 2 is a schematic structural diagram of a bus interface test circuit provided in the present invention, and as shown in fig. 2, the data processing unit 21 of this embodiment includes: a mode configuration module 211, a data generation module 212 and a data verification module 213; wherein the content of the first and second substances,

the output end of the mode configuration module 211 is connected to the input end of the data generation module 212, and the output end of the data generation module 212 is connected to the input end of the encoding circuit 11, the input end of the first selection circuit 22, and the input end of the data verification module 213;

the input of the data checking module 213 is further connected to the output of the decoding circuit 14, the output of the second selection circuit 23 and the output of the first differential circuit 12,

a mode configuration module 211, configured to set N test modes;

the data generating module 212 is configured to obtain test data, send the test data to the data verifying module 213, and process and transmit the test data through N test channels corresponding to the N test modes respectively;

and the data checking module 213 is configured to obtain a test result according to the output data and the test data of the N test channels.

Specifically, in this embodiment, the mode configuration module 211 may set the test mode in advance by itself, or may agree on different test modes by receiving manual configuration of a tester, which is not limited in this embodiment. And the mode configuration module 211 may distinguish the test modes by the identification code or the form of a code. For example, 00 represents test mode one, 01 represents test mode two, 10 represents test mode three, and 11 represents test mode four. For another example, a represents test mode one, B represents test mode two, C represents test mode three, and D represents test mode four.

Further, when determining the current test mode, the mode configuration module 211 may send an instruction indicating the current test mode to the data generation module 212 through connection with the input terminal of the data generation module 212, so that the data generation module 212 may select and change the input terminal of the test data according to the test mode, and then the data generation module 212 may send the test data to the test channel corresponding to the test mode for processing and transmission. The data generating module 212 may transmit the test data in a circulating manner, or may send the test data at a fixed time and a fixed length, and the specific manner of sending the test data by the data generating module 212 is not limited in this embodiment.

Further, since the output end of each test channel is connected to the input end of the data checking module 213, the data checking module 213 can receive the output data output by each transmission channel. Since the output terminal of the data generating module 212 is connected to the input terminal of the data checking module 213, the data checking module 213 can receive the test data sent by the data generating module 212. Thus, for each of the N test patterns, the data generation module 212 may send test data used at the current test to the data verification module 213, the test data is processed and transmitted through the respective circuits in the test channel corresponding to the test mode, the output data of the test channel can be obtained, the data verification module 213 can receive the output data through the connection of the output end of the test channel, and judge whether the test data and the output data are the same, or comparing whether the predicted data and the output data corresponding to the test data are the same or not, further verifying whether each circuit in the test channel has a fault or not, in this way, the data verification module 213 can obtain the test result according to each output data and the corresponding test data, whether each circuit in the SpaceWire bus interface circuit 10 has a fault is judged through the test result.

Here, it should be noted that: in this embodiment, the mode configuration module 211, the data generation module 212, and the data verification module 213 may be an integrated circuit built with components, or may also be an integrated chip, and the specific forms of the mode configuration module 211, the data generation module 212, and the data verification module 213 are not limited in this embodiment. In addition, the number and types of the ports corresponding to the input end and the output end of each of the mode configuration module 211, the data generation module 212, and the data verification module 213 are not limited in this embodiment.

In addition, besides the implementation of the data processing unit 21 shown in fig. 2, optionally, the data processing unit 21 is a processor. The specific implementation form of the processor is not limited in this embodiment, and only the function that the processor can test each circuit of the SpaceWire bus interface circuit 10 needs to be satisfied.

Next, on the basis of the embodiment shown in fig. 2, in order to detect whether each circuit in the SpaceWire bus interface circuit 10 has a fault, the embodiment may set different test modes to respectively correspond to different test channels, so that all the test channels can include each circuit in the SpaceWire bus interface circuit 10. Next, a specific procedure of the bus interface test circuit 20 in this embodiment performing a test using different test modes will be described in detail.

a data checking module 213, configured to obtain a first determination result according to output data and test data from the test channel in the full-path test mode, where the first determination result is used to determine whether each circuit in the test channel in the full-path test mode has a fault; obtaining a second judgment result according to the output data and the test data of the test channel in the differential channel test mode, wherein the second judgment result is used for determining whether each circuit in the test channel in the differential channel test mode has a fault; obtaining a third judgment result according to the output data and the test data of the test channel in the coding and decoding channel test mode, wherein the third judgment result is used for determining whether each circuit in the test channel has a fault in the coding and decoding channel test mode; obtaining a fourth judgment result according to the output data and the test data of the test channel in the single-path test mode, wherein the fourth judgment result is used for determining whether each circuit in the test channel has a fault in the single-path test mode; and obtaining a test result according to the first judgment result, the second judgment result, the third judgment result and the fourth judgment result.

Specifically, the bus interface test circuit 20 may set that the 4 test channels corresponding to the full-path test mode, the differential-path test mode, the codec-path test mode, and the single-path test mode can include all the circuits in the SpaceWire bus interface circuit 10, so that the data check module 213 may obtain the working conditions of all the circuits in the SpaceWire bus interface circuit 10 according to the first determination result, the second determination result, the third determination result, and the fourth determination result, and further determine the test result that can indicate the working condition of each circuit in the SpaceWire bus interface circuit 10. The present embodiment does not limit the specific form of the test result.

Optionally, when the test mode corresponding to the test channel is the full-channel test mode, the mode configuration module 211 is configured to determine that the test channel is a channel formed by the encoding circuit 11, the first differential circuit 12, the second differential circuit 13, and the decoding circuit 14; and sends a full pass test instruction to the data generation module 212;

the data generation module 212 is configured to, when receiving a full-channel test instruction, process and transmit test data through each circuit in the test channel;

the data checking module 213 is configured to receive the output data of the test channel, and determine whether the output data is the same as the test data, so as to obtain a first determination result, where the first determination result is used to determine whether each circuit in the test channel has a fault.

Specifically, the user may randomly select the test mode through the mode configuration module 211 according to the actual requirement, or the mode configuration module 211 may default the execution sequence of the test mode, and the specific manner in which the mode configuration module 211 selects the configuration mode is not limited in this embodiment. Furthermore, when the test mode is the full-pass test mode, the mode configuration module 211 may determine that the test channel is a channel formed by the encoding circuit 11, the first differential circuit 12, the second differential circuit 13, and the decoding circuit 14, so that the mode configuration module 211 may send a full-pass test instruction to the data generation module 212, so that the data generation module 212 determines that the input end of the test data is the input end of the encoding circuit 11, and then the test data is processed and transmitted through the encoding circuit 11, the first differential circuit 12, the second differential circuit 13, and the decoding circuit 14, and the output end of the decoding circuit 14 obtains the output data and transmits the output data to the data verification module 213. The embodiment does not limit the specific form of the full-path test instruction. For example, the full-path test instruction may be an identification code or a code, etc.

Further, the data checking module 213 obtains a first determination result by determining whether the output data is the same as the test data. The first determination result may be that the output data is the same as the test data, which indicates that each circuit in the test channel can work normally, or that the output data is different from the test data, which indicates that one or more circuits in the test channel have a fault.

Further, if the first determination result is that the output data and the test data are the same, each circuit in the SpaceWire bus interface circuit 10 can work normally, and therefore, the bus interface test circuit 20 does not need to perform a test. If the first determination result is that the output data and the test data are different, the SpaceWire bus interface circuit 10 has a faulty circuit, but it cannot be determined which circuit has a fault, and therefore the bus interface test circuit 20 needs to change the test mode and continue to test the SpaceWire bus interface circuit 10.

Optionally, when the test mode corresponding to the test channel is a differential channel test mode, the mode configuration module 211 is configured to determine that the test channel is a channel formed by the first selection circuit 22, the first differential circuit 12, the second differential circuit 13, and the second selection circuit 23; and sends a differential path test command to the data generation module 212;

the data generation module 212 is configured to, when receiving the differential channel test instruction, process and transmit test data through each circuit in the test channel;

the data checking module 213 is configured to receive the output data of the test channel, and determine whether the output data is the same as the test data, so as to obtain a second determination result, where the second determination result is used to determine whether each circuit in the test channel has a fault.

Specifically, the user may randomly select the test mode through the mode configuration module 211 according to the actual requirement, or the mode configuration module 211 may default the execution sequence of the test mode, and the specific manner in which the mode configuration module 211 selects the configuration mode is not limited in this embodiment. Furthermore, when the test mode is the differential path test mode, the mode configuration module 211 may determine that the test channel is a channel formed by the first selection circuit 22, the first differential circuit 12, the second differential circuit 13, and the second selection circuit 23, and thus, the mode configuration module 211 may send a differential path test instruction to the data generation module 212, so that the data generation module 212 determines that the input end of the test data is the input end of the first selection circuit 22, and then processes and transmits the test data through the first selection circuit 22, the first differential circuit 12, the second differential circuit 13, and the second selection circuit 23, and obtains output data from the output end of the second selection circuit 23 and transmits the output data to the data verification module 213. In this embodiment, the specific form of the differential path test command is not limited. For example, the differential path test instruction may be an identification code or a code or the like.

Further, the data checking module 213 obtains a second determination result by determining whether the output data is the same as the test data. The second determination result may be that the output data is the same as the test data, indicating that each circuit in the test channel can work normally, or that the output data is different from the test data, indicating that one or more circuits in the test channel have a fault.

Further, if the second determination result is that the output data and the test data are the same, both the first differential circuit 12 and the second differential circuit 13 can operate normally, and it is impossible to determine whether a fault occurs in the encoding circuit 11 and the decoding circuit 14. If the second determination result is that the output data and the test data are different, at least one of the first differential circuit 12 and the second differential circuit 13 has a failure, and it is not possible to determine whether a failure has occurred in the encoding circuit 11 and the decoding circuit 14. Therefore, the bus interface test circuit 20 needs to change the test mode to continue testing the SpaceWire bus interface circuit 10.

Optionally, when the test mode corresponding to the test channel is a codec channel test mode, the mode configuration module 211 is configured to determine that the test channel is a channel formed by the encoding circuit 11, the first selection circuit 22, the second selection circuit 23, and the decoding circuit 14; and sends a codec path test command to the data generation module 212;

the data generation module 212 is configured to, when receiving the codec channel test instruction, process and transmit test data through each circuit in the test channel;

and the data checking module 213 is configured to receive the output data of the test channel, and determine whether the output data is the same as the test data, so as to obtain a third determination result, where the third determination result is used to determine whether each circuit in the test channel has a fault.

Specifically, the user may randomly select the test mode through the mode configuration module 211 according to the actual requirement, or the mode configuration module 211 may default the execution sequence of the test mode, and the specific manner in which the mode configuration module 211 selects the configuration mode is not limited in this embodiment. Furthermore, when the test mode is the codec path test mode, the mode configuration module 211 may determine that the test channel is a channel formed by the encoding circuit 11, the first selection circuit 22, the second selection circuit 23, and the decoding circuit 14, so that the mode configuration module 211 may send a codec path test instruction to the data generation module 212, so that the data generation module 212 determines that the input end of the test data is the input end of the encoding circuit 11, and then the test data is processed and transmitted through the encoding circuit 11, the first selection circuit 22, the second selection circuit 23, and the decoding circuit 14, and the output end of the decoding circuit 14 obtains the output data and transmits the output data to the data verification module 213. In this embodiment, the specific form of the codec path test instruction is not limited. For example, the codec path test instruction may be an identification code or a code or the like.

Further, the data checking module 213 obtains a third determination result by determining whether the output data is the same as the test data. The third determination result may be that the output data is the same as the test data, which indicates that each circuit in the test channel can work normally, or that the output data is different from the test data, which indicates that one or more circuits in the test channel have a fault.

Further, if the third determination result is that the output data is the same as the test data, both the encoding circuit 11 and the decoding circuit 14 can operate normally, and it is not possible to determine whether a fault occurs in the first differential circuit 12 and the second differential circuit 13. If the third determination result is that the output data and the test data are different, at least one of the encoding circuit 11 and the decoding circuit 14 has a failure, and it is not possible to determine whether or not a failure has occurred in the first differential circuit 12 and the second differential circuit 13. Therefore, the bus interface test circuit 20 needs to change the test mode to continue testing the SpaceWire bus interface circuit 10.

Optionally, when the test mode corresponding to the test channel is a single-channel test mode, the mode configuration module 211 is configured to determine that the test channel is a channel formed by the encoding circuit 11 and the first differential circuit 12; and sends a single-pass test instruction to the data generation module 212;

a data generating module 212, configured to determine that the test channel is a channel formed by the encoding circuit 11 and the first differential circuit 12, and transmit the test data through the test channel;

the data checking module 213 is configured to predict the test data through the same processing procedure as that of each circuit in the test channel to obtain predicted data, receive output data of the test channel, determine whether the output data is the same as the predicted data, and obtain a fourth determination result, where the fourth determination result is used to determine whether the test channel fails.

Specifically, the user may randomly select the test mode through the mode configuration module 211 according to the actual requirement, or the mode configuration module 211 may default the execution sequence of the test mode, and the specific manner in which the mode configuration module 211 selects the configuration mode is not limited in this embodiment. Furthermore, when the test mode is a single-channel test mode, the mode configuration module 211 may determine that the test channel is a channel formed by the encoding circuit 11 and the first differential circuit 12, and thus, the mode configuration module 211 may send a single-channel test instruction to the data generation module 212, so that the data generation module 212 determines that the input end of the test data is the input end of the encoding circuit 11, and then the test data is processed and transmitted through the encoding circuit 11 and the first differential circuit 12, and the output end of the first differential circuit 12 obtains the output data and transmits the output data to the data verification module 213. The present embodiment does not limit the specific form of the single-path test instruction. For example, the single-path test instruction may be an identification code or the like.

Further, since the test data is known, and the working principle of the coding circuit 11 and the first differential circuit 12 in the circuit to be tested is known, the data verification module 213 may predict the test data through the same processing procedure of the coding circuit 11 and the first differential circuit 12 in the circuit to be tested, to obtain predicted data, and then obtain a fourth determination result by determining whether the output data is the same as the predicted data. The fourth determination result may be that the output data is the same as the prediction data, which indicates that each circuit in the test channel can work normally, or that the output data is different from the prediction data, which indicates that one or more circuits in the test channel have a fault.

Further, if the fourth determination result is that the output data is the same as the prediction data, both the encoding circuit 11 and the first differential circuit 12 can operate normally, and it is not possible to determine whether a failure occurs in the decoding circuit 14 and the second differential circuit 13. If the fourth determination result is that the output data and the prediction data are different, at least one of the encoding circuit 11 and the first differential circuit 12 has a failure, and it is not possible to determine whether or not a failure has occurred in the decoding circuit 14 and the second differential circuit 13. Therefore, the bus interface test circuit 20 needs to change the test mode to continue testing the SpaceWire bus interface circuit 10.

Fig. 3 is a flowchart of a bus interface testing method provided by the present invention, and as shown in fig. 3, the bus interface testing method of this embodiment may include:

s301, obtaining test data and N test patterns, wherein N is a positive integer.

S302, processing and transmitting the test data through N test channels corresponding to N test modes respectively to obtain output data of the N test channels, wherein the test modes correspond to the test channels one to one, and each test channel comprises at least one circuit in a SpaceWire bus interface circuit.

And S303, obtaining a test result according to the output data and the test data of the N test channels, wherein the test result is used for indicating whether each circuit in the SpaceWire bus interface circuit has a fault.

Specifically, referring to fig. 1 or fig. 2, the present embodiment uses a bus interface test circuit 20 as an execution main body, wherein the SpaceWire bus interface circuit 10 includes: the bus interface test circuit 20 can generate or receive test data input by a user, and can provide N test modes for the user, and the test channels correspond to the test modes one to one. When the test mode is selected, the bus interface test circuit 20 processes and transmits the test data through the test channel corresponding to the test mode. Because each test channel includes at least one circuit in the SpaceWire bus interface circuit 10, when the test data is transmitted through the test channel, each circuit in the test channel can process and operate the test data, so that the output end of the test channel obtains the output data.

Further, the bus interface test circuit 20 verifies whether each circuit in the test channel has a fault by comparing whether the test data is the same as the output data or comparing whether the prediction data corresponding to the test data is the same as the output data, so that the bus interface test circuit 20 obtains a test result according to the output data and the test data of the N test channels, and determines whether each circuit in the SpaceWire bus interface circuit 10 has a fault according to the test result.

The bus interface test method according to the embodiment of the present invention may be used to implement the technical solution of the circuit embodiment shown in fig. 1, and the implementation principle is similar, and will not be described herein again.

On the basis of the embodiment of fig. 3, a detailed description is given, with reference to fig. 4, of a specific process of obtaining a test result according to the output data and the test data of the N test channels in the embodiment S303.

Fig. 4 is a flowchart of a bus interface testing method provided by the present invention, and as shown in fig. 4, the bus interface testing method of this embodiment may include:

s401, obtaining test data and N test patterns, wherein N is a positive integer.

S402, processing and transmitting the test data through N test channels corresponding to N test modes respectively to obtain output data of the N test channels, wherein the test modes correspond to the test channels one to one, and each test channel comprises at least one circuit in a SpaceWire bus interface circuit.

S401 and S402 are similar to the implementation manners of S301 and S302 in the embodiment of fig. 3, and are not described again here in the embodiment of the present invention.

S4031, obtaining a first determination result according to the output data and the test data from the test channel in the full-pass test mode, where the first determination result is used to determine whether each circuit in the test channel in the full-pass test mode has a fault.

S4032, obtaining a second determination result according to the output data and the test data from the test channel in the differential path test mode, where the second determination result is used to determine whether each circuit in the test channel in the differential path test mode has a fault.

S4033, obtaining a third determination result according to the output data and the test data from the test channel in the codec channel test mode, where the third determination result is used to determine whether each circuit in the test channel in the codec channel test mode has a fault.

S4034, obtaining a fourth determination result according to the output data and the test data from the test channel in the single-pass test mode, where the fourth determination result is used to determine whether each circuit in the test channel has a fault in the single-pass test mode.

And S4035, obtaining a test result according to the first judgment result, the second judgment result, the third judgment result and the fourth judgment result.

Specifically, with reference to fig. 1 or fig. 2, the bus interface test circuit 20 may respectively obtain a first determination result, a second determination result, a third determination result, and a fourth determination result by processing and transmitting transmission data in test channels corresponding to the full-path test mode, the differential path test mode, the coding/decoding path test mode, and the single-path test mode, and may obtain a test result indicating whether each circuit in the SpaceWire bus interface circuit 10 has a fault according to the first determination result, the second determination result, the third determination result, and the fourth determination result.

Here, it should be noted that: there is no chronological sequence between the above-mentioned S4031-S4034, and S4031-S4034 may be executed simultaneously or sequentially.

The bus interface test method according to the embodiment of the present invention may be used to implement the technical solution of the circuit embodiment shown in fig. 2, and the implementation principle is similar, which is not described herein again.

Next, based on the embodiment of fig. 4, a detailed description is given to a specific implementation process of each step in S401 to S405 with reference to fig. 5 to 8, respectively.

Optionally, fig. 5 is a flowchart of a bus interface testing method provided by the present invention, and as shown in fig. 5, the bus interface testing method of this embodiment may include:

s501, determining that the test channel is a channel formed by the coding circuit, the first differential circuit, the second differential circuit and the decoding circuit and a full-channel test instruction according to the fact that the test mode corresponding to the test channel is a full-channel test mode.

And S502, processing and transmitting the test data through each circuit in the test channel according to the full-channel test instruction to obtain the output data of the test channel.

S503, judging whether the output data is the same as the test data or not, and obtaining a first judgment result.

Specifically, with reference to fig. 1 or fig. 2, the bus interface test circuit 20 may determine, according to that the current test mode is the full-pass test mode, a test channel corresponding to the current test mode, and obtain a full-pass test instruction, and under an instruction of the full-pass test instruction, process and transmit test data in the test channel through the encoding circuit 11, the first differential circuit 12, the second differential circuit 13, and the decoding circuit 14, so as to obtain output data, and then obtain a first prediction result by determining whether the output data is the same as the test data.

Optionally, fig. 6 is a flowchart of a bus interface testing method provided by the present invention, and as shown in fig. 6, the bus interface testing method of this embodiment may include:

s601, determining that the test channel is a channel formed by the first selection circuit, the first differential circuit, the second differential circuit and the second selection circuit and a differential channel test instruction according to the fact that the test mode corresponding to the test channel is a differential channel test mode.

And S602, processing and transmitting the test data through each circuit in the test channel according to the differential channel test instruction to obtain the output data of the test channel.

S603, judging whether the output data is the same as the test data or not to obtain a second judgment result.

Specifically, with reference to fig. 1 or fig. 2, the bus interface test circuit 20 may determine a test channel corresponding to the current test mode according to that the current test mode is the differential path test mode, and obtain a differential path test instruction, and under the instruction of the differential path test instruction, process and transmit the test data in the test channel through the first selection circuit 22, the first differential circuit 12, the second differential circuit 13, and the second selection circuit 23, so as to obtain output data, and then obtain a second prediction result by determining whether the output data is the same as the test data.

Optionally, fig. 7 is a flowchart of a bus interface testing method provided by the present invention, and as shown in fig. 7, the bus interface testing method of this embodiment may include:

s701, determining that the test channel is a channel formed by the coding circuit, the first selection circuit, the second selection circuit and the decoding circuit and a coding and decoding channel test instruction according to the fact that the test mode corresponding to the test channel is a coding and decoding channel test mode.

S702, according to the coding and decoding channel test instruction, processing and transmitting the test data through each circuit in the test channel to obtain the output data of the test channel.

And S703, judging whether the output data is the same as the test data or not to obtain a third judgment result.

Specifically, with reference to fig. 1 or fig. 2, the bus interface test circuit 20 may determine a test channel corresponding to the current test mode according to that the current test mode is a codec channel test mode, and obtain a codec channel test instruction, and under the instruction of the codec channel test instruction, process and transmit test data in the test channel through the encoding circuit 11, the first selection circuit 22, the second selection circuit 23, and the decoding circuit 14, so as to obtain output data, and then obtain a third prediction result by determining whether the output data is the same as the test data.

Optionally, fig. 8 is a flowchart of a bus interface testing method provided by the present invention, and as shown in fig. 8, the bus interface testing method of this embodiment may include:

s801, determining that the test channel is a channel formed by the coding circuit and the first differential circuit and a single-channel test instruction according to the fact that the test mode corresponding to the test channel is a single-channel test mode.

S802, according to the single-channel test instruction, processing and transmitting the test data through each circuit in the test channel to obtain the output data of the test channel.

And S803, predicting the test data in the same processing process with each circuit in the test channel to obtain predicted data.

S804, judging whether the output data is the same as the prediction data or not, and obtaining a fourth judgment result.

Specifically, with reference to fig. 1 or fig. 2, the bus interface test circuit 20 may determine a test channel corresponding to the current test mode according to that the current test mode is a single-channel test mode, obtain a single-channel test instruction, process and transmit test data in the test channel through the encoding circuit 11 and the first differential circuit 12 under the instruction of the single-channel test instruction, obtain output data, obtain test data according to the working principle of the encoding circuit 11 and the first differential circuit 12, and obtain a fourth determination result by determining whether the output data is the same as the prediction data.

Fig. 9 is a schematic diagram of a hardware structure of the electronic device provided in the present invention. As shown in fig. 9, the electronic apparatus 90 includes: a memory 91 and a processor 92;

a memory 91 for storing a computer program;

the processor 92 is used for executing the computer program stored in the memory to implement the bus interface testing method in the above embodiments. Reference may be made in particular to the description relating to the method embodiments described above.

Alternatively, the memory 91 may be separate or integrated with the processor 92.

When the memory 91 is a device independent of the processor 92, the electronic device 90 may further include:

a bus 93 for connecting the memory 91 and the processor 92.

The electronic device provided in this embodiment can be used to execute the bus interface testing method, and its implementation manner and technical effect are similar, which are not described herein again.

The present invention also provides a computer-readable storage medium including a computer program for implementing the bus interface test method in the above embodiments.

In the embodiments provided in the present invention, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described device embodiments are merely illustrative, and for example, the division of the modules is only one logical division, and other divisions may be realized in practice, for example, a plurality of modules may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or modules, and may be in an electrical, mechanical or other form.

The modules described as separate parts may or may not be physically separate, and parts displayed as modules may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment.

In addition, functional modules in the embodiments of the present invention may be integrated into one processing unit, or each module may exist alone physically, or two or more modules are integrated into one unit. The unit formed by the modules can be realized in a hardware form, and can also be realized in a form of hardware and a software functional unit.

The integrated module implemented in the form of a software functional module may be stored in a computer-readable storage medium. The software functional module is stored in a storage medium and includes several instructions for enabling a computer device (which may be a personal computer, a server, or a network device) or a processor (processor) to execute some steps of the methods according to the embodiments of the present application.

It should be understood that the Processor may be a Central Processing Unit (CPU), other general purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), etc. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of a method disclosed in connection with the present invention may be embodied directly in a hardware processor, or in a combination of the hardware and software modules within the processor.

The memory may comprise a high-speed RAM memory, and may further comprise a non-volatile storage NVM, such as at least one disk memory, and may also be a usb disk, a removable hard disk, a read-only memory, a magnetic or optical disk, etc.

The bus may be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, an Extended ISA (EISA) bus, or the like. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, the buses in the figures of the present application are not limited to only one bus or one type of bus.

The computer-readable storage medium may be implemented by any type or combination of volatile or non-volatile memory devices, such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic or optical disks. A storage media may be any available media that can be accessed by a general purpose or special purpose computer.

Those of ordinary skill in the art will understand that: all or a portion of the steps of implementing the above-described method embodiments may be performed by hardware associated with program instructions. The program may be stored in a computer-readable storage medium. When executed, the program performs steps comprising the method embodiments described above; and the aforementioned storage medium includes: various media that can store program codes, such as ROM, RAM, magnetic or optical disks.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. The utility model provides a bus interface test circuit which characterized in that, is applied to the test to SpaceWire bus interface circuit, SpaceWire bus interface circuit includes: coding circuit, first difference circuit, second difference circuit and the decoding circuit that connects gradually, bus interface test circuit includes: the data processing unit, the first selection circuit and the second selection circuit; wherein the content of the first and second substances,

2. The circuit of claim 1, wherein the data processing unit comprises: the system comprises a mode configuration module, a data generation module and a data verification module; wherein the content of the first and second substances,

the mode configuration module is used for setting the N test modes;

3. The circuit of claim 1, wherein the data processing unit is a processor.

4. The circuit of any of claims 1-3, wherein the N test modes include: the system comprises a full-channel test mode, a differential channel test mode, a coding and decoding channel test mode and a single-channel test mode; wherein the content of the first and second substances,

5. The circuit of claim 4, wherein when the test mode corresponding to the test channel is the full-path test mode, the mode configuration module is configured to determine that the test channel is a channel formed by the encoding circuit, the first differential circuit, the second differential circuit, and the decoding circuit; sending a full-channel test instruction to the data generation module;

6. The circuit of claim 4, wherein when the test mode corresponding to the test channel is a differential channel test mode, the mode configuration module is configured to determine that the test channel is a channel formed by the first selection circuit, the first differential circuit, the second differential circuit, and the second selection circuit; sending a differential channel test instruction to the data generation module;

7. The circuit of claim 4, wherein when the test mode corresponding to the test channel is a codec path test mode, the mode configuration module is configured to determine that the test channel is a channel formed by the encoding circuit, the first selection circuit, the second selection circuit, and the decoding circuit; sending a coding and decoding path test instruction to the data generation module;

8. The circuit of claim 4, wherein the mode configuration module is configured to determine that the test channel is a channel formed by the encoding circuit and the first differential circuit when the test mode corresponding to the test channel is a single-channel test mode; and sending a single-channel test instruction to the data generation module;

9. The circuit of claim 1, wherein the first differential circuit is connected to the second differential circuit by a cable or an external device.

10. A bus interface test method is characterized by comprising the following steps:

acquiring test data and N test patterns, wherein N is a positive integer;

11. The method of claim 10, wherein the N test patterns comprise: the test device comprises a full-channel test mode, a differential channel test mode, a coding and decoding channel test mode and a single-channel test mode.

12. The method according to claim 10 or 11, wherein obtaining the test result according to the output data of the N test channels and the test data comprises:

13. The method of claim 12, wherein obtaining a first determination based on the output data from the test channel in full pass test mode and the test data comprises:

14. The method of claim 12, wherein obtaining a second determination result based on the output data from the test channel in the differential path test mode and the test data comprises:

15. The method according to claim 12, wherein obtaining a third determination result according to the output data from the test channel in the codec path test mode and the test data comprises:

16. The method of claim 12, wherein obtaining a fourth determination based on the output data from the test channel in the single-pass test mode and the test data comprises:

17. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the bus interface testing method according to any one of claims 10 to 16.

18. An electronic device, comprising:

a processor; and

a memory for storing executable instructions of the processor;

wherein the processor is configured to perform the bus interface testing method of any of claims 10-16 via execution of the executable instructions.