CN112242389A - Micro-system chip configuration SIP - Google Patents
Micro-system chip configuration SIP Download PDFInfo
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- CN112242389A CN112242389A CN202011180245.9A CN202011180245A CN112242389A CN 112242389 A CN112242389 A CN 112242389A CN 202011180245 A CN202011180245 A CN 202011180245A CN 112242389 A CN112242389 A CN 112242389A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
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Abstract
The invention discloses an SIP (session initiation protocol), and belongs to the technical field of SIP system-in-package. The micro-system chip configuration SIP adopts a TSV tube process to longitudinally stack a plurality of micro components to form a micro system, and is packaged and led out through a chip BGA, so that the micro-system chip configuration is realized. The number of the micro-components is 5, welding is carried out sequentially from bottom to top through the bonding pads and the BGA balls, resin filling is carried out on gaps welded in the middle, and a final micro-system chip configuration is formed. The micro system chip configuration SIP is integrated with a DSP minimum system, an FPGA minimum system, a CAN bus interface circuit, an Ethernet interface circuit, a 485 interface circuit, an AD acquisition system, a level conversion interface, an LVDS bus interface, an MLVDS interface circuit and a 429 interface circuit.
Description
Technical Field
The invention relates to the technical field of SIP system-in-package, in particular to a micro-system chip configuration SIP.
Background
At present, most of systems for processing signals used in aerospace are provided with AD acquisition, 485 interfaces, 429 interfaces, LVDS interfaces and other interfaces, and finished circuits are combined into a board card. The adoption of each circuit for welding can occupy larger space and bring the defects of high reliability and high cost. Therefore, the anti-interference capability, the function integration level, the safety and reliability, the installation mode, the cost, the size and the like of the micro-system chip configuration SIP are all the key points for user investigation.
At present, similar products at home and abroad mostly integrate a processor and a numerous interfaces in a tube shell, and although the requirement of system miniaturization is solved to a great extent, the expensive die sinking cost of the tube shell is still very troublesome, and the size integration degree of the tube shell is limited. .
Disclosure of Invention
The invention aims to provide a micro-system chip configuration SIP, which is used for solving the requirements of the traditional aerospace on the reliability, power consumption, cost and size of a signal processing system.
In order to solve the above technical problem, the present invention provides a microsystem chip configuration SIP, which includes:
and a plurality of micro components are longitudinally stacked to form a micro system by adopting a TSV tube process, and are packaged and led out by a chip BGA, so that the chip configuration of the micro system is realized.
Optionally, the number of the micro-components is 5, the bonding pads and the BGA balls are sequentially welded from bottom to top, and gaps welded in the middle are filled with resin, so that a final microsystem chip configuration is formed.
Optionally, the microsystem chip configuration SIP is integrated with a DSP minimum system, an FPGA minimum system, a CAN bus interface circuit, an ethernet interface circuit, a 485 interface circuit, an AD acquisition system, a level conversion interface, an LVDS bus interface, an MLVDS interface circuit, and a 429 interface circuit.
Optionally, the DSP minimal system comprises a digital signal processor FT-C6713J/400, a FLASH HRFL29208 and an SRAM JM64LV25616 to implement the loading and storing extensions of the digital processing functions and programs, while internally uploading the HOLD signal of the DSP minimal system so that no external request is suspended.
Optionally, the FPGA minimum system includes an FPGA JXCLX25 and a configuration chip JXCF32P, and implements processing of an interface and preprocessing of a digital signal, and internally pulls up an EN _ EXT _ SEL signal of the JXCF32P, so that a design partition is controlled by an internal programmable partition selection control bit, and the internal control is in a parallel mode, so that the loading speed is faster.
Optionally, the ethernet interface circuit is formed by 4 JDP83848 and a clock driving circuit JCK25081, so as to implement four ethernet channels; an interface bus of the four-channel Ethernet PHY and the MAC adopts an MII or RMII bus, and a single-path clock signal is expanded into 4 paths of clocks through a clock driving circuit JCK25081, so that the number of off-chip crystal oscillators is reduced.
Optionally, the 485 interface circuit includes 4 JMAX3485 differential transceivers, so as to implement four 485 buses.
Optionally, the AD acquisition system includes 2 pieces of JAD7998, which are expanded into 16 channels, JS3025 is used as a reference voltage source of the JAD7998, and JTXS0108 is used as a level conversion circuit, so that communication between the JAD7998 and various level controllers is realized, a 12-bit and 188KSPS sampling 16-channel ADC is realized, and the AD acquisition system is applicable to the measurement and control field requiring multi-channel sampling, and the input signal range is 0-ref.
Optionally, the CAN bus interface circuit is composed of 4 pieces of JMCP2551 and a decoupling capacitor, so as to implement 4 paths of CAN buses.
Optionally, the MLVDS interface circuit is composed of an 8-way JRMLVD201 differential transceiver.
Optionally, the 429 interface circuit adopts 4 JHI8591 and 4 JHI8596, so as to implement a 4-transmission 4-reception 429 bus interface.
Optionally, the LVDS interface circuit employs JSRLVDS031LV and JSRLVDS032LV, so as to implement a 4-transmission 4-reception LVDS interface.
Optionally, the level conversion interface circuit adopts 3 pieces of JALVC164245, so as to implement 24-bit dual-channel level conversion.
Optionally, the micro-assembly is prepared by the following method: after the PADs of the required chips are placed upwards, each PAD needing interconnection is punched and led out, then lead interconnection is carried out, according to required wiring complexity, a punching layer and a wiring layer are added, all interconnection is completed, then an upper surface PAD is led out, lower surface ball planting is led out, resin filling is carried out on the upper surface PAD, a single micro component is formed, and the top micro component only carries out lower surface ball planting and leading out.
The invention provides a micro-system chip configuration SIP, which is characterized in that a TSV tube process is adopted to longitudinally stack a plurality of micro components to form a micro system, and the micro system is packaged and led out by a chip BGA, so that the micro system chip configuration is realized. The number of the micro-components is 5, welding is carried out sequentially from bottom to top through the bonding pads and the BGA balls, resin filling is carried out on gaps welded in the middle, and a final micro-system chip configuration is formed. The micro system chip configuration SIP is integrated with a DSP minimum system, an FPGA minimum system, a CAN bus interface circuit, an Ethernet interface circuit, a 485 interface circuit, an AD acquisition system, a level conversion interface, an LVDS bus interface, an MLVDS interface circuit and a 429 interface circuit. The processor and various universal interfaces are integrated in a certain size, and high-density integration and multi-functionalization are realized; a domestic bare chip is selected, so that the domestic rate is high, and the board distribution area is small; the interface modules are isolated from each other, so that the associated multi-part circuits can be isolated without influencing signal transmission, and the parts are not electrically connected, thereby achieving the purpose of inhibiting interference. The SIP is extremely low in size and power consumption, low-power-consumption components are preferentially selected on the premise of ensuring performance, and reliable and safe operation under most military environments is met.
The invention has the following beneficial effects:
(1) for the bare chip, a silicon substrate is adopted for bonding, and fillers are coated around the bare chip, so that the reliability of the module is enhanced;
(2) integration of a 1553B bus is realized in an FPGA minimum system by instantiating a 1553B soft core, so that control of the 1553B bus is more conveniently realized;
(3) welding is directly adopted among all the stacked modules, high-lead and low-lead solders can be selected according to practical application modes, and reliability of the SIP is improved;
(4) the SIP can be directly welded on a PCB (printed Circuit Board) or a ceramic substrate after being molded, so that the application range is enlarged.
Drawings
FIG. 1 is a schematic diagram of a stack of a microsystem chip configuration SIP provided by the present invention;
FIG. 2 is a schematic diagram of a portion of a DSP minimum system FLASH and SRAM of a microsystem chip configuration SIP;
FIG. 3 is a schematic diagram of a CAN bus interface circuit of a micro-system chip-based configuration SIP;
FIG. 4 is a schematic diagram of an Ethernet interface circuit of a microsystem chip-based configuration SIP;
FIG. 5 is a circuit schematic diagram of the 4485 interface of the microsystem chip-based configuration SIP;
FIG. 6 is a schematic diagram of an AD acquisition system of a micro-system chip configuration SIP;
FIG. 7 is a schematic diagram of a level translation interface of a micro system on-chip configuration SIP;
FIG. 8 is a schematic diagram of an LVDS bus interface of a micro-system chip-based configuration SIP;
FIG. 9 is a schematic diagram of an MLVDS interface circuit of a micro-system chip configuration SIP;
FIG. 10 is a schematic diagram of the 429 interface circuit of the microsystem chip-based configuration SIP;
FIG. 11 is a component diagram of M1 micro components of a micro system chip configuration SIP;
FIG. 12 is a component diagram of the M2 micro components of the SIP chip configuration;
FIG. 13 is a component diagram of the M3 micro components of the SIP chip configuration;
FIG. 14 is a component diagram of the M4 micro component of the SIP chip configuration;
fig. 15 is a diagram of the M5 micro component composition of the microsystem chip configuration SIP.
Detailed Description
The microsystem chip configuration SIP of the present invention will be described in detail with reference to the accompanying drawings and specific embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Example one
The invention provides a microsystem chip configuration SIP, the stacking structure of which is shown in figure 1, a TSV tube process is adopted to stack five micro-components of M1, M2, M3, M4 and M5 to form a microsystem, and the microsystem chip configuration is realized by leading out chip BGA packages with the size of 20mm by 3 mm. Taking M1 as an example, after placing the PAD of the required chip upwards, punching and leading out each PAD which needs to be interconnected, then interconnecting leads, properly increasing a punching layer and a wiring layer according to the required wiring complexity, leading out an upper surface PAD and a lower surface ball-planting and leading out all the interconnected PADs, and filling resin to the PADs to form a single micro-component. The microcomponents M2, M3 and M4 are similar, and the topmost microcomponent M5 is only subjected to lower surface ball mounting extraction; sequentially welding the bonding pad and the BGA ball from bottom to top, and filling resin into the gap between the middle welding parts to form the final microsystem chip configuration; the chip is formed into a whole, so that the chip is reliable and stable in the subsequent use process. The SIP can be directly welded on a printed board for use, and can also be led out for use by ceramic tube shells or plastic package packages according to requirements.
The micro system chip configuration SIP is provided with a DSP minimum system, a CAN bus interface circuit, an Ethernet interface circuit, a 485 interface circuit, an AD acquisition system, a level conversion interface, an LVDS bus interface, an MLVDS interface circuit and a 429 interface circuit, and each micro component is subjected to appropriate up-down pulling or decoupling capacitance processing, so that the board-level use convenience is improved.
The DSP minimum system is a DSP main control chip and comprises a digital signal processor FT-C6713J/400, a FLASH HRFL29208 and an SRAM JM64LV25616, wherein the digital signal processor FT-C6713/400, the SRAM JM 3564 LV25616 realizes the loading and storage expansion of digital processing functions and programs, and meanwhile, the HOLD signal of the DSP minimum system is uploaded internally, so that the external request is not hung. FIG. 2 shows a schematic diagram of a portion of FLASH and SRAM. The FPGA minimum system is an FPGA preprocessor, which comprises an FPGA JXCLX25 and a configuration chip JXCF32P, and is used for processing an interface and a digital signal, internally pulling up an EN _ EXT _ SEL signal of the JXCF32P, controlling a design partition by an internal programmable partition selection control bit, and enabling the internal control to be in a parallel mode so as to enable the loading speed to be higher; in the FPGA, the functions of the 1553B protocol chip are integrated in a soft core mode, so that the size is effectively reduced, and the use universality is increased. The CAN bus interface circuit is composed of 4 JMCP2551 pieces and decoupling capacitors as shown in figure 3, and 4 paths of CAN buses are realized. The Ethernet interface circuit is composed of 4 JDPs 83848 and a clock driving circuit JCK25081 as shown in FIG. 4, so as to realize four-path Ethernet; an interface bus of the four-channel Ethernet PHY and the MAC adopts an MII or RMII bus, and a single-channel clock signal is expanded into 4-channel clocks through a clock driving circuit JCK25081, so that the number of off-chip crystal oscillators is reduced, the area of a user board card can be saved, and the EMC design of a user is optimized. The 485 interface circuit is shown in fig. 5, and comprises 4 pieces of JMAX3485 differential transceivers, so as to realize four 485 buses. The AD acquisition system comprises 2 pieces of JAD7998, 16 channels are expanded, JS3025 is used as a JAD7998 reference voltage source, JTXS0108 is used as a level conversion circuit, communication between the JAD7998 and various level controllers is achieved, a 16-channel ADC with 12-bit and 188KSPS sampling is achieved, and the AD acquisition system is suitable for the measurement and control field needing multi-channel sampling, and the input signal range is 0-ref. The principle of the level conversion interface circuit is shown in fig. 7, and the level conversion interface circuit comprises three JALVC164245, so that 24-bit dual-channel level conversion is realized, and decoupling capacitor integration of a power supply is performed inside the level conversion interface circuit. The LVDS interface circuit is shown in fig. 8 and includes a JSRLVDS031LV and a JSRLVDS032LV, so that a 4-transmission 4-reception LVDS interface is realized, a driver is enabled, external processing is reduced, a receiver is enabled, 100-ohm termination is performed, data acquisition is facilitated, internal enabling processing is performed on two chips, and board-level processing is reduced. As shown in fig. 9, the MLVDS interface circuit is composed of 8 channels of JRMLVD201 differential transceivers, and 8 receiver enable pins are connected in parallel to form an enable control signal, so as to implement 8 channels of MLVDS. The 429 interface circuit adopts 4 JHI8591 and 4 JHI8596 to realize 4-transmission 4-reception 429 bus interface, and performs pull-up processing on a driver SLP signal to select a fast mode as shown in FIG. 10.
The M1 micro component composition is shown in FIG. 11, which is the DSP minimum system. The M2 micro-component composition is shown in FIG. 12, and is the FPGA minimum system. The M3 micro component assembly is shown in fig. 13, and includes the ethernet interface, the 485 interface and the AD acquisition system. The M4 micro component assembly is shown in fig. 14, and includes the 429 interface and the level conversion interface. The M5 micro component is shown in fig. 15, and includes the CAN bus interface, the M-LVDS interface and the LVDS interface.
The microsystem chip configuration SIP provided by the invention adopts a PGA816 (FC) packaging form, can be directly welded on a printed board for use, and can also be led out for use by a ceramic tube shell or plastic package according to requirements. The SIP enables each power supply to be uniformly distributed on the leading-out end through a modular power supply management mode on the leading-out end, and the integrity of the power supplies is guaranteed; and the single-ended signal and the differential signal are separately led out on the lead-out, so that the signal interference is reduced, and the signal integrity is ensured.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (14)
1. A microsystem chip-on-a-chip configuration (SIP), comprising:
and a plurality of micro components are longitudinally stacked to form a micro system by adopting a TSV tube process, and are packaged and led out by a chip BGA, so that the chip configuration of the micro system is realized.
2. The microsystem chipforming SIP of claim 1, wherein the number of the microsystem chips is 5, the soldering is performed sequentially from bottom to top through the bonding pad and the BGA ball, and the gap of the middle soldering is filled with resin to form the final microsystem chipforming configuration.
3. The microsystem on-chip configuration SIP as claimed in claim 1 or 2, characterized in that the microsystem on-chip configuration SIP is integrated with a DSP minimal system, an FPGA minimal system, a CAN bus interface circuit, an ethernet interface circuit, a 485 interface circuit, an AD acquisition system, a level conversion interface, an LVDS bus interface, an MLVDS interface circuit and a 429 interface circuit.
4. The microsystem chip-on-chip SIP as claimed in claim 3, wherein the DSP minimum system comprises a digital signal processor FT-C6713J/400, a FLASH HRFL29208 and an SRAM JM64LV25616 implementing the loading and storing extensions of digital processing functions and programs, while internally uploading the HOLD signal of the DSP minimum system so that no external request is suspended.
5. A microsystem chip configuration SIP as claimed in claim 3, wherein the FPGA minimal system comprises one FPGA JXCLX25 and a configuration chip JXCF32P, implementing the processing of the interface and the pre-processing of the digital signals, internally pulling up the EN _ EXT _ SEL signal of JXCF32P, implementing the design partition controlled by an internal programmable partition selection control bit, the internal control being in parallel mode, enabling faster loading.
6. The microsystem chip-on-chip SIP as claimed in claim 3, wherein the ethernet interface circuit is composed of 4 JDP83848 and clock driver circuit JCK25081 to implement four-way ethernet; an interface bus of the four-channel Ethernet PHY and the MAC adopts an MII or RMII bus, and a single-path clock signal is expanded into 4 paths of clocks through a clock driving circuit JCK25081, so that the number of off-chip crystal oscillators is reduced.
7. A microsystem chip-on-chip configuration SIP as claimed in claim 3, wherein the 485 interface circuit comprises 4 JMAX3485 differential transceivers implementing a four-way 485 bus.
8. The microsystem chip configuration SIP as claimed in claim 3, wherein the AD acquisition system comprises 2 JAD7998 chips, 16 channels are expanded, JS3025 is used as a JAD7998 reference voltage source, JTXS0108 is used as a level conversion circuit, communication between the JAD7998 chip and various level controllers is achieved, a 12-bit 188KSPS sampling 16-channel ADC is achieved, and the microsystem chip configuration SIP is applicable to a measurement and control field needing multi-channel sampling, and an input signal range is 0-ref.
9. The microsystem chip-on-chip configuration SIP as recited in claim 3, wherein the CAN bus interface circuit is composed of 4 JMCP2551 with decoupling capacitors, and realizes a 4-way CAN bus.
10. A microsystem chip-on-chip configuration SIP as claimed in claim 3, characterized in that the MLVDS interface circuit consists of an 8-way JRMLVD201 differential transceiver.
11. The microsystem chip-on-chip configuration SIP as recited in claim 3, wherein the 429 interface circuit employs 4 JHI8591 and 4 JHI8596 to implement a 4-issue, 4-receive 429 bus interface.
12. A micro-system on-chip SIP according to claim 3, wherein the LVDS interface circuit implements a 4-transmit-4-receive LVDS interface using JSRLVDS031LV and JSRLVDS032 LV.
13. The microsystem chip-on-chip configuration SIP as claimed in claim 3, wherein the level conversion interface circuit adopts 3-chip JALVC164245 to realize 24-bit dual-channel level conversion.
14. The microsystem chip configuration SIP according to claim 1, wherein the microcomponent is prepared by the following method: after the PADs of the required chips are placed upwards, each PAD needing interconnection is punched and led out, then lead interconnection is carried out, according to required wiring complexity, a punching layer and a wiring layer are added, all interconnection is completed, then an upper surface PAD is led out, lower surface ball planting is led out, resin filling is carried out on the upper surface PAD, a single micro component is formed, and the top micro component only carries out lower surface ball planting and leading out.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011180245.9A CN112242389A (en) | 2020-10-29 | 2020-10-29 | Micro-system chip configuration SIP |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011180245.9A CN112242389A (en) | 2020-10-29 | 2020-10-29 | Micro-system chip configuration SIP |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN112242389A true CN112242389A (en) | 2021-01-19 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011180245.9A Withdrawn CN112242389A (en) | 2020-10-29 | 2020-10-29 | Micro-system chip configuration SIP |
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|---|---|
| CN (1) | CN112242389A (en) |
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2020
- 2020-10-29 CN CN202011180245.9A patent/CN112242389A/en not_active Withdrawn
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Application publication date: 20210119 |