CN112234035A - 半导体封装结构及其形成方法 - Google Patents
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Abstract
本发明实施例提供了一种半导体封装结构,包括:内埋式基板;扇出结构,位于内埋式基板上方;第一导电通孔,贯穿整个扇出结构并且与内埋式基板中的第一芯片的第一接合垫连接。本申请的实施例另一方面提供一种形成半导体封装结构的方法。本申请的实施例至少提高了半导体封装结构的良率。
Description
技术领域
本发明涉及领域半导体领域,具体地,涉及一种半导体封装结构及其形成方法。
背景技术
现有的量产的衬底无法实现线路层的线宽/间距为较大,并且其通孔尺寸较大。在现有技术中,芯片内埋于衬底在进行后续的扇出或集成工艺时容易受到翘曲的影响,造成制程上的困难。并且翘曲会导致最终产品的良率下降。
发明内容
针对相关技术中存在的问题,本发明的目的在于提供一种半导体封装结构及其形成方法,以提高半导体封装结构的良率。
为实现上述目的,本发明提供了一种半导体封装结构,包括:内埋式基板;扇出结构,位于内埋式基板上方;第一导电通孔,贯穿整个扇出结构并且与内埋式基板中的第一芯片的第一接合垫连接。
根据本发明的实施例,内埋式基板还包括包围第一芯片的第一模塑材料;扇出结构位于第一模塑材料的上方,其中,第一导电通孔贯穿扇出结构中的介电层,并且穿过第一模塑材料以直接连接第一接合垫。
根据本发明的实施例,还包括:粘合层,内埋式基板通过粘合层和扇出结构粘合在一起,第一导电通孔还贯穿粘合层。
根据本发明的实施例,还包括:第二导电通孔,内埋式基板还包括第一线路层,由第一模塑材料覆盖;其中,第二导电通孔依次贯穿介电层、粘合层以及第一模塑材料以直接连接至第一线路层,第二导电通孔与第一芯片横向间隔开。
根据本发明的实施例,第二导电通孔设置在第一导电通孔和第一芯片的外围。
根据本发明的实施例,扇出结构包括:由介电层掩埋的底部线路层;从介电层的上表面暴露的顶部线路层,底部线路层和顶部线路层上下间隔开,第一导电通孔贯穿并且电连接底部线路层和顶部线路层。
根据本发明的实施例,第一导电通孔所穿过的顶部线路层的开口,大于所穿过的底部线路层的开口。
根据本发明的实施例,第一导电通孔所穿过的顶部线路层的开口、以及第一导电通孔所穿过的底部线路层的开口,均为上宽下窄的截锥形开口,第一导电通孔为上宽下窄的截锥形。
根据本发明的实施例,顶部线路层的与第一导电通孔接触的部分,在俯视时呈环形形状。
根据本发明的实施例,扇出结构中线路的线宽和间距,分别小于内埋式基板中线路的线宽和间距。
根据本发明的实施例,扇出结构中线路层的层数小于等于2,内埋式基板中线路层的层数小于等于4。
根据本发明的实施例,半导体封装结构为系统级封装结构。
根据本发明的实施例,还包括:第二芯片,位于扇出结构上并且电连接第一导电通孔;第二模塑材料,覆盖第二芯片。
本发明的实施例另一方面提供一种形成半导体结构的方法,包括:提供内埋式基板;将扇出结构设置在内埋式基板上方;形成贯穿扇出结构的第一导电通孔,以将扇出结构直接电连接至内埋式基板中的第一芯片。
根据本发明的实施例,通过粘合层将将扇出结构粘合在内埋式基板上方,形成第一导电通孔包括:形成依次贯穿扇出结构中所有的线路层、粘合层直至露出第一芯片的接合垫的第一开孔;在第一开孔中填充导电材料以形成第一导电通孔。
根据本发明的实施例,第一开孔为激光钻孔。
根据本发明的实施例,第一芯片被模塑材料包围,在形成第一开孔的同时,形成依次贯穿扇出结构、粘合层和模塑材料直至露出内埋式基板的线路层的第二开孔,使用导电材料填充第二开孔,以将扇出结构电连接至内埋式基板的线路层。
根据本发明的实施例,第二开孔设置在第一开孔以及第一芯片的外围。
根据本发明的实施例,通过电镀的方式在第一开孔和第二开孔中填充导电材料。
根据本发明的实施例,扇出结构中线路层的层数小于等于2,内埋式基板中线路层的层数小于等于4。
本发明的有益技术效果在于:
本申请的内埋式基板和扇出结构的形成方法及结构,克服了翘曲的影响,提高了产品的良率。
附图说明
当结合附图进行阅读时,从以下详细描述可最佳地理解本发明的各个方面。应该注意,根据工业中的标准实践,各个部件未按比例绘制。实际上,为了清楚的讨论,各种部件的尺寸可以被任意增大或减小。
图1至图7示出了根据本申请的实施例的制造半导体封装结构的结构示意图。
具体实施方式
为更好的理解本申请实施例的精神,以下结合本申请的部分优选实施例对其作进一步说明。
本申请的实施例将会被详细的描示在下文中。在本申请说明书全文中,将相同或相似的组件以及具有相同或相似的功能的组件通过类似附图标记来表示。在此所描述的有关附图的实施例为说明性质的、图解性质的且用于提供对本申请的基本理解。本申请的实施例不应该被解释为对本申请的限制。
如本文中所使用,术语“大致”、“大体上”、“实质”及“约”用以描述及说明小的变化。当与事件或情形结合使用时,所述术语可指代其中事件或情形精确发生的例子以及其中事件或情形极近似地发生的例子。举例来说,当结合数值使用时,术语可指代小于或等于所述数值的±10%的变化范围,例如小于或等于±5%、小于或等于±4%、小于或等于±3%、小于或等于±2%、小于或等于±1%、小于或等于±0.5%、小于或等于±0.1%、或小于或等于±0.05%。举例来说,如果两个数值之间的差值小于或等于所述值的平均值的±10%(例如小于或等于±5%、小于或等于±4%、小于或等于±3%、小于或等于±2%、小于或等于±1%、小于或等于±0.5%、小于或等于±0.1%、或小于或等于±0.05%),那么可认为所述两个数值“大体上”相同。
在本说明书中,除非经特别指定或限定之外,相对性的用词例如:“中央的”、“纵向的”、“侧向的”、“前方的”、“后方的”、“右方的”、“左方的”、“内部的”、“外部的”、“较低的”、“较高的”、“水平的”、“垂直的”、“高于”、“低于”、“上方的”、“下方的”、“顶部的”、“底部的”以及其衍生性的用词(例如“水平地”、“向下地”、“向上地”等等)应该解释成引用在讨论中所描述或在附图中所描示的方向。这些相对性的用词仅用于描述上的方便,且并不要求将本申请以特定的方向建构或操作。
另外,有时在本文中以范围格式呈现量、比率和其它数值。应理解,此类范围格式是用于便利及简洁起见,且应灵活地理解,不仅包含明确地指定为范围限制的数值,而且包含涵盖于所述范围内的所有个别数值或子范围,如同明确地指定每一数值及子范围一般。
再者,为便于描述,“第一”、“第二”、“第三”等等可在本文中用于区分一个图或一系列图的不同组件。“第一”、“第二”、“第三”等等不意欲描述对应组件。
现有技术的基板量产化尚无法做到10μm/10μm线路与小于60μm的通孔。现有的内埋式基板具有多层线路层,在进行后续扇出或集成芯片时容易受到翘曲的影响,使得制造难度增加。因此,现有的半导体封装结构的内埋式基板良率低。以下根据图1至图7对本申请的半导体封装结构100进行阐述。
参见图1和图2,分别制作内埋式基板10、以及扇出结构12,扇出结构12的底面粘附有粘合层14。内埋式基板10具有内埋在内埋式基板10的第一模塑材料18中的第一芯片16。在实施例中,第一模塑材料18为单一材料。
参见图3,使用粘合层14将扇出结构12粘接到内埋式基板10上。在实施例中,第一模塑材料18包括第一层181以及位于第一层181上方的第二层182。在制作过程中,先形成第一层181,将第一芯片16放置在第一层181上,再形成覆盖第一层181以及第一芯片16的第二层182。
参见图4,形成穿过扇出结构12、粘合层14以及第一模塑材料18的部分以暴露第一芯片16的接合垫161的第一开口202,并且同时的,形成穿过扇出结构12、粘合层14以及第一模塑材料18以暴露内埋式基板10的第一线路层103的第一开口204。
参见图5,在第一开口202和第二开口204中填充导电材料205,以在第一开口202和第二开口204中形成第一通孔201和第二通孔203。导电材料205还形成在扇出结构12的上方。第一通孔201直接地连接于第一芯片16的接合垫161。
参见图6,将位于扇出结构12上方的导电材料205图案化,形成扇出结构12的顶部线路层125。
参见图7,使用连接件262将第二芯片26电连接至顶部线路层125,并使用第二模塑材料28包封第二芯片26。在实施例中,连接件262可以是焊料凸块。
本发明的实施例提供了一种半导体封装结构100,包括:内埋式基板10;扇出结构12,位于内埋式基板10上方;第一导电通孔201,贯穿整个扇出结构12并且与内埋式基板10中的第一芯片16的第一接合垫161连接。在实施例中,内埋式基板10还包括包围第一芯片16的第一模塑材料18;扇出结构12位于第一模塑材料18的上方,其中,第一导电通孔201贯穿扇出结构12中的介电层121,并且穿过第一模塑材料18以直接连接第一接合垫161。在实施例中,介电层121的材料可以是聚酰亚胺(polyimide,PI)。在实施例中,还包括:粘合层14,内埋式基板10通过粘合层14和扇出结构12粘合在一起,第一导电通孔201还贯穿粘合层14。在实施例中,还包括:第二导电通孔202,内埋式基板10还包括第一线路层103,由第一模塑材料18覆盖;其中,第二导电通孔202依次贯穿介电层121、粘合层14以及第一模塑材料18以直接连接至第一线路层103,第二导电通孔202与第一芯片16横向间隔开。在实施例中,第二导电通孔202设置在第一导电通孔201和第一芯片16的外围。在实施例中,扇出结构12包括:由介电层121掩埋的底部线路层123;从介电层121的上表面暴露的顶部线路层125,底部线路层123和顶部线路层125上下间隔开,第一导电通孔201贯穿并且电连接底部线路层203和顶部线路层205。在实施例中,第一导电通孔201所穿过的顶部线路层205的开口,大于第一导电通孔201所穿过的底部线路层123的开口。在实施例中,顶部线路层125中的开口的直径小于60μm,低部线路层123中的开口的直径小于55μm。在实施例中,第一导电通孔201所穿过的顶部线路层125的开口、以及第一导电通孔201所穿过的底部线路层123的开口,均为上宽下窄的截锥形开口,第一导电通孔201为上宽下窄的截锥形。在实施例中,顶部线路层125的与第一导电通孔201接触的部分,在俯视时呈环形形状。在实施例中,扇出结构12中线路的线宽和间距,分别小于内埋式基板10中线路的线宽和间距。在实施例中,扇出结构12中线路层的层数小于等于2,内埋式基板10中线路层的层数小于等于4。在实施例中,半导体封装结构100为系统级封装结构。在实施例中,还包括:第二芯片26,位于扇出结构上并且电连接第一导电通孔;第二模塑材料28,覆盖第二芯片26。
本发明的实施例另一方面提供一种形成半导体结构的方法,包括:提供内埋式基板10;将扇出结构12设置在内埋式基板10上方;形成贯穿扇出结构的第一导电通孔201,以将扇出结构12直接电连接至内埋式基板10中的第一芯片16。在实施例中,通过粘合层14将将扇出结构12粘合在内埋式基板10上方,形成第一导电通孔201包括:形成依次贯穿扇出结构12中所有的线路层123、125、粘合层14直至露出第一芯片16的接合垫161的第一开孔202;在第一开孔202中填充导电材料205以形成第一导电通孔201。在实施例中,第一开孔202为激光钻孔。在实施例中,第一芯片16被模塑材料18包围,在形成第一开孔202的同时,形成依次贯穿扇出结构12、粘合层14和模塑材料18直至露出内埋式基板10的线路层103的第二开孔204,使用导电材料205填充第二开孔204,以将扇出结构12电连接至内埋式基板10的线路层103。在实施例中,第二开孔204设置在第一开孔202以及第一芯片16的外围。在实施例中,通过电镀的方式在第一开孔202和第二开孔204中填充导电材料205。在实施例中,扇出结构12中线路层的层数小于等于2,内埋式基板10中线路层的层数小于等于4。
以上所述仅为本发明的优选实施例而已,并不用于限制本发明,对于本领域的技术人员来说,本发明可以有各种更改和变化。凡在本发明的精神和原则之内,所作的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。
Claims (10)
1.一种半导体封装结构,其特征在于,包括:
内埋式基板;
扇出结构,位于所述内埋式基板上方;
第一导电通孔,贯穿整个所述扇出结构并且与所述内埋式基板中的第一芯片的第一接合垫连接。
2.根据权利要求1所述的半导体封装结构,其特征在于,
所述内埋式基板还包括包围所述第一芯片的第一模塑材料;
所述扇出结构位于所述第一模塑材料的上方,
其中,所述第一导电通孔贯穿所述扇出结构中的介电层,并且穿过所述第一模塑材料以直接连接所述第一接合垫。
3.根据权利要求2所述的半导体封装结构,其特征在于,还包括:
粘合层,所述内埋式基板通过所述粘合层和所述扇出结构粘合在一起,所述第一导电通孔还贯穿所述粘合层。
4.根据权利要求3所述的半导体封装封装结构,其特征在于,还包括:
第二导电通孔,
所述内埋式基板还包括第一线路层,由所述第一模塑材料覆盖;
其中,所述第二导电通孔依次贯穿所述介电层、所述粘合层以及所述第一模塑材料以直接连接至所述第一线路层,所述第二导电通孔与所述第一芯片横向间隔开。
5.根据权利要求4所述的半导体封装封装结构,其特征在于,
所述第二导电通孔设置在所述第一导电通孔和所述第一芯片的外围。
6.根据权利要求1所述的半导体封装封装结构,其特征在于,所述扇出结构包括:
由所述介电层掩埋的底部线路层;
从所述介电层的上表面暴露的顶部线路层,所述底部线路层和所述顶部线路层上下间隔开,
所述第一导电通孔贯穿并且电连接所述底部线路层和所述顶部线路层。
7.根据权利要求1所述的半导体结构,其特征在于,
所述扇出结构中线路的线宽和间距,分别小于所述内埋式基板中线路的线宽和间距。
8.根据权利要求1所述的半导体封装结构,其特征在于,还包括:
第二芯片,位于所述扇出结构上并且电连接所述第一导电通孔;
第二模塑材料,覆盖所述第二芯片。
9.一种形成半导体结构的方法,其特征在于,包括:
提供内埋式基板;
将扇出结构设置在所述内埋式基板上方;
形成贯穿所述扇出结构的第一导电通孔,以将所述扇出结构直接电连接至所述内埋式基板中的第一芯片。
10.根据权利要求9所述的形成半导体结构的方法,其特征在于,
通过粘合层将所述将扇出结构粘合在所述内埋式基板上方,
形成所述第一导电通孔包括:
形成依次贯穿所述扇出结构中所有的线路层、所述粘合层直至露出所述第一芯片的接合垫的第一开孔;
在所述第一开孔中填充导电材料以形成所述第一导电通孔。
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