CN112201189A

CN112201189A - Potential shift circuit and display device with same

Info

Publication number: CN112201189A
Application number: CN202010947323.7A
Authority: CN
Inventors: 黄柏文; 卓均勇
Original assignee: Tianyu Technology Co ltd
Current assignee: Tianyu Technology Co ltd
Priority date: 2020-09-10
Filing date: 2020-09-10
Publication date: 2021-01-08
Anticipated expiration: 2040-09-10

Abstract

A level shift circuit and a display device include a differential input circuit, a current limiting circuit, a latch circuit and a voltage shielding circuit. The voltage shielding circuit includes first to fourth shielding transistors. The first shielding transistor and the second shielding transistor are connected in series between the differential input circuit and the second output terminal, and the third shielding transistor and the fourth shielding transistor are connected in series between the differential input circuit and the first output terminal. Gates of the first and third shield transistors receive a first voltage, and gates of the second and fourth shield transistors receive a second voltage that is less than the first voltage. The substrates of the first shield transistor and the third shield transistor receive a third voltage and the substrates of the second shield transistor and the fourth shield transistor receive a fourth voltage that is greater than the third voltage.

Description

Potential shift circuit and display device with same

Technical Field

The invention relates to a potential shift circuit and a display device with the same.

Background

A display generally includes a display panel and a display driving circuit for driving the display panel to display an image. The driving circuit disposed in the non-display region generally has a potential shift circuit. The potential translation circuit is used for converting a signal of a low voltage domain into a signal of a high voltage domain or converting a signal of the high voltage domain into a signal of a low voltage domain, so as to realize signal transmission in different voltage domains. The level shift circuit comprises a differential input circuit, a latch circuit, a current limiting circuit and a voltage shielding circuit. The differential input circuit includes a forward input terminal and a reverse input terminal. The latch circuit includes a forward output terminal and a reverse output terminal. The current limiting circuit is used for limiting the current flowing through the transistor. In a single-stage to full positive voltage potential shift circuit composed of half-press process elements, a potential shielding circuit is the key point for protecting the half-press process elements so as to protect the whole circuit in a correct operating voltage range. Typically, the shield voltage is set near the medium voltage, and the substrate voltage of the transistors in the potential shield circuit will also be near the medium voltage. However, the closer the shield voltage is to the medium voltage, the slower the transition speed of the potential shift circuit is, and when the shield voltage is kept away from the medium voltage in order to increase the transition speed of the potential shift circuit, the problem of substrate leakage of the shield transistor is caused by the shield point between the potential shield circuit and the differential input circuit, and how to achieve the transition speed and prevent the shield transistor leakage is an urgent technical problem to be solved.

Disclosure of Invention

In view of the above, it is desirable to provide a level shift circuit and a display device having the same, which are capable of solving the technical problems of the prior art that the transition speed is high and the leakage of the shielding transistor is prevented.

A level shift circuit is used for converting a signal of a low voltage domain into a signal of a high voltage domain; the potential shift circuit includes:

a differential input circuit having a first input transistor and a second input transistor;

a latch circuit having a first output terminal and a second output terminal;

the current limiting circuit is electrically connected with the bolt-lock circuit; the current limiting circuit is used for limiting the current flowing through the latch circuit;

the voltage shielding circuit is electrically connected between the differential input circuit and the bolt-lock circuit; the voltage shielding circuit comprises a first shielding transistor, a second shielding transistor, a third shielding transistor and a fourth shielding transistor; the first shielding transistor and the second shielding transistor are connected in series between the first input transistor and the second output end, and the source electrode of the first shielding transistor is electrically connected with the source electrode of the second shielding transistor; the third shielding transistor and the fourth shielding transistor are connected in series between the second input transistor and the first output end, and the source electrode of the third shielding transistor is electrically connected with the source electrode of the fourth shielding transistor; the gate of the first shield transistor and the gate of the third shield transistor receive a first voltage, and the gate of the second shield transistor and the gate of the fourth shield transistor receive a second voltage; the substrate of the first shield transistor and the substrate of the third shield transistor receive a third voltage, and the substrate of the second shield transistor and the substrate of the fourth shield transistor receive a fourth voltage; wherein the first voltage is greater than the second voltage; the fourth voltage is greater than the third voltage.

A display device has a potential shift circuit; the potential translation circuit converts a signal of a low voltage domain into a signal of a high voltage domain; the potential shift circuit includes:

a latch circuit having a first output terminal and a second output terminal;

the current limiting circuit receives the driving voltage and is electrically connected with the bolt-lock circuit; the current limiting circuit is used for limiting the current flowing through the latch circuit;

Based on the potential shift circuit with the structure and the display device with the potential shift circuit, the third voltage is provided on the substrates of the first shielding transistor and the third shielding transistor, the fourth voltage is provided on the substrates of the second shielding transistor and the fourth shielding transistor, and the fourth voltage is set to be larger than the third voltage so as to enlarge the reverse bias range of the PN junction surface of the transistor substrate in the potential shielding circuit, so that the voltage difference between the first voltage and the second voltage of the potential shielding circuit can be designed to be enlarged, and the conversion speed of the potential shift circuit is improved.

Drawings

FIG. 1 is a block diagram of a display device according to a preferred embodiment.

Fig. 2 is a block diagram of the level shift circuit of fig. 1.

Fig. 3 is an equivalent circuit diagram of the level shift circuit in fig. 2.

Description of the main elements

Display device 100

Scan driving circuit 110

Data driving circuit 120

Timing controller 130

Display area 101

Non-display area 103

Scanning line S₁-S_n

Data line D₁-D_m

Pixel unit 20

Level shift circuit 200

Differential input circuit 201

Latch circuit 203

Current limiting circuit 205

Voltage shielding circuit 207

A first input terminal IN

Second input terminal INB

First input transistor M1

Second input transistor M2

First output transistor M3

Second output transistor M4

First output terminal OUT

Second output terminal OUTB

First transistor M5

Second transistor M6

First shield transistor M7

Second shield transistor M8

Third shield transistor M9

Fourth shield transistor M10

First node N1

Second node N2

Third node N3

Fourth node N4

First voltage V1

Second voltage V2

Third voltage V3

Fourth voltage V4

Supply voltage AVDD

Bias voltage VP

The following detailed description will further illustrate the invention in conjunction with the above-described figures.

Detailed Description

In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The terms "first", "second", and "third", etc. in the description of the present invention and the above-described drawings are used for distinguishing between different objects and not for describing a particular order. Furthermore, the terms "comprises" and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or modules is not limited to the listed steps or modules but may alternatively include other steps or modules not listed or inherent to such process, method, article, or apparatus.

The following describes embodiments of a potential shift circuit and a display device having the potential shift circuit according to the present invention with reference to the drawings. Referring to fig. 1, fig. 1 is a schematic diagram of an equivalent module of a display device 100 according to an embodiment of the invention. The display device 100 is defined with a display area 101 and a non-display area 103 disposed around the display area 101. The display region 101 includes a plurality of scan lines S₁-S_nAnd a plurality of data lines D₁-D_m. Wherein n and m are positive integers. Multiple scanning lines S₁-S_nExtend along the first direction X and are arranged in parallel to each other, and a plurality of data lines D₁-D_mExtending along a second direction Y and arranged in parallel to each other, a plurality of scan lines S₁-S_nAnd a plurality of data lines D₁-D_mAre insulated from each other and arranged in a grid-crossing mannerA plurality of pixel cells 20 are defined in a matrix arrangement.

The display device 100 includes a scan driving circuit 110, a data driving circuit 120, and a timing controller 130. Each column of pixel units 20 passes through a scanning line S_nElectrically connected to the scan driving circuit 110, each row of pixel units 20 passes through a data line D_mIs electrically connected to the data driving circuit 120. The timing controller 130 is electrically connected to the scan driving circuit 110 and the data driving circuit 120, respectively. The timing controller 130 generates a plurality of synchronization control signals to the scan driving circuit 110 and the data driving circuit 120. The plurality of synchronization control signals may include a periodic synchronization control signal and a non-periodic synchronization control signal. The plurality of synchronization control signals include a Vertical synchronization (Vsync) signal, a Horizontal synchronization (Hsync) signal, and a Data Enable (DE) signal. In the present embodiment, the timing controller 130 supplies a clock signal to the scan driving circuit 110. The scan driving circuit 110 provides scan signals to the plurality of scan lines S₁-S_nTo scan the pixel cells 20. The data driving circuit 120 is for supplying image signals to the plurality of data lines D₁-D_mTo display the image. The image signal is a digital signal, and is composed of a low level (e.g., logic 0) and a high level (e.g., logic 1). In this embodiment, the scan driving circuit 110 is disposed above the display region, and the data driving circuit 120 is disposed on the left side of the display region.

The data driving circuit 120 includes a potential shift circuit 200. Fig. 2 is a block diagram of a level shift circuit 200 according to the present invention. The level shift circuit 200 is configured to convert the image signal in the low voltage domain into a conversion signal in the high voltage domain and provide the conversion signal to the pixel unit 20. In at least one embodiment of the present invention, the level shift circuit 200 is applied to a circuit structure formed by half-pressure process elements. In at least one embodiment of the invention, the supply voltage AVDD in the high voltage domain may be greater than the supply voltage in the low voltage domain. The high voltage domain may include a low level, an intermediate level, and a high level. Wherein the intermediate level is between the low level and the high level. In at least one embodiment of the present invention, in the high voltage domain, the low level may be 0 volt, the middle level may be 6 volts, and the high level may be 12 volts; in the low voltage domain, the low level may be 0 volts and the high level may be 1.8 volts. In other embodiments, the intermediate level in the high voltage domain may also be set to other values as desired. The level shifter circuit 200 includes a differential input circuit 201, a latch circuit 203, a current limiting circuit 205, and a voltage shielding circuit 207.

Fig. 3 is an equivalent circuit diagram of the level shift circuit 200.

The differential input circuit 201 has a first input terminal IN and a second input terminal INB. The input signal is provided to the first input terminal IN, and is inverted by an inverter (not shown) and provided to the second input terminal INB. The differential input circuit 201 includes a first input transistor M1 and a second input transistor M2. The gate of the first input transistor M1 is electrically connected to the first input terminal IN, the gate of the first input transistor M1 is electrically connected to the second input terminal INB, the source of the first input transistor M1 and the source of the second input transistor M2 are both electrically connected to the ground, and the drain of the first input transistor M1 and the drain of the second input transistor M2 are respectively electrically connected to the voltage shielding circuit 207. In at least one embodiment of the present invention, the first and second input transistors M1 and M2 may be NMOS transistors.

The latch circuit 203 has a first output terminal OUT and a second output terminal OUTB. The latch circuit 203 includes a first output transistor M3 and a second output transistor M4. The gate of the first output transistor M3 is electrically connected to the first output terminal OUT, the gate of the second output transistor M4 is electrically connected to the second output terminal OUTB, the source of the first output transistor M3 and the source of the second output transistor M4 are simultaneously electrically connected to the current limiting circuit 205, the drain of the first output transistor M3 is electrically connected to the second output terminal OUTB, and the drain of the second output transistor M4 is electrically connected to the first output terminal OUT. In at least one embodiment of the present invention, the first output transistor M3 and the second output transistor M4 may be PMOS transistors.

The current limiting circuit 205 is electrically connected to the latch circuit 203. The current limiting circuit 205 is used to limit the current flowing through the first output transistor M3 and the second output transistor M4. The current limiting circuit 205 includes a first transistor M5 and a second transistor M6. The gate of the first transistor M5 and the gate of the second transistor M6 receive the bias voltage VP. The source of the first transistor M5 and the source of the second transistor M6 receive the power supply voltage AVDD, respectively. The drain of the first transistor M5 is electrically connected to the source of the first output transistor M3, and the drain of the second transistor M6 is electrically connected to the source of the second output transistor M4. In at least one embodiment of the present invention, the first transistor M5 and the second transistor M6 may be PMOS transistors.

The voltage shielding circuit 207 is electrically connected between the differential input circuit 201 and the latch circuit 203. The voltage shielding circuit 207 is used for controlling the switching speed of the level shift circuit 200 according to the first voltage V1 and the second voltage V2. The voltage shielding circuit 207 includes a first shielding transistor M7, a second shielding transistor M8, a third shielding transistor M9, and a fourth shielding transistor M10. The first and second shielding transistors M7 and M8 are connected in series between the drain of the first input transistor M1 and the second output terminal OUTB, and the third and fourth shielding transistors M9 and M10 are connected in series between the drain of the second input transistor M2 and the first output terminal OUT. The gates of the first and third shielding transistors M7 and M9 receive the first voltage V1, and the gates of the second and fourth shielding transistors M8 and M10 receive the second voltage V2. The first voltage V1 is greater than the second voltage V2. The source of the first shielding transistor M7 is electrically connected to the source of the second shielding transistor M8 through a third node N3, and the source of the third shielding transistor M9 is electrically connected to the source of the fourth shielding transistor M10 through a fourth node N4. The drain of the first shielding transistor M7 is electrically connected to the second output terminal OUTB. The drain of the second shielding transistor M8 is electrically connected to the drain of the first input transistor M1 via a first node N1. The drain of the third shielding transistor M9 is electrically connected to the first output terminal OUT. The drain of the fourth shielding transistor M10 is electrically connected to the drain of the second input transistor M2 via a second node N2. The substrate of the first shield transistor M7 and the substrate of the third shield transistor M9 receive a third voltage V3, and the substrate of the second shield transistor M8 and the substrate of the fourth shield transistor M10 receive a fourth voltage V4. Wherein the third voltage V3 is less than the fourth voltage V4. In at least one embodiment of the present invention, the first and third shielding transistors M7 and M9 may be NMOS transistors, and the second and fourth shielding transistors M8 and M10 may be PMOS transistors. In at least one embodiment of the present invention, one of the third voltage V3 and the fourth voltage V4 may be set to an intermediate level. When the third voltage V3 is at the middle level, the fourth voltage V4 is greater than the middle level. When the fourth voltage V4 is at the middle level, the third voltage V3 is smaller than the middle level.

In the process of switching the input signal of the low voltage domain from the low level to the high level, the first input transistor M1 is turned on gradually, and the second input transistor M2 is turned off gradually. The voltage of the third node N3 gradually decreases until the potential of the third node N3 is the sum of the second voltage V2 and the threshold voltage VTH of the second shield transistor M8. At the same time, the voltage of the second output terminal OUTB in the latch circuit 203 also gradually decreases to a voltage close to the third node N3. Therefore, the voltage of the fourth node N4 gradually rises until the potential of the fourth node becomes the difference between the first voltage V1 and the threshold voltage VTH of the third shield transistor M9. In the process of switching the input signal in the low voltage domain from the high level to the low level, the second input transistor M2 is turned on gradually, and the first input transistor M1 is turned off gradually. The voltage of the fourth node N4 gradually decreases until the potential of the fourth node becomes the sum of the second voltage V2 and the threshold voltage VTH of the fourth shield transistor M10. Meanwhile, the voltage of the first output terminal OUT of the latch circuit 203 also gradually decreases to approach the voltage of the fourth node N4, and therefore, the voltage of the third node N3 gradually increases until the voltage of the third node N3 is the difference between the first voltage V1 and the threshold voltage VTH of the first shielding transistor M7. To improve the transition speed, the first voltage V1 and the second voltage V2 are usually far from the middle level, and the PN junction between the substrates of the first to fourth shielding transistors M7-M10 is controlled to be reversely biased by designing the appropriate third voltage V3 and fourth voltage V4, so as to prevent the first to fourth shielding transistors M7-M10 from leaking. Meanwhile, after the first voltage V1 and the second voltage V2 are designed according to the required state transition speed, the voltages of the third node N3 and the fourth node N4 can be between the first voltage V1 and the second voltage V2 by setting the first voltage V1 to be equal to the fourth voltage V4 and setting the second voltage V2 to be the same as the third voltage V3. Meanwhile, since the first voltage V1 is equal to the fourth voltage V4, and the second voltage V2 is equal to the third voltage V3, the PN junction between the substrates of the first to fourth shield transistors M7-M10 is also controlled to be reversely biased, thereby preventing the leakage of the first to fourth shield transistors M7-M10. The method can simultaneously take the consideration of both the state transition speed and the electric leakage into consideration.

It will be appreciated by those skilled in the art that the above embodiments are illustrative only and not intended to be limiting, and that suitable modifications and variations may be made to the above embodiments without departing from the true spirit and scope of the invention.

Claims

1. A level shift circuit is used for converting a signal of a low voltage domain into a signal of a high voltage domain; the method is characterized in that: the potential shift circuit includes:

a latch circuit having a first output terminal and a second output terminal;

2. The potential shift circuit of claim 1, wherein: the high voltage domain comprises a low level, a middle level and a high level; the intermediate level is greater than the low level and less than the high level; the third voltage is at an intermediate level.

3. The potential shift circuit of claim 1, wherein: the high voltage domain comprises a low level, a middle level and a high level; the intermediate level is greater than the low level and less than the high level; the fourth voltage is at an intermediate level.

4. The potential shift circuit of claim 1, wherein: the first voltage is equal to the third voltage, and the second voltage is equal to the fourth voltage.

5. The potential shift circuit of claim 1, wherein: the first shielding transistor and the third shielding transistor are N-type transistors, and the second shielding transistor and the fourth shielding transistor are P-type transistors.

6. The potential shift circuit of claim 1, wherein: the grid electrode of the first input transistor is electrically connected with the first input end, the source electrode of the first input transistor receives a grounding voltage, and the drain electrode of the first input transistor is electrically connected with the drain electrode of the second shielding transistor; the grid electrode of the second input transistor is electrically connected with the second input end, the source electrode of the second input transistor receives the grounding voltage, and the drain electrode of the second input transistor is electrically connected with the drain electrode of the fourth shielding transistor.

7. A display device with a potential shift circuit includes a potential shift circuit; the potential translation circuit is used for converting a signal of a low voltage domain into a signal of a high voltage domain; the method is characterized in that: the potential shift circuit includes:

a latch circuit having a first output terminal and a second output terminal;

the voltage shielding circuit is electrically connected between the differential input circuit and the bolt-lock circuit; the voltage shielding circuit comprises a first shielding transistor, a second shielding transistor, a third shielding transistor and a fourth shielding transistor; the first shielding transistor and the second shielding transistor are connected in series between the first input transistor and the second output end, and the source electrode of the first shielding transistor is electrically connected with the source electrode of the second shielding transistor; the third shielding transistor and the fourth shielding transistor are connected in series between the second input transistor and the first output end, and the source electrode of the third shielding transistor is electrically connected with the source electrode of the fourth shielding transistor; the gate of the first shield transistor and the gate of the third shield transistor receive a first voltage, and the gate of the second shield transistor and the gate of the fourth shield transistor receive a second voltage; the substrate of the first shield transistor and the substrate of the third shield transistor receive a third voltage, and the substrate of the second shield transistor and the substrate of the fourth shield transistor receive a fourth voltage; wherein the first voltage is greater than the second voltage; the third voltage is greater than the fourth voltage.

8. The display device of claim 7, wherein: the high voltage domain comprises a low level, a middle level and a high level; the intermediate level is greater than the low level and less than the high level; the third voltage is at an intermediate level.

9. The display device of claim 7, wherein: the high voltage domain comprises a low level, a middle level and a high level; the intermediate level is greater than the low level and less than the high level; the fourth voltage is at an intermediate level.

10. The display device of claim 7, wherein: the first voltage is equal to the third voltage, and the second voltage is equal to the fourth voltage.